1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 Waldorf GMBH 7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle 8 * Copyright (C) 1996 Paul M. Antoine 9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_PROCESSOR_H 12 #define _ASM_PROCESSOR_H 13 14 #include <linux/cpumask.h> 15 #include <linux/threads.h> 16 17 #include <asm/cachectl.h> 18 #include <asm/cpu.h> 19 #include <asm/cpu-info.h> 20 #include <asm/mipsregs.h> 21 #include <asm/prefetch.h> 22 23 /* 24 * Return current * instruction pointer ("program counter"). 25 */ 26 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 27 28 /* 29 * System setup and hardware flags.. 30 */ 31 32 extern unsigned int vced_count, vcei_count; 33 34 /* 35 * MIPS does have an arch_pick_mmap_layout() 36 */ 37 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 38 39 #ifdef CONFIG_32BIT 40 #ifdef CONFIG_KVM_GUEST 41 /* User space process size is limited to 1GB in KVM Guest Mode */ 42 #define TASK_SIZE 0x3fff8000UL 43 #else 44 /* 45 * User space process size: 2GB. This is hardcoded into a few places, 46 * so don't change it unless you know what you are doing. 47 */ 48 #define TASK_SIZE 0x80000000UL 49 #endif 50 51 #define STACK_TOP_MAX TASK_SIZE 52 53 #define TASK_IS_32BIT_ADDR 1 54 55 #endif 56 57 #ifdef CONFIG_64BIT 58 /* 59 * User space process size: 1TB. This is hardcoded into a few places, 60 * so don't change it unless you know what you are doing. TASK_SIZE 61 * is limited to 1TB by the R4000 architecture; R10000 and better can 62 * support 16TB; the architectural reserve for future expansion is 63 * 8192EB ... 64 */ 65 #define TASK_SIZE32 0x7fff8000UL 66 #ifdef CONFIG_MIPS_VA_BITS_48 67 #define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits)) 68 #else 69 #define TASK_SIZE64 0x10000000000UL 70 #endif 71 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 72 #define STACK_TOP_MAX TASK_SIZE64 73 74 #define TASK_SIZE_OF(tsk) \ 75 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 76 77 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR) 78 79 #endif 80 81 #define STACK_TOP (TASK_SIZE & PAGE_MASK) 82 83 /* 84 * This decides where the kernel will search for a free chunk of vm 85 * space during mmap's. 86 */ 87 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) 88 89 90 #define NUM_FPU_REGS 32 91 92 #ifdef CONFIG_CPU_HAS_MSA 93 # define FPU_REG_WIDTH 128 94 #else 95 # define FPU_REG_WIDTH 64 96 #endif 97 98 union fpureg { 99 __u32 val32[FPU_REG_WIDTH / 32]; 100 __u64 val64[FPU_REG_WIDTH / 64]; 101 }; 102 103 #ifdef CONFIG_CPU_LITTLE_ENDIAN 104 # define FPR_IDX(width, idx) (idx) 105 #else 106 # define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1)) 107 #endif 108 109 #define BUILD_FPR_ACCESS(width) \ 110 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \ 111 { \ 112 return fpr->val##width[FPR_IDX(width, idx)]; \ 113 } \ 114 \ 115 static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \ 116 u##width val) \ 117 { \ 118 fpr->val##width[FPR_IDX(width, idx)] = val; \ 119 } 120 121 BUILD_FPR_ACCESS(32) 122 BUILD_FPR_ACCESS(64) 123 124 /* 125 * It would be nice to add some more fields for emulator statistics, 126 * the additional information is private to the FPU emulator for now. 127 * See arch/mips/include/asm/fpu_emulator.h. 128 */ 129 130 struct mips_fpu_struct { 131 union fpureg fpr[NUM_FPU_REGS]; 132 unsigned int fcr31; 133 unsigned int msacsr; 134 }; 135 136 #define NUM_DSP_REGS 6 137 138 typedef __u32 dspreg_t; 139 140 struct mips_dsp_state { 141 dspreg_t dspr[NUM_DSP_REGS]; 142 unsigned int dspcontrol; 143 }; 144 145 #define INIT_CPUMASK { \ 146 {0,} \ 147 } 148 149 struct mips3264_watch_reg_state { 150 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a 151 64 bit kernel. We use unsigned long as it has the same 152 property. */ 153 unsigned long watchlo[NUM_WATCH_REGS]; 154 /* Only the mask and IRW bits from watchhi. */ 155 u16 watchhi[NUM_WATCH_REGS]; 156 }; 157 158 union mips_watch_reg_state { 159 struct mips3264_watch_reg_state mips3264; 160 }; 161 162 #if defined(CONFIG_CPU_CAVIUM_OCTEON) 163 164 struct octeon_cop2_state { 165 /* DMFC2 rt, 0x0201 */ 166 unsigned long cop2_crc_iv; 167 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */ 168 unsigned long cop2_crc_length; 169 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */ 170 unsigned long cop2_crc_poly; 171 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */ 172 unsigned long cop2_llm_dat[2]; 173 /* DMFC2 rt, 0x0084 */ 174 unsigned long cop2_3des_iv; 175 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */ 176 unsigned long cop2_3des_key[3]; 177 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */ 178 unsigned long cop2_3des_result; 179 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */ 180 unsigned long cop2_aes_inp0; 181 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */ 182 unsigned long cop2_aes_iv[2]; 183 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2 184 * rt, 0x0107 */ 185 unsigned long cop2_aes_key[4]; 186 /* DMFC2 rt, 0x0110 */ 187 unsigned long cop2_aes_keylen; 188 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */ 189 unsigned long cop2_aes_result[2]; 190 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2 191 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt, 192 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt, 193 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt, 194 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */ 195 unsigned long cop2_hsh_datw[15]; 196 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2 197 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt, 198 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */ 199 unsigned long cop2_hsh_ivw[8]; 200 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */ 201 unsigned long cop2_gfm_mult[2]; 202 /* DMFC2 rt, 0x025E - Pass2 */ 203 unsigned long cop2_gfm_poly; 204 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 205 unsigned long cop2_gfm_result[2]; 206 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */ 207 unsigned long cop2_sha3[2]; 208 }; 209 #define COP2_INIT \ 210 .cp2 = {0,}, 211 212 struct octeon_cvmseg_state { 213 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] 214 [cpu_dcache_line_size() / sizeof(unsigned long)]; 215 }; 216 217 #elif defined(CONFIG_CPU_XLP) 218 struct nlm_cop2_state { 219 u64 rx[4]; 220 u64 tx[4]; 221 u32 tx_msg_status; 222 u32 rx_msg_status; 223 }; 224 225 #define COP2_INIT \ 226 .cp2 = {{0}, {0}, 0, 0}, 227 #else 228 #define COP2_INIT 229 #endif 230 231 typedef struct { 232 unsigned long seg; 233 } mm_segment_t; 234 235 #ifdef CONFIG_CPU_HAS_MSA 236 # define ARCH_MIN_TASKALIGN 16 237 # define FPU_ALIGN __aligned(16) 238 #else 239 # define ARCH_MIN_TASKALIGN 8 240 # define FPU_ALIGN 241 #endif 242 243 struct mips_abi; 244 245 /* 246 * If you change thread_struct remember to change the #defines below too! 247 */ 248 struct thread_struct { 249 /* Saved main processor registers. */ 250 unsigned long reg16; 251 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; 252 unsigned long reg29, reg30, reg31; 253 254 /* Saved cp0 stuff. */ 255 unsigned long cp0_status; 256 257 /* Saved fpu/fpu emulator stuff. */ 258 struct mips_fpu_struct fpu FPU_ALIGN; 259 #ifdef CONFIG_MIPS_MT_FPAFF 260 /* Emulated instruction count */ 261 unsigned long emulated_fp; 262 /* Saved per-thread scheduler affinity mask */ 263 cpumask_t user_cpus_allowed; 264 #endif /* CONFIG_MIPS_MT_FPAFF */ 265 266 /* Saved state of the DSP ASE, if available. */ 267 struct mips_dsp_state dsp; 268 269 /* Saved watch register state, if available. */ 270 union mips_watch_reg_state watch; 271 272 /* Other stuff associated with the thread. */ 273 unsigned long cp0_badvaddr; /* Last user fault */ 274 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 275 unsigned long error_code; 276 unsigned long trap_nr; 277 #ifdef CONFIG_CPU_CAVIUM_OCTEON 278 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 279 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 280 #endif 281 #ifdef CONFIG_CPU_XLP 282 struct nlm_cop2_state cp2; 283 #endif 284 struct mips_abi *abi; 285 }; 286 287 #ifdef CONFIG_MIPS_MT_FPAFF 288 #define FPAFF_INIT \ 289 .emulated_fp = 0, \ 290 .user_cpus_allowed = INIT_CPUMASK, 291 #else 292 #define FPAFF_INIT 293 #endif /* CONFIG_MIPS_MT_FPAFF */ 294 295 #define INIT_THREAD { \ 296 /* \ 297 * Saved main processor registers \ 298 */ \ 299 .reg16 = 0, \ 300 .reg17 = 0, \ 301 .reg18 = 0, \ 302 .reg19 = 0, \ 303 .reg20 = 0, \ 304 .reg21 = 0, \ 305 .reg22 = 0, \ 306 .reg23 = 0, \ 307 .reg29 = 0, \ 308 .reg30 = 0, \ 309 .reg31 = 0, \ 310 /* \ 311 * Saved cp0 stuff \ 312 */ \ 313 .cp0_status = 0, \ 314 /* \ 315 * Saved FPU/FPU emulator stuff \ 316 */ \ 317 .fpu = { \ 318 .fpr = {{{0,},},}, \ 319 .fcr31 = 0, \ 320 .msacsr = 0, \ 321 }, \ 322 /* \ 323 * FPU affinity state (null if not FPAFF) \ 324 */ \ 325 FPAFF_INIT \ 326 /* \ 327 * Saved DSP stuff \ 328 */ \ 329 .dsp = { \ 330 .dspr = {0, }, \ 331 .dspcontrol = 0, \ 332 }, \ 333 /* \ 334 * saved watch register stuff \ 335 */ \ 336 .watch = {{{0,},},}, \ 337 /* \ 338 * Other stuff associated with the process \ 339 */ \ 340 .cp0_badvaddr = 0, \ 341 .cp0_baduaddr = 0, \ 342 .error_code = 0, \ 343 .trap_nr = 0, \ 344 /* \ 345 * Platform specific cop2 registers(null if no COP2) \ 346 */ \ 347 COP2_INIT \ 348 } 349 350 struct task_struct; 351 352 /* Free all resources held by a thread. */ 353 #define release_thread(thread) do { } while(0) 354 355 extern unsigned long thread_saved_pc(struct task_struct *tsk); 356 357 /* 358 * Do necessary setup to start up a newly executed thread. 359 */ 360 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp); 361 362 static inline void flush_thread(void) 363 { 364 } 365 366 unsigned long get_wchan(struct task_struct *p); 367 368 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \ 369 THREAD_SIZE - 32 - sizeof(struct pt_regs)) 370 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk)) 371 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc) 372 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) 373 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status) 374 375 #define cpu_relax() barrier() 376 #define cpu_relax_lowlatency() cpu_relax() 377 378 /* 379 * Return_address is a replacement for __builtin_return_address(count) 380 * which on certain architectures cannot reasonably be implemented in GCC 381 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386). 382 * Note that __builtin_return_address(x>=1) is forbidden because GCC 383 * aborts compilation on some CPUs. It's simply not possible to unwind 384 * some CPU's stackframes. 385 * 386 * __builtin_return_address works only for non-leaf functions. We avoid the 387 * overhead of a function call by forcing the compiler to save the return 388 * address register on the stack. 389 */ 390 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) 391 392 #ifdef CONFIG_CPU_HAS_PREFETCH 393 394 #define ARCH_HAS_PREFETCH 395 #define prefetch(x) __builtin_prefetch((x), 0, 1) 396 397 #define ARCH_HAS_PREFETCHW 398 #define prefetchw(x) __builtin_prefetch((x), 1, 1) 399 400 #endif 401 402 /* 403 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options 404 * to the prctl syscall. 405 */ 406 extern int mips_get_process_fp_mode(struct task_struct *task); 407 extern int mips_set_process_fp_mode(struct task_struct *task, 408 unsigned int value); 409 410 #define GET_FP_MODE(task) mips_get_process_fp_mode(task) 411 #define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value) 412 413 #endif /* _ASM_PROCESSOR_H */ 414