1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 Waldorf GMBH 7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle 8 * Copyright (C) 1996 Paul M. Antoine 9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_PROCESSOR_H 12 #define _ASM_PROCESSOR_H 13 14 #include <linux/atomic.h> 15 #include <linux/cpumask.h> 16 #include <linux/sizes.h> 17 #include <linux/threads.h> 18 19 #include <asm/cachectl.h> 20 #include <asm/cpu.h> 21 #include <asm/cpu-info.h> 22 #include <asm/dsemul.h> 23 #include <asm/mipsregs.h> 24 #include <asm/prefetch.h> 25 #include <asm/vdso/processor.h> 26 27 /* 28 * System setup and hardware flags.. 29 */ 30 31 extern unsigned int vced_count, vcei_count; 32 33 #ifdef CONFIG_32BIT 34 #ifdef CONFIG_KVM_GUEST 35 /* User space process size is limited to 1GB in KVM Guest Mode */ 36 #define TASK_SIZE 0x3fff8000UL 37 #else 38 /* 39 * User space process size: 2GB. This is hardcoded into a few places, 40 * so don't change it unless you know what you are doing. 41 */ 42 #define TASK_SIZE 0x80000000UL 43 #endif 44 45 #define STACK_TOP_MAX TASK_SIZE 46 47 #define TASK_IS_32BIT_ADDR 1 48 49 #endif 50 51 #ifdef CONFIG_64BIT 52 /* 53 * User space process size: 1TB. This is hardcoded into a few places, 54 * so don't change it unless you know what you are doing. TASK_SIZE 55 * is limited to 1TB by the R4000 architecture; R10000 and better can 56 * support 16TB; the architectural reserve for future expansion is 57 * 8192EB ... 58 */ 59 #define TASK_SIZE32 0x7fff8000UL 60 #ifdef CONFIG_MIPS_VA_BITS_48 61 #define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits)) 62 #else 63 #define TASK_SIZE64 0x10000000000UL 64 #endif 65 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 66 #define STACK_TOP_MAX TASK_SIZE64 67 68 #define TASK_SIZE_OF(tsk) \ 69 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 70 71 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR) 72 73 #endif 74 75 #define VDSO_RANDOMIZE_SIZE (TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M) 76 77 extern unsigned long mips_stack_top(void); 78 #define STACK_TOP mips_stack_top() 79 80 /* 81 * This decides where the kernel will search for a free chunk of vm 82 * space during mmap's. 83 */ 84 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) 85 86 87 #define NUM_FPU_REGS 32 88 89 #ifdef CONFIG_CPU_HAS_MSA 90 # define FPU_REG_WIDTH 128 91 #else 92 # define FPU_REG_WIDTH 64 93 #endif 94 95 union fpureg { 96 __u32 val32[FPU_REG_WIDTH / 32]; 97 __u64 val64[FPU_REG_WIDTH / 64]; 98 }; 99 100 #ifdef CONFIG_CPU_LITTLE_ENDIAN 101 # define FPR_IDX(width, idx) (idx) 102 #else 103 # define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1)) 104 #endif 105 106 #define BUILD_FPR_ACCESS(width) \ 107 static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \ 108 { \ 109 return fpr->val##width[FPR_IDX(width, idx)]; \ 110 } \ 111 \ 112 static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \ 113 u##width val) \ 114 { \ 115 fpr->val##width[FPR_IDX(width, idx)] = val; \ 116 } 117 118 BUILD_FPR_ACCESS(32) 119 BUILD_FPR_ACCESS(64) 120 121 /* 122 * It would be nice to add some more fields for emulator statistics, 123 * the additional information is private to the FPU emulator for now. 124 * See arch/mips/include/asm/fpu_emulator.h. 125 */ 126 127 struct mips_fpu_struct { 128 union fpureg fpr[NUM_FPU_REGS]; 129 unsigned int fcr31; 130 unsigned int msacsr; 131 }; 132 133 #define NUM_DSP_REGS 6 134 135 typedef unsigned long dspreg_t; 136 137 struct mips_dsp_state { 138 dspreg_t dspr[NUM_DSP_REGS]; 139 unsigned int dspcontrol; 140 }; 141 142 #define INIT_CPUMASK { \ 143 {0,} \ 144 } 145 146 struct mips3264_watch_reg_state { 147 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a 148 64 bit kernel. We use unsigned long as it has the same 149 property. */ 150 unsigned long watchlo[NUM_WATCH_REGS]; 151 /* Only the mask and IRW bits from watchhi. */ 152 u16 watchhi[NUM_WATCH_REGS]; 153 }; 154 155 union mips_watch_reg_state { 156 struct mips3264_watch_reg_state mips3264; 157 }; 158 159 #if defined(CONFIG_CPU_CAVIUM_OCTEON) 160 161 struct octeon_cop2_state { 162 /* DMFC2 rt, 0x0201 */ 163 unsigned long cop2_crc_iv; 164 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */ 165 unsigned long cop2_crc_length; 166 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */ 167 unsigned long cop2_crc_poly; 168 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */ 169 unsigned long cop2_llm_dat[2]; 170 /* DMFC2 rt, 0x0084 */ 171 unsigned long cop2_3des_iv; 172 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */ 173 unsigned long cop2_3des_key[3]; 174 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */ 175 unsigned long cop2_3des_result; 176 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */ 177 unsigned long cop2_aes_inp0; 178 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */ 179 unsigned long cop2_aes_iv[2]; 180 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2 181 * rt, 0x0107 */ 182 unsigned long cop2_aes_key[4]; 183 /* DMFC2 rt, 0x0110 */ 184 unsigned long cop2_aes_keylen; 185 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */ 186 unsigned long cop2_aes_result[2]; 187 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2 188 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt, 189 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt, 190 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt, 191 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */ 192 unsigned long cop2_hsh_datw[15]; 193 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2 194 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt, 195 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */ 196 unsigned long cop2_hsh_ivw[8]; 197 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */ 198 unsigned long cop2_gfm_mult[2]; 199 /* DMFC2 rt, 0x025E - Pass2 */ 200 unsigned long cop2_gfm_poly; 201 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 202 unsigned long cop2_gfm_result[2]; 203 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */ 204 unsigned long cop2_sha3[2]; 205 }; 206 #define COP2_INIT \ 207 .cp2 = {0,}, 208 209 struct octeon_cvmseg_state { 210 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] 211 [cpu_dcache_line_size() / sizeof(unsigned long)]; 212 }; 213 214 #elif defined(CONFIG_CPU_XLP) 215 struct nlm_cop2_state { 216 u64 rx[4]; 217 u64 tx[4]; 218 u32 tx_msg_status; 219 u32 rx_msg_status; 220 }; 221 222 #define COP2_INIT \ 223 .cp2 = {{0}, {0}, 0, 0}, 224 #else 225 #define COP2_INIT 226 #endif 227 228 typedef struct { 229 unsigned long seg; 230 } mm_segment_t; 231 232 #ifdef CONFIG_CPU_HAS_MSA 233 # define ARCH_MIN_TASKALIGN 16 234 # define FPU_ALIGN __aligned(16) 235 #else 236 # define ARCH_MIN_TASKALIGN 8 237 # define FPU_ALIGN 238 #endif 239 240 struct mips_abi; 241 242 /* 243 * If you change thread_struct remember to change the #defines below too! 244 */ 245 struct thread_struct { 246 /* Saved main processor registers. */ 247 unsigned long reg16; 248 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; 249 unsigned long reg29, reg30, reg31; 250 251 /* Saved cp0 stuff. */ 252 unsigned long cp0_status; 253 254 #ifdef CONFIG_MIPS_FP_SUPPORT 255 /* Saved fpu/fpu emulator stuff. */ 256 struct mips_fpu_struct fpu FPU_ALIGN; 257 /* Assigned branch delay slot 'emulation' frame */ 258 atomic_t bd_emu_frame; 259 /* PC of the branch from a branch delay slot 'emulation' */ 260 unsigned long bd_emu_branch_pc; 261 /* PC to continue from following a branch delay slot 'emulation' */ 262 unsigned long bd_emu_cont_pc; 263 #endif 264 #ifdef CONFIG_MIPS_MT_FPAFF 265 /* Emulated instruction count */ 266 unsigned long emulated_fp; 267 /* Saved per-thread scheduler affinity mask */ 268 cpumask_t user_cpus_allowed; 269 #endif /* CONFIG_MIPS_MT_FPAFF */ 270 271 /* Saved state of the DSP ASE, if available. */ 272 struct mips_dsp_state dsp; 273 274 /* Saved watch register state, if available. */ 275 union mips_watch_reg_state watch; 276 277 /* Other stuff associated with the thread. */ 278 unsigned long cp0_badvaddr; /* Last user fault */ 279 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 280 unsigned long error_code; 281 unsigned long trap_nr; 282 #ifdef CONFIG_CPU_CAVIUM_OCTEON 283 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 284 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 285 #endif 286 #ifdef CONFIG_CPU_XLP 287 struct nlm_cop2_state cp2; 288 #endif 289 struct mips_abi *abi; 290 }; 291 292 #ifdef CONFIG_MIPS_MT_FPAFF 293 #define FPAFF_INIT \ 294 .emulated_fp = 0, \ 295 .user_cpus_allowed = INIT_CPUMASK, 296 #else 297 #define FPAFF_INIT 298 #endif /* CONFIG_MIPS_MT_FPAFF */ 299 300 #ifdef CONFIG_MIPS_FP_SUPPORT 301 # define FPU_INIT \ 302 .fpu = { \ 303 .fpr = {{{0,},},}, \ 304 .fcr31 = 0, \ 305 .msacsr = 0, \ 306 }, \ 307 /* Delay slot emulation */ \ 308 .bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \ 309 .bd_emu_branch_pc = 0, \ 310 .bd_emu_cont_pc = 0, 311 #else 312 # define FPU_INIT 313 #endif 314 315 #define INIT_THREAD { \ 316 /* \ 317 * Saved main processor registers \ 318 */ \ 319 .reg16 = 0, \ 320 .reg17 = 0, \ 321 .reg18 = 0, \ 322 .reg19 = 0, \ 323 .reg20 = 0, \ 324 .reg21 = 0, \ 325 .reg22 = 0, \ 326 .reg23 = 0, \ 327 .reg29 = 0, \ 328 .reg30 = 0, \ 329 .reg31 = 0, \ 330 /* \ 331 * Saved cp0 stuff \ 332 */ \ 333 .cp0_status = 0, \ 334 /* \ 335 * Saved FPU/FPU emulator stuff \ 336 */ \ 337 FPU_INIT \ 338 /* \ 339 * FPU affinity state (null if not FPAFF) \ 340 */ \ 341 FPAFF_INIT \ 342 /* \ 343 * Saved DSP stuff \ 344 */ \ 345 .dsp = { \ 346 .dspr = {0, }, \ 347 .dspcontrol = 0, \ 348 }, \ 349 /* \ 350 * saved watch register stuff \ 351 */ \ 352 .watch = {{{0,},},}, \ 353 /* \ 354 * Other stuff associated with the process \ 355 */ \ 356 .cp0_badvaddr = 0, \ 357 .cp0_baduaddr = 0, \ 358 .error_code = 0, \ 359 .trap_nr = 0, \ 360 /* \ 361 * Platform specific cop2 registers(null if no COP2) \ 362 */ \ 363 COP2_INIT \ 364 } 365 366 struct task_struct; 367 368 /* Free all resources held by a thread. */ 369 #define release_thread(thread) do { } while(0) 370 371 /* 372 * Do necessary setup to start up a newly executed thread. 373 */ 374 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp); 375 376 static inline void flush_thread(void) 377 { 378 } 379 380 unsigned long get_wchan(struct task_struct *p); 381 382 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \ 383 THREAD_SIZE - 32 - sizeof(struct pt_regs)) 384 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk)) 385 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc) 386 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) 387 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status) 388 389 /* 390 * Return_address is a replacement for __builtin_return_address(count) 391 * which on certain architectures cannot reasonably be implemented in GCC 392 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386). 393 * Note that __builtin_return_address(x>=1) is forbidden because GCC 394 * aborts compilation on some CPUs. It's simply not possible to unwind 395 * some CPU's stackframes. 396 * 397 * __builtin_return_address works only for non-leaf functions. We avoid the 398 * overhead of a function call by forcing the compiler to save the return 399 * address register on the stack. 400 */ 401 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) 402 403 #ifdef CONFIG_CPU_HAS_PREFETCH 404 405 #define ARCH_HAS_PREFETCH 406 #define prefetch(x) __builtin_prefetch((x), 0, 1) 407 408 #define ARCH_HAS_PREFETCHW 409 #define prefetchw(x) __builtin_prefetch((x), 1, 1) 410 411 #endif 412 413 /* 414 * Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options 415 * to the prctl syscall. 416 */ 417 extern int mips_get_process_fp_mode(struct task_struct *task); 418 extern int mips_set_process_fp_mode(struct task_struct *task, 419 unsigned int value); 420 421 #define GET_FP_MODE(task) mips_get_process_fp_mode(task) 422 #define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value) 423 424 #endif /* _ASM_PROCESSOR_H */ 425