1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 Waldorf GMBH 7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle 8 * Copyright (C) 1996 Paul M. Antoine 9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_PROCESSOR_H 12 #define _ASM_PROCESSOR_H 13 14 #include <linux/cpumask.h> 15 #include <linux/threads.h> 16 17 #include <asm/cachectl.h> 18 #include <asm/cpu.h> 19 #include <asm/cpu-info.h> 20 #include <asm/mipsregs.h> 21 #include <asm/prefetch.h> 22 23 /* 24 * Return current * instruction pointer ("program counter"). 25 */ 26 #define current_text_addr() ({ __label__ _l; _l: &&_l;}) 27 28 /* 29 * System setup and hardware flags.. 30 */ 31 32 extern unsigned int vced_count, vcei_count; 33 34 /* 35 * MIPS does have an arch_pick_mmap_layout() 36 */ 37 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 38 39 /* 40 * A special page (the vdso) is mapped into all processes at the very 41 * top of the virtual memory space. 42 */ 43 #define SPECIAL_PAGES_SIZE PAGE_SIZE 44 45 #ifdef CONFIG_32BIT 46 #ifdef CONFIG_KVM_GUEST 47 /* User space process size is limited to 1GB in KVM Guest Mode */ 48 #define TASK_SIZE 0x3fff8000UL 49 #else 50 /* 51 * User space process size: 2GB. This is hardcoded into a few places, 52 * so don't change it unless you know what you are doing. 53 */ 54 #define TASK_SIZE 0x7fff8000UL 55 #endif 56 57 #ifdef __KERNEL__ 58 #define STACK_TOP_MAX TASK_SIZE 59 #endif 60 61 #define TASK_IS_32BIT_ADDR 1 62 63 #endif 64 65 #ifdef CONFIG_64BIT 66 /* 67 * User space process size: 1TB. This is hardcoded into a few places, 68 * so don't change it unless you know what you are doing. TASK_SIZE 69 * is limited to 1TB by the R4000 architecture; R10000 and better can 70 * support 16TB; the architectural reserve for future expansion is 71 * 8192EB ... 72 */ 73 #define TASK_SIZE32 0x7fff8000UL 74 #define TASK_SIZE64 0x10000000000UL 75 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 76 77 #ifdef __KERNEL__ 78 #define STACK_TOP_MAX TASK_SIZE64 79 #endif 80 81 82 #define TASK_SIZE_OF(tsk) \ 83 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64) 84 85 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR) 86 87 #endif 88 89 #define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE) 90 91 /* 92 * This decides where the kernel will search for a free chunk of vm 93 * space during mmap's. 94 */ 95 #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3) 96 97 98 #define NUM_FPU_REGS 32 99 100 typedef __u64 fpureg_t; 101 102 /* 103 * It would be nice to add some more fields for emulator statistics, but there 104 * are a number of fixed offsets in offset.h and elsewhere that would have to 105 * be recalculated by hand. So the additional information will be private to 106 * the FPU emulator for now. See asm-mips/fpu_emulator.h. 107 */ 108 109 struct mips_fpu_struct { 110 fpureg_t fpr[NUM_FPU_REGS]; 111 unsigned int fcr31; 112 }; 113 114 #define NUM_DSP_REGS 6 115 116 typedef __u32 dspreg_t; 117 118 struct mips_dsp_state { 119 dspreg_t dspr[NUM_DSP_REGS]; 120 unsigned int dspcontrol; 121 }; 122 123 #define INIT_CPUMASK { \ 124 {0,} \ 125 } 126 127 struct mips3264_watch_reg_state { 128 /* The width of watchlo is 32 in a 32 bit kernel and 64 in a 129 64 bit kernel. We use unsigned long as it has the same 130 property. */ 131 unsigned long watchlo[NUM_WATCH_REGS]; 132 /* Only the mask and IRW bits from watchhi. */ 133 u16 watchhi[NUM_WATCH_REGS]; 134 }; 135 136 union mips_watch_reg_state { 137 struct mips3264_watch_reg_state mips3264; 138 }; 139 140 #ifdef CONFIG_CPU_CAVIUM_OCTEON 141 142 struct octeon_cop2_state { 143 /* DMFC2 rt, 0x0201 */ 144 unsigned long cop2_crc_iv; 145 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */ 146 unsigned long cop2_crc_length; 147 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */ 148 unsigned long cop2_crc_poly; 149 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */ 150 unsigned long cop2_llm_dat[2]; 151 /* DMFC2 rt, 0x0084 */ 152 unsigned long cop2_3des_iv; 153 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */ 154 unsigned long cop2_3des_key[3]; 155 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */ 156 unsigned long cop2_3des_result; 157 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */ 158 unsigned long cop2_aes_inp0; 159 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */ 160 unsigned long cop2_aes_iv[2]; 161 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2 162 * rt, 0x0107 */ 163 unsigned long cop2_aes_key[4]; 164 /* DMFC2 rt, 0x0110 */ 165 unsigned long cop2_aes_keylen; 166 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */ 167 unsigned long cop2_aes_result[2]; 168 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2 169 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt, 170 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt, 171 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt, 172 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */ 173 unsigned long cop2_hsh_datw[15]; 174 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2 175 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt, 176 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */ 177 unsigned long cop2_hsh_ivw[8]; 178 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */ 179 unsigned long cop2_gfm_mult[2]; 180 /* DMFC2 rt, 0x025E - Pass2 */ 181 unsigned long cop2_gfm_poly; 182 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */ 183 unsigned long cop2_gfm_result[2]; 184 }; 185 #define INIT_OCTEON_COP2 {0,} 186 187 struct octeon_cvmseg_state { 188 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] 189 [cpu_dcache_line_size() / sizeof(unsigned long)]; 190 }; 191 192 #endif 193 194 typedef struct { 195 unsigned long seg; 196 } mm_segment_t; 197 198 #define ARCH_MIN_TASKALIGN 8 199 200 struct mips_abi; 201 202 /* 203 * If you change thread_struct remember to change the #defines below too! 204 */ 205 struct thread_struct { 206 /* Saved main processor registers. */ 207 unsigned long reg16; 208 unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23; 209 unsigned long reg29, reg30, reg31; 210 211 /* Saved cp0 stuff. */ 212 unsigned long cp0_status; 213 214 /* Saved fpu/fpu emulator stuff. */ 215 struct mips_fpu_struct fpu; 216 #ifdef CONFIG_MIPS_MT_FPAFF 217 /* Emulated instruction count */ 218 unsigned long emulated_fp; 219 /* Saved per-thread scheduler affinity mask */ 220 cpumask_t user_cpus_allowed; 221 #endif /* CONFIG_MIPS_MT_FPAFF */ 222 223 /* Saved state of the DSP ASE, if available. */ 224 struct mips_dsp_state dsp; 225 226 /* Saved watch register state, if available. */ 227 union mips_watch_reg_state watch; 228 229 /* Other stuff associated with the thread. */ 230 unsigned long cp0_badvaddr; /* Last user fault */ 231 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 232 unsigned long error_code; 233 #ifdef CONFIG_CPU_CAVIUM_OCTEON 234 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); 235 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); 236 #endif 237 struct mips_abi *abi; 238 }; 239 240 #ifdef CONFIG_MIPS_MT_FPAFF 241 #define FPAFF_INIT \ 242 .emulated_fp = 0, \ 243 .user_cpus_allowed = INIT_CPUMASK, 244 #else 245 #define FPAFF_INIT 246 #endif /* CONFIG_MIPS_MT_FPAFF */ 247 248 #ifdef CONFIG_CPU_CAVIUM_OCTEON 249 #define OCTEON_INIT \ 250 .cp2 = INIT_OCTEON_COP2, 251 #else 252 #define OCTEON_INIT 253 #endif /* CONFIG_CPU_CAVIUM_OCTEON */ 254 255 #define INIT_THREAD { \ 256 /* \ 257 * Saved main processor registers \ 258 */ \ 259 .reg16 = 0, \ 260 .reg17 = 0, \ 261 .reg18 = 0, \ 262 .reg19 = 0, \ 263 .reg20 = 0, \ 264 .reg21 = 0, \ 265 .reg22 = 0, \ 266 .reg23 = 0, \ 267 .reg29 = 0, \ 268 .reg30 = 0, \ 269 .reg31 = 0, \ 270 /* \ 271 * Saved cp0 stuff \ 272 */ \ 273 .cp0_status = 0, \ 274 /* \ 275 * Saved FPU/FPU emulator stuff \ 276 */ \ 277 .fpu = { \ 278 .fpr = {0,}, \ 279 .fcr31 = 0, \ 280 }, \ 281 /* \ 282 * FPU affinity state (null if not FPAFF) \ 283 */ \ 284 FPAFF_INIT \ 285 /* \ 286 * Saved DSP stuff \ 287 */ \ 288 .dsp = { \ 289 .dspr = {0, }, \ 290 .dspcontrol = 0, \ 291 }, \ 292 /* \ 293 * saved watch register stuff \ 294 */ \ 295 .watch = {{{0,},},}, \ 296 /* \ 297 * Other stuff associated with the process \ 298 */ \ 299 .cp0_badvaddr = 0, \ 300 .cp0_baduaddr = 0, \ 301 .error_code = 0, \ 302 /* \ 303 * Cavium Octeon specifics (null if not Octeon) \ 304 */ \ 305 OCTEON_INIT \ 306 } 307 308 struct task_struct; 309 310 /* Free all resources held by a thread. */ 311 #define release_thread(thread) do { } while(0) 312 313 extern unsigned long thread_saved_pc(struct task_struct *tsk); 314 315 /* 316 * Do necessary setup to start up a newly executed thread. 317 */ 318 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp); 319 320 unsigned long get_wchan(struct task_struct *p); 321 322 #define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \ 323 THREAD_SIZE - 32 - sizeof(struct pt_regs)) 324 #define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk)) 325 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc) 326 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29]) 327 #define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status) 328 329 #define cpu_relax() barrier() 330 331 /* 332 * Return_address is a replacement for __builtin_return_address(count) 333 * which on certain architectures cannot reasonably be implemented in GCC 334 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386). 335 * Note that __builtin_return_address(x>=1) is forbidden because GCC 336 * aborts compilation on some CPUs. It's simply not possible to unwind 337 * some CPU's stackframes. 338 * 339 * __builtin_return_address works only for non-leaf functions. We avoid the 340 * overhead of a function call by forcing the compiler to save the return 341 * address register on the stack. 342 */ 343 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) 344 345 #ifdef CONFIG_CPU_HAS_PREFETCH 346 347 #define ARCH_HAS_PREFETCH 348 #define prefetch(x) __builtin_prefetch((x), 0, 1) 349 350 #define ARCH_HAS_PREFETCHW 351 #define prefetchw(x) __builtin_prefetch((x), 1, 1) 352 353 /* 354 * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP 355 * systems. 356 */ 357 #define __ARCH_WANT_UNLOCKED_CTXSW 358 359 #endif 360 361 #endif /* _ASM_PROCESSOR_H */ 362