1 /* 2 * Copyright (C) 2014 Imagination Technologies 3 * Author: Paul Burton <paul.burton@imgtec.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #ifndef __MIPS_ASM_PM_CPS_H__ 12 #define __MIPS_ASM_PM_CPS_H__ 13 14 /* 15 * The CM & CPC can only handle coherence & power control on a per-core basis, 16 * thus in an MT system the VPEs within each core are coupled and can only 17 * enter or exit states requiring CM or CPC assistance in unison. 18 */ 19 #ifdef CONFIG_MIPS_MT 20 # define coupled_coherence cpu_has_mipsmt 21 #else 22 # define coupled_coherence 0 23 #endif 24 25 /* Enumeration of possible PM states */ 26 enum cps_pm_state { 27 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */ 28 CPS_PM_CLOCK_GATED, /* Core clock gated */ 29 CPS_PM_POWER_GATED, /* Core power gated */ 30 CPS_PM_STATE_COUNT, 31 }; 32 33 /** 34 * cps_pm_support_state - determine whether the system supports a PM state 35 * @state: the state to test for support 36 * 37 * Returns true if the system supports the given state, otherwise false. 38 */ 39 extern bool cps_pm_support_state(enum cps_pm_state state); 40 41 /** 42 * cps_pm_enter_state - enter a PM state 43 * @state: the state to enter 44 * 45 * Enter the given PM state. If coupled_coherence is non-zero then it is 46 * expected that this function be called at approximately the same time on 47 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno. 48 */ 49 extern int cps_pm_enter_state(enum cps_pm_state state); 50 51 #endif /* __MIPS_ASM_PM_CPS_H__ */ 52