1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 */ 6 #ifndef _ASM_PCI_H 7 #define _ASM_PCI_H 8 9 #include <linux/mm.h> 10 11 #ifdef __KERNEL__ 12 13 /* 14 * This file essentially defines the interface between board 15 * specific PCI code and MIPS common PCI code. Should potentially put 16 * into include/asm/pci.h file. 17 */ 18 19 #include <linux/ioport.h> 20 #include <linux/of.h> 21 22 /* 23 * Each pci channel is a top-level PCI bus seem by CPU. A machine with 24 * multiple PCI channels may have multiple PCI host controllers or a 25 * single controller supporting multiple channels. 26 */ 27 struct pci_controller { 28 struct pci_controller *next; 29 struct pci_bus *bus; 30 struct device_node *of_node; 31 32 struct pci_ops *pci_ops; 33 struct resource *mem_resource; 34 unsigned long mem_offset; 35 struct resource *io_resource; 36 unsigned long io_offset; 37 unsigned long io_map_base; 38 struct resource *busn_resource; 39 unsigned long busn_offset; 40 41 unsigned int index; 42 /* For compatibility with current (as of July 2003) pciutils 43 and XFree86. Eventually will be removed. */ 44 unsigned int need_domain_info; 45 46 int iommu; 47 48 /* Optional access methods for reading/writing the bus number 49 of the PCI controller */ 50 int (*get_busno)(void); 51 void (*set_busno)(int busno); 52 }; 53 54 /* 55 * Used by boards to register their PCI busses before the actual scanning. 56 */ 57 extern void register_pci_controller(struct pci_controller *hose); 58 59 /* 60 * board supplied pci irq fixup routine 61 */ 62 extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); 63 64 65 /* Can be used to override the logic in pci_scan_bus for skipping 66 already-configured bus numbers - to be used for buggy BIOSes 67 or architectures with incomplete PCI setup by the loader */ 68 69 extern unsigned int pcibios_assign_all_busses(void); 70 71 extern unsigned long PCIBIOS_MIN_IO; 72 extern unsigned long PCIBIOS_MIN_MEM; 73 74 #define PCIBIOS_MIN_CARDBUS_IO 0x4000 75 76 extern void pcibios_set_master(struct pci_dev *dev); 77 78 #define HAVE_PCI_MMAP 79 80 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 81 enum pci_mmap_state mmap_state, int write_combine); 82 83 #define HAVE_ARCH_PCI_RESOURCE_TO_USER 84 85 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, 86 const struct resource *rsrc, resource_size_t *start, 87 resource_size_t *end) 88 { 89 phys_addr_t size = resource_size(rsrc); 90 91 *start = fixup_bigphys_addr(rsrc->start, size); 92 *end = rsrc->start + size; 93 } 94 95 /* 96 * Dynamic DMA mapping stuff. 97 * MIPS has everything mapped statically. 98 */ 99 100 #include <linux/types.h> 101 #include <linux/slab.h> 102 #include <linux/scatterlist.h> 103 #include <linux/string.h> 104 #include <asm/io.h> 105 #include <asm-generic/pci-bridge.h> 106 107 struct pci_dev; 108 109 /* 110 * The PCI address space does equal the physical memory address space. The 111 * networking and block device layers use this boolean for bounce buffer 112 * decisions. This is set if any hose does not have an IOMMU. 113 */ 114 extern unsigned int PCI_DMA_BUS_IS_PHYS; 115 116 #ifdef CONFIG_PCI_DOMAINS 117 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index 118 119 static inline int pci_proc_domain(struct pci_bus *bus) 120 { 121 struct pci_controller *hose = bus->sysdata; 122 return hose->need_domain_info; 123 } 124 #endif /* CONFIG_PCI_DOMAINS */ 125 126 #endif /* __KERNEL__ */ 127 128 /* implement the pci_ DMA API in terms of the generic device dma_ one */ 129 #include <asm-generic/pci-dma-compat.h> 130 131 /* Do platform specific device initialization at pci_enable_device() time */ 132 extern int pcibios_plat_dev_init(struct pci_dev *dev); 133 134 /* Chances are this interrupt is wired PC-style ... */ 135 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 136 { 137 return channel ? 15 : 14; 138 } 139 140 extern char * (*pcibios_plat_setup)(char *str); 141 142 #ifdef CONFIG_OF 143 /* this function parses memory ranges from a device node */ 144 extern void pci_load_of_ranges(struct pci_controller *hose, 145 struct device_node *node); 146 #else 147 static inline void pci_load_of_ranges(struct pci_controller *hose, 148 struct device_node *node) {} 149 #endif 150 151 #endif /* _ASM_PCI_H */ 152