xref: /openbmc/linux/arch/mips/include/asm/pci.h (revision 9ac8d3fb)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  */
6 #ifndef _ASM_PCI_H
7 #define _ASM_PCI_H
8 
9 #include <linux/mm.h>
10 
11 #ifdef __KERNEL__
12 
13 /*
14  * This file essentially defines the interface between board
15  * specific PCI code and MIPS common PCI code.  Should potentially put
16  * into include/asm/pci.h file.
17  */
18 
19 #include <linux/ioport.h>
20 
21 /*
22  * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
23  * multiple PCI channels may have multiple PCI host controllers or a
24  * single controller supporting multiple channels.
25  */
26 struct pci_controller {
27 	struct pci_controller *next;
28 	struct pci_bus *bus;
29 
30 	struct pci_ops *pci_ops;
31 	struct resource *mem_resource;
32 	unsigned long mem_offset;
33 	struct resource *io_resource;
34 	unsigned long io_offset;
35 	unsigned long io_map_base;
36 
37 	unsigned int index;
38 	/* For compatibility with current (as of July 2003) pciutils
39 	   and XFree86. Eventually will be removed. */
40 	unsigned int need_domain_info;
41 
42 	int iommu;
43 
44 	/* Optional access methods for reading/writing the bus number
45 	   of the PCI controller */
46 	int (*get_busno)(void);
47 	void (*set_busno)(int busno);
48 };
49 
50 /*
51  * Used by boards to register their PCI busses before the actual scanning.
52  */
53 extern struct pci_controller * alloc_pci_controller(void);
54 extern void register_pci_controller(struct pci_controller *hose);
55 
56 /*
57  * board supplied pci irq fixup routine
58  */
59 extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
60 
61 
62 /* Can be used to override the logic in pci_scan_bus for skipping
63    already-configured bus numbers - to be used for buggy BIOSes
64    or architectures with incomplete PCI setup by the loader */
65 
66 extern unsigned int pcibios_assign_all_busses(void);
67 
68 #define pcibios_scan_all_fns(a, b)	0
69 
70 extern unsigned long PCIBIOS_MIN_IO;
71 extern unsigned long PCIBIOS_MIN_MEM;
72 
73 #define PCIBIOS_MIN_CARDBUS_IO	0x4000
74 
75 extern void pcibios_set_master(struct pci_dev *dev);
76 
77 static inline void pcibios_penalize_isa_irq(int irq, int active)
78 {
79 	/* We don't do dynamic PCI IRQ allocation */
80 }
81 
82 /*
83  * Dynamic DMA mapping stuff.
84  * MIPS has everything mapped statically.
85  */
86 
87 #include <linux/types.h>
88 #include <linux/slab.h>
89 #include <asm/scatterlist.h>
90 #include <linux/string.h>
91 #include <asm/io.h>
92 
93 struct pci_dev;
94 
95 /*
96  * The PCI address space does equal the physical memory address space.  The
97  * networking and block device layers use this boolean for bounce buffer
98  * decisions.  This is set if any hose does not have an IOMMU.
99  */
100 extern unsigned int PCI_DMA_BUS_IS_PHYS;
101 
102 #ifdef CONFIG_DMA_NEED_PCI_MAP_STATE
103 
104 /* pci_unmap_{single,page} is not a nop, thus... */
105 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	dma_addr_t ADDR_NAME;
106 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		__u32 LEN_NAME;
107 #define pci_unmap_addr(PTR, ADDR_NAME)		((PTR)->ADDR_NAME)
108 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	(((PTR)->ADDR_NAME) = (VAL))
109 #define pci_unmap_len(PTR, LEN_NAME)		((PTR)->LEN_NAME)
110 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)	(((PTR)->LEN_NAME) = (VAL))
111 
112 #else /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
113 
114 /* pci_unmap_{page,single} is a nop so... */
115 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
116 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
117 #define pci_unmap_addr(PTR, ADDR_NAME)		(0)
118 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	do { } while (0)
119 #define pci_unmap_len(PTR, LEN_NAME)		(0)
120 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)
121 
122 #endif /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
123 
124 #ifdef CONFIG_PCI
125 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
126 					enum pci_dma_burst_strategy *strat,
127 					unsigned long *strategy_parameter)
128 {
129 	*strat = PCI_DMA_BURST_INFINITY;
130 	*strategy_parameter = ~0UL;
131 }
132 #endif
133 
134 extern void pcibios_resource_to_bus(struct pci_dev *dev,
135 	struct pci_bus_region *region, struct resource *res);
136 
137 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
138 				    struct pci_bus_region *region);
139 
140 static inline struct resource *
141 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
142 {
143 	struct resource *root = NULL;
144 
145 	if (res->flags & IORESOURCE_IO)
146 		root = &ioport_resource;
147 	if (res->flags & IORESOURCE_MEM)
148 		root = &iomem_resource;
149 
150 	return root;
151 }
152 
153 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
154 
155 static inline int pci_proc_domain(struct pci_bus *bus)
156 {
157 	struct pci_controller *hose = bus->sysdata;
158 	return hose->need_domain_info;
159 }
160 
161 #endif /* __KERNEL__ */
162 
163 /* implement the pci_ DMA API in terms of the generic device dma_ one */
164 #include <asm-generic/pci-dma-compat.h>
165 
166 /* Do platform specific device initialization at pci_enable_device() time */
167 extern int pcibios_plat_dev_init(struct pci_dev *dev);
168 
169 /* Chances are this interrupt is wired PC-style ...  */
170 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
171 {
172 	return channel ? 15 : 14;
173 }
174 
175 extern int pci_probe_only;
176 
177 extern char * (*pcibios_plat_setup)(char *str);
178 
179 #endif /* _ASM_PCI_H */
180