xref: /openbmc/linux/arch/mips/include/asm/page.h (revision e5080a96)
1384740dcSRalf Baechle /*
2384740dcSRalf Baechle  * This file is subject to the terms and conditions of the GNU General Public
3384740dcSRalf Baechle  * License.  See the file "COPYING" in the main directory of this archive
4384740dcSRalf Baechle  * for more details.
5384740dcSRalf Baechle  *
6384740dcSRalf Baechle  * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle
7384740dcSRalf Baechle  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8384740dcSRalf Baechle  */
9384740dcSRalf Baechle #ifndef _ASM_PAGE_H
10384740dcSRalf Baechle #define _ASM_PAGE_H
11384740dcSRalf Baechle 
12384740dcSRalf Baechle #include <spaces.h>
1399502d94SNelson Elhage #include <linux/const.h>
1475b5b5e0SLeonid Yegoshin #include <linux/kernel.h>
1575b5b5e0SLeonid Yegoshin #include <asm/mipsregs.h>
16384740dcSRalf Baechle 
17384740dcSRalf Baechle /*
18384740dcSRalf Baechle  * PAGE_SHIFT determines the page size
19384740dcSRalf Baechle  */
20384740dcSRalf Baechle #ifdef CONFIG_PAGE_SIZE_4KB
21384740dcSRalf Baechle #define PAGE_SHIFT	12
22384740dcSRalf Baechle #endif
23384740dcSRalf Baechle #ifdef CONFIG_PAGE_SIZE_8KB
24384740dcSRalf Baechle #define PAGE_SHIFT	13
25384740dcSRalf Baechle #endif
26384740dcSRalf Baechle #ifdef CONFIG_PAGE_SIZE_16KB
27384740dcSRalf Baechle #define PAGE_SHIFT	14
28384740dcSRalf Baechle #endif
29c52399beSRalf Baechle #ifdef CONFIG_PAGE_SIZE_32KB
30c52399beSRalf Baechle #define PAGE_SHIFT	15
31c52399beSRalf Baechle #endif
32384740dcSRalf Baechle #ifdef CONFIG_PAGE_SIZE_64KB
33384740dcSRalf Baechle #define PAGE_SHIFT	16
34384740dcSRalf Baechle #endif
3599502d94SNelson Elhage #define PAGE_SIZE	(_AC(1,UL) << PAGE_SHIFT)
36800dc4f4SDan Williams #define PAGE_MASK	(~((1 << PAGE_SHIFT) - 1))
37384740dcSRalf Baechle 
3875b5b5e0SLeonid Yegoshin /*
3975b5b5e0SLeonid Yegoshin  * This is used for calculating the real page sizes
4091ff7ac0SGeert Uytterhoeven  * for FTLB or VTLB + FTLB configurations.
4175b5b5e0SLeonid Yegoshin  */
page_size_ftlb(unsigned int mmuextdef)4275b5b5e0SLeonid Yegoshin static inline unsigned int page_size_ftlb(unsigned int mmuextdef)
4375b5b5e0SLeonid Yegoshin {
4475b5b5e0SLeonid Yegoshin 	switch (mmuextdef) {
4575b5b5e0SLeonid Yegoshin 	case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
4675b5b5e0SLeonid Yegoshin 		if (PAGE_SIZE == (1 << 30))
4775b5b5e0SLeonid Yegoshin 			return 5;
4875b5b5e0SLeonid Yegoshin 		if (PAGE_SIZE == (1llu << 32))
4975b5b5e0SLeonid Yegoshin 			return 6;
5075b5b5e0SLeonid Yegoshin 		if (PAGE_SIZE > (256 << 10))
5175b5b5e0SLeonid Yegoshin 			return 7; /* reserved */
52c9b02990SLiangliang Huang 		fallthrough;
5375b5b5e0SLeonid Yegoshin 	case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
5475b5b5e0SLeonid Yegoshin 		return (PAGE_SHIFT - 10) / 2;
5575b5b5e0SLeonid Yegoshin 	default:
5675b5b5e0SLeonid Yegoshin 		panic("Invalid FTLB configuration with Conf4_mmuextdef=%d value\n",
5775b5b5e0SLeonid Yegoshin 		      mmuextdef >> 14);
5875b5b5e0SLeonid Yegoshin 	}
5975b5b5e0SLeonid Yegoshin }
6075b5b5e0SLeonid Yegoshin 
61aa1762f4SDavid Daney #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
62dd794392SDavid Daney #define HPAGE_SHIFT	(PAGE_SHIFT + PAGE_SHIFT - 3)
6399502d94SNelson Elhage #define HPAGE_SIZE	(_AC(1,UL) << HPAGE_SHIFT)
64dd794392SDavid Daney #define HPAGE_MASK	(~(HPAGE_SIZE - 1))
65dd794392SDavid Daney #define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
66aa1762f4SDavid Daney #else /* !CONFIG_MIPS_HUGE_TLB_SUPPORT */
67f467e4bfSHillf Danton #define HPAGE_SHIFT	({BUILD_BUG(); 0; })
68f467e4bfSHillf Danton #define HPAGE_SIZE	({BUILD_BUG(); 0; })
69f467e4bfSHillf Danton #define HPAGE_MASK	({BUILD_BUG(); 0; })
70f467e4bfSHillf Danton #define HUGETLB_PAGE_ORDER	({BUILD_BUG(); 0; })
71aa1762f4SDavid Daney #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
72dd794392SDavid Daney 
73384740dcSRalf Baechle #include <linux/pfn.h>
74384740dcSRalf Baechle 
75384740dcSRalf Baechle extern void build_clear_page(void);
76384740dcSRalf Baechle extern void build_copy_page(void);
77384740dcSRalf Baechle 
78384740dcSRalf Baechle /*
79384740dcSRalf Baechle  * It's normally defined only for FLATMEM config but it's
80384740dcSRalf Baechle  * used in our early mem init code for all memory models.
81384740dcSRalf Baechle  * So always define it.
82384740dcSRalf Baechle  */
836c359eb1SPaul Burton #ifdef CONFIG_MIPS_AUTO_PFN_OFFSET
846c359eb1SPaul Burton extern unsigned long ARCH_PFN_OFFSET;
856c359eb1SPaul Burton # define ARCH_PFN_OFFSET	ARCH_PFN_OFFSET
866c359eb1SPaul Burton #else
87384740dcSRalf Baechle # define ARCH_PFN_OFFSET	PFN_UP(PHYS_OFFSET)
886c359eb1SPaul Burton #endif
89384740dcSRalf Baechle 
90384740dcSRalf Baechle extern void clear_page(void * page);
91384740dcSRalf Baechle extern void copy_page(void * to, void * from);
92384740dcSRalf Baechle 
93384740dcSRalf Baechle extern unsigned long shm_align_mask;
94384740dcSRalf Baechle 
pages_do_alias(unsigned long addr1,unsigned long addr2)95384740dcSRalf Baechle static inline unsigned long pages_do_alias(unsigned long addr1,
96384740dcSRalf Baechle 	unsigned long addr2)
97384740dcSRalf Baechle {
98384740dcSRalf Baechle 	return (addr1 ^ addr2) & shm_align_mask;
99384740dcSRalf Baechle }
100384740dcSRalf Baechle 
101384740dcSRalf Baechle struct page;
102384740dcSRalf Baechle 
clear_user_page(void * addr,unsigned long vaddr,struct page * page)103384740dcSRalf Baechle static inline void clear_user_page(void *addr, unsigned long vaddr,
104384740dcSRalf Baechle 	struct page *page)
105384740dcSRalf Baechle {
106384740dcSRalf Baechle 	extern void (*flush_data_cache_page)(unsigned long addr);
107384740dcSRalf Baechle 
108384740dcSRalf Baechle 	clear_page(addr);
109384740dcSRalf Baechle 	if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
110384740dcSRalf Baechle 		flush_data_cache_page((unsigned long)addr);
111384740dcSRalf Baechle }
112384740dcSRalf Baechle 
113384740dcSRalf Baechle struct vm_area_struct;
114384740dcSRalf Baechle extern void copy_user_highpage(struct page *to, struct page *from,
115384740dcSRalf Baechle 	unsigned long vaddr, struct vm_area_struct *vma);
116384740dcSRalf Baechle 
117384740dcSRalf Baechle #define __HAVE_ARCH_COPY_USER_HIGHPAGE
118384740dcSRalf Baechle 
119384740dcSRalf Baechle /*
120384740dcSRalf Baechle  * These are used to make use of C type-checking..
121384740dcSRalf Baechle  */
12234adb28dSRalf Baechle #ifdef CONFIG_PHYS_ADDR_T_64BIT
123384740dcSRalf Baechle   #ifdef CONFIG_CPU_MIPS32
124384740dcSRalf Baechle     typedef struct { unsigned long pte_low, pte_high; } pte_t;
125384740dcSRalf Baechle     #define pte_val(x)	  ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
126384740dcSRalf Baechle     #define __pte(x)	  ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
127384740dcSRalf Baechle   #else
128384740dcSRalf Baechle      typedef struct { unsigned long long pte; } pte_t;
129384740dcSRalf Baechle      #define pte_val(x) ((x).pte)
130384740dcSRalf Baechle      #define __pte(x)	((pte_t) { (x) } )
131384740dcSRalf Baechle   #endif
132384740dcSRalf Baechle #else
133384740dcSRalf Baechle typedef struct { unsigned long pte; } pte_t;
134384740dcSRalf Baechle #define pte_val(x)	((x).pte)
135384740dcSRalf Baechle #define __pte(x)	((pte_t) { (x) } )
136384740dcSRalf Baechle #endif
137384740dcSRalf Baechle typedef struct page *pgtable_t;
138384740dcSRalf Baechle 
139384740dcSRalf Baechle /*
140384740dcSRalf Baechle  * Right now we don't support 4-level pagetables, so all pud-related
141384740dcSRalf Baechle  * definitions come from <asm-generic/pgtable-nopud.h>.
142384740dcSRalf Baechle  */
143384740dcSRalf Baechle 
144384740dcSRalf Baechle /*
145384740dcSRalf Baechle  * Finall the top of the hierarchy, the pgd
146384740dcSRalf Baechle  */
147384740dcSRalf Baechle typedef struct { unsigned long pgd; } pgd_t;
148384740dcSRalf Baechle #define pgd_val(x)	((x).pgd)
149384740dcSRalf Baechle #define __pgd(x)	((pgd_t) { (x) } )
150384740dcSRalf Baechle 
151384740dcSRalf Baechle /*
152384740dcSRalf Baechle  * Manipulate page protection bits
153384740dcSRalf Baechle  */
154384740dcSRalf Baechle typedef struct { unsigned long pgprot; } pgprot_t;
155384740dcSRalf Baechle #define pgprot_val(x)	((x).pgprot)
156384740dcSRalf Baechle #define __pgprot(x)	((pgprot_t) { (x) } )
157b3a428b4SHassan Naveed #define pte_pgprot(x)	__pgprot(pte_val(x) & ~_PFN_MASK)
158384740dcSRalf Baechle 
159384740dcSRalf Baechle /*
160384740dcSRalf Baechle  * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
161384740dcSRalf Baechle  * pair of pages we only have a single global bit per pair of pages.  When
162384740dcSRalf Baechle  * writing to the TLB make sure we always have the bit set for both pages
163384740dcSRalf Baechle  * or none.  This macro is used to access the `buddy' of the pte we're just
164384740dcSRalf Baechle  * working on.
165384740dcSRalf Baechle  */
166384740dcSRalf Baechle #define ptep_buddy(x)	((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
167384740dcSRalf Baechle 
168384740dcSRalf Baechle /*
169384740dcSRalf Baechle  * __pa()/__va() should be used only during mem init.
170384740dcSRalf Baechle  */
___pa(unsigned long x)1710d8d83d0SPaul Burton static inline unsigned long ___pa(unsigned long x)
1720d8d83d0SPaul Burton {
173a5ff1b34SMasahiro Yamada 	if (IS_ENABLED(CONFIG_64BIT)) {
1740d8d83d0SPaul Burton 		/*
1750d8d83d0SPaul Burton 		 * For MIPS64 the virtual address may either be in one of
1760d8d83d0SPaul Burton 		 * the compatibility segements ckseg0 or ckseg1, or it may
1770d8d83d0SPaul Burton 		 * be in xkphys.
1780d8d83d0SPaul Burton 		 */
1790d8d83d0SPaul Burton 		return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x);
1800d8d83d0SPaul Burton 	}
1810d8d83d0SPaul Burton 
182a5ff1b34SMasahiro Yamada 	if (!IS_ENABLED(CONFIG_EVA)) {
1830d8d83d0SPaul Burton 		/*
1840d8d83d0SPaul Burton 		 * We're using the standard MIPS32 legacy memory map, ie.
1850d8d83d0SPaul Burton 		 * the address x is going to be in kseg0 or kseg1. We can
1860d8d83d0SPaul Burton 		 * handle either case by masking out the desired bits using
1870d8d83d0SPaul Burton 		 * CPHYSADDR.
1880d8d83d0SPaul Burton 		 */
1890d8d83d0SPaul Burton 		return CPHYSADDR(x);
1900d8d83d0SPaul Burton 	}
1910d8d83d0SPaul Burton 
1920d8d83d0SPaul Burton 	/*
1930d8d83d0SPaul Burton 	 * EVA is in use so the memory map could be anything, making it not
1940d8d83d0SPaul Burton 	 * safe to just mask out bits.
1950d8d83d0SPaul Burton 	 */
1960d8d83d0SPaul Burton 	return x - PAGE_OFFSET + PHYS_OFFSET;
1970d8d83d0SPaul Burton }
1980d8d83d0SPaul Burton #define __pa(x)		___pa((unsigned long)(x))
199384740dcSRalf Baechle #define __va(x)		((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
20049c426baSDavid Daney #include <asm/io.h>
2015707bf6bSRalf Baechle 
2025707bf6bSRalf Baechle /*
2035707bf6bSRalf Baechle  * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad
2045707bf6bSRalf Baechle  * (lmo) rsp. 8431fd094d625b94d364fe393076ccef88e6ce18 (kernel.org).  The
205e66ef72dSKees Cook  * discussion can be found in
206e66ef72dSKees Cook  * https://lore.kernel.org/lkml/a2ebde260608230500o3407b108hc03debb9da6e62c@mail.gmail.com
2075707bf6bSRalf Baechle  *
2085707bf6bSRalf Baechle  * It is unclear if the misscompilations mentioned in
209e66ef72dSKees Cook  * https://lore.kernel.org/lkml/1281303490-390-1-git-send-email-namhyung@gmail.com
210e66ef72dSKees Cook  * also affect MIPS so we keep this one until GCC 3.x has been retired
211e66ef72dSKees Cook  * before we can apply https://patchwork.linux-mips.org/patch/1541/
2125707bf6bSRalf Baechle  */
213*dfad83cbSFlorian Fainelli #define __pa_symbol_nodebug(x)	__pa(RELOC_HIDE((unsigned long)(x), 0))
214*dfad83cbSFlorian Fainelli 
215*dfad83cbSFlorian Fainelli #ifdef CONFIG_DEBUG_VIRTUAL
216*dfad83cbSFlorian Fainelli extern phys_addr_t __phys_addr_symbol(unsigned long x);
217*dfad83cbSFlorian Fainelli #else
218*dfad83cbSFlorian Fainelli #define __phys_addr_symbol(x)	__pa_symbol_nodebug(x)
219*dfad83cbSFlorian Fainelli #endif
2205707bf6bSRalf Baechle 
22127b3db20SLeonid Yegoshin #ifndef __pa_symbol
222*dfad83cbSFlorian Fainelli #define __pa_symbol(x)		__phys_addr_symbol((unsigned long)(x))
22327b3db20SLeonid Yegoshin #endif
224384740dcSRalf Baechle 
225384740dcSRalf Baechle #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
226384740dcSRalf Baechle 
22737d15948SFlorian Fainelli #define virt_to_pfn(kaddr)   	PFN_DOWN(virt_to_phys((void *)(kaddr)))
22837d15948SFlorian Fainelli #define virt_to_page(kaddr)	pfn_to_page(virt_to_pfn(kaddr))
229d3ce8843SRalf Baechle 
23031875a54SPaul Burton extern bool __virt_addr_valid(const volatile void *kaddr);
231d3ce8843SRalf Baechle #define virt_addr_valid(kaddr)						\
232d3ce8843SRalf Baechle 	__virt_addr_valid((const volatile void *) (kaddr))
233384740dcSRalf Baechle 
234c62da0c3SAnshuman Khandual #define VM_DATA_DEFAULT_FLAGS	VM_DATA_FLAGS_TSK_EXEC
235384740dcSRalf Baechle 
236d4d3ef8bSJinyang He extern unsigned long __kaslr_offset;
kaslr_offset(void)237d4d3ef8bSJinyang He static inline unsigned long kaslr_offset(void)
238d4d3ef8bSJinyang He {
239d4d3ef8bSJinyang He 	return __kaslr_offset;
240d4d3ef8bSJinyang He }
241d4d3ef8bSJinyang He 
242384740dcSRalf Baechle #include <asm-generic/memory_model.h>
2435b17e1cdSArnd Bergmann #include <asm-generic/getorder.h>
244384740dcSRalf Baechle 
245384740dcSRalf Baechle #endif /* _ASM_PAGE_H */
246