101a6221aSDavid Daney /* 201a6221aSDavid Daney * This file is subject to the terms and conditions of the GNU General Public 301a6221aSDavid Daney * License. See the file "COPYING" in the main directory of this archive 401a6221aSDavid Daney * for more details. 501a6221aSDavid Daney * 601a6221aSDavid Daney * Copyright (C) 2005-2009 Cavium Networks 701a6221aSDavid Daney */ 801a6221aSDavid Daney 901a6221aSDavid Daney #ifndef __PCI_OCTEON_H__ 1001a6221aSDavid Daney #define __PCI_OCTEON_H__ 1101a6221aSDavid Daney 1201a6221aSDavid Daney #include <linux/pci.h> 1301a6221aSDavid Daney 1401a6221aSDavid Daney /* 152b5987abSDavid Daney * The physical memory base mapped by BAR1. 256MB at the end of the 162b5987abSDavid Daney * first 4GB. 172b5987abSDavid Daney */ 182b5987abSDavid Daney #define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28)) 192b5987abSDavid Daney #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28) 202b5987abSDavid Daney 212b5987abSDavid Daney /* 222b5987abSDavid Daney * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, 232b5987abSDavid Daney * place BAR1 so it is the same for both. 242b5987abSDavid Daney */ 252b5987abSDavid Daney #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41) 262b5987abSDavid Daney 272b5987abSDavid Daney /* 2801a6221aSDavid Daney * pcibios_map_irq() is defined inside pci-octeon.c. All it does is 2901a6221aSDavid Daney * call the Octeon specific version pointed to by this variable. This 3001a6221aSDavid Daney * function needs to change for PCI or PCIe based hosts. 3101a6221aSDavid Daney */ 3201a6221aSDavid Daney extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, 3301a6221aSDavid Daney u8 slot, u8 pin); 3401a6221aSDavid Daney 3501a6221aSDavid Daney /* 36b93b2abcSDavid Daney * For PCI (not PCIe) the BAR2 base address. 37b93b2abcSDavid Daney */ 38b93b2abcSDavid Daney #define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull 39b93b2abcSDavid Daney 40b93b2abcSDavid Daney /* 41b93b2abcSDavid Daney * For PCI (not PCIe) the base of the memory mapped by BAR1 42b93b2abcSDavid Daney */ 43b93b2abcSDavid Daney extern u64 octeon_bar1_pci_phys; 44b93b2abcSDavid Daney 45b93b2abcSDavid Daney /* 4601a6221aSDavid Daney * The following defines are used when octeon_dma_bar_type = 4701a6221aSDavid Daney * OCTEON_DMA_BAR_TYPE_BIG 4801a6221aSDavid Daney */ 4901a6221aSDavid Daney #define OCTEON_PCI_BAR1_HOLE_BITS 5 5001a6221aSDavid Daney #define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3)) 5101a6221aSDavid Daney 5201a6221aSDavid Daney enum octeon_dma_bar_type { 5301a6221aSDavid Daney OCTEON_DMA_BAR_TYPE_INVALID, 5401a6221aSDavid Daney OCTEON_DMA_BAR_TYPE_SMALL, 5501a6221aSDavid Daney OCTEON_DMA_BAR_TYPE_BIG, 56714c1f5cSDavid Daney OCTEON_DMA_BAR_TYPE_PCIE, 57714c1f5cSDavid Daney OCTEON_DMA_BAR_TYPE_PCIE2 5801a6221aSDavid Daney }; 5901a6221aSDavid Daney 6001a6221aSDavid Daney /* 6101a6221aSDavid Daney * This tells the DMA mapping system in dma-octeon.c how to map PCI 6201a6221aSDavid Daney * DMA addresses. 6301a6221aSDavid Daney */ 6401a6221aSDavid Daney extern enum octeon_dma_bar_type octeon_dma_bar_type; 6501a6221aSDavid Daney 66a330a9c5SChristoph Hellwig void octeon_pci_dma_init(void); 67a330a9c5SChristoph Hellwig extern char *octeon_swiotlb; 68a330a9c5SChristoph Hellwig 6901a6221aSDavid Daney #endif 70