1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2008 Cavium Networks 7 */ 8 #ifndef __ASM_OCTEON_OCTEON_H 9 #define __ASM_OCTEON_OCTEON_H 10 11 #include <asm/octeon/cvmx.h> 12 #include <asm/bitfield.h> 13 14 extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size, 15 uint64_t alignment, 16 uint64_t min_addr, 17 uint64_t max_addr, 18 int do_locking); 19 extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment, 20 int do_locking); 21 extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment, 22 uint64_t min_addr, uint64_t max_addr, 23 int do_locking); 24 extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment, 25 char *name); 26 extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, 27 uint64_t max_addr, uint64_t align, 28 char *name); 29 extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address, 30 char *name); 31 extern int octeon_bootmem_free_named(char *name); 32 extern void octeon_bootmem_lock(void); 33 extern void octeon_bootmem_unlock(void); 34 35 extern int octeon_is_simulation(void); 36 extern int octeon_is_pci_host(void); 37 extern int octeon_usb_is_ref_clk(void); 38 extern uint64_t octeon_get_clock_rate(void); 39 extern u64 octeon_get_io_clock_rate(void); 40 extern const char *octeon_board_type_string(void); 41 extern const char *octeon_get_pci_interrupts(void); 42 extern int octeon_get_southbridge_interrupt(void); 43 extern int octeon_get_boot_coremask(void); 44 extern int octeon_get_boot_num_arguments(void); 45 extern const char *octeon_get_boot_argument(int arg); 46 extern void octeon_user_io_init(void); 47 48 extern void octeon_init_cvmcount(void); 49 extern void octeon_setup_delays(void); 50 extern void octeon_io_clk_delay(unsigned long); 51 52 #define OCTEON_ARGV_MAX_ARGS 64 53 #define OCTEON_SERIAL_LEN 20 54 55 struct octeon_boot_descriptor { 56 #ifdef __BIG_ENDIAN_BITFIELD 57 /* Start of block referenced by assembly code - do not change! */ 58 uint32_t desc_version; 59 uint32_t desc_size; 60 uint64_t stack_top; 61 uint64_t heap_base; 62 uint64_t heap_end; 63 /* Only used by bootloader */ 64 uint64_t entry_point; 65 uint64_t desc_vaddr; 66 /* End of This block referenced by assembly code - do not change! */ 67 uint32_t exception_base_addr; 68 uint32_t stack_size; 69 uint32_t heap_size; 70 /* Argc count for application. */ 71 uint32_t argc; 72 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 73 74 #define BOOT_FLAG_INIT_CORE (1 << 0) 75 #define OCTEON_BL_FLAG_DEBUG (1 << 1) 76 #define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) 77 /* If set, use uart1 for console */ 78 #define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) 79 /* If set, use PCI console */ 80 #define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) 81 /* Call exit on break on serial port */ 82 #define OCTEON_BL_FLAG_BREAK (1 << 5) 83 84 uint32_t flags; 85 uint32_t core_mask; 86 /* DRAM size in megabyes. */ 87 uint32_t dram_size; 88 /* physical address of free memory descriptor block. */ 89 uint32_t phy_mem_desc_addr; 90 /* used to pass flags from app to debugger. */ 91 uint32_t debugger_flags_base_addr; 92 /* CPU clock speed, in hz. */ 93 uint32_t eclock_hz; 94 /* DRAM clock speed, in hz. */ 95 uint32_t dclock_hz; 96 /* SPI4 clock in hz. */ 97 uint32_t spi_clock_hz; 98 uint16_t board_type; 99 uint8_t board_rev_major; 100 uint8_t board_rev_minor; 101 uint16_t chip_type; 102 uint8_t chip_rev_major; 103 uint8_t chip_rev_minor; 104 char board_serial_number[OCTEON_SERIAL_LEN]; 105 uint8_t mac_addr_base[6]; 106 uint8_t mac_addr_count; 107 uint64_t cvmx_desc_vaddr; 108 #else 109 uint32_t desc_size; 110 uint32_t desc_version; 111 uint64_t stack_top; 112 uint64_t heap_base; 113 uint64_t heap_end; 114 /* Only used by bootloader */ 115 uint64_t entry_point; 116 uint64_t desc_vaddr; 117 /* End of This block referenced by assembly code - do not change! */ 118 uint32_t stack_size; 119 uint32_t exception_base_addr; 120 uint32_t argc; 121 uint32_t heap_size; 122 /* 123 * Argc count for application. 124 * Warning low bit scrambled in little-endian. 125 */ 126 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 127 128 #define BOOT_FLAG_INIT_CORE (1 << 0) 129 #define OCTEON_BL_FLAG_DEBUG (1 << 1) 130 #define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) 131 /* If set, use uart1 for console */ 132 #define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) 133 /* If set, use PCI console */ 134 #define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) 135 /* Call exit on break on serial port */ 136 #define OCTEON_BL_FLAG_BREAK (1 << 5) 137 138 uint32_t core_mask; 139 uint32_t flags; 140 /* physical address of free memory descriptor block. */ 141 uint32_t phy_mem_desc_addr; 142 /* DRAM size in megabyes. */ 143 uint32_t dram_size; 144 /* CPU clock speed, in hz. */ 145 uint32_t eclock_hz; 146 /* used to pass flags from app to debugger. */ 147 uint32_t debugger_flags_base_addr; 148 /* SPI4 clock in hz. */ 149 uint32_t spi_clock_hz; 150 /* DRAM clock speed, in hz. */ 151 uint32_t dclock_hz; 152 uint8_t chip_rev_minor; 153 uint8_t chip_rev_major; 154 uint16_t chip_type; 155 uint8_t board_rev_minor; 156 uint8_t board_rev_major; 157 uint16_t board_type; 158 159 uint64_t unused1[4]; /* Not even filled in by bootloader. */ 160 161 uint64_t cvmx_desc_vaddr; 162 #endif 163 }; 164 165 union octeon_cvmemctl { 166 uint64_t u64; 167 struct { 168 /* RO 1 = BIST fail, 0 = BIST pass */ 169 __BITFIELD_FIELD(uint64_t tlbbist:1, 170 /* RO 1 = BIST fail, 0 = BIST pass */ 171 __BITFIELD_FIELD(uint64_t l1cbist:1, 172 /* RO 1 = BIST fail, 0 = BIST pass */ 173 __BITFIELD_FIELD(uint64_t l1dbist:1, 174 /* RO 1 = BIST fail, 0 = BIST pass */ 175 __BITFIELD_FIELD(uint64_t dcmbist:1, 176 /* RO 1 = BIST fail, 0 = BIST pass */ 177 __BITFIELD_FIELD(uint64_t ptgbist:1, 178 /* RO 1 = BIST fail, 0 = BIST pass */ 179 __BITFIELD_FIELD(uint64_t wbfbist:1, 180 /* Reserved */ 181 __BITFIELD_FIELD(uint64_t reserved:17, 182 /* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU. 183 * This field selects between the TLB replacement policies: 184 * bitmask LRU or NLU. Bitmask LRU maintains a mask of 185 * recently used TLB entries and avoids them as new entries 186 * are allocated. NLU simply guarantees that the next 187 * allocation is not the last used TLB entry. */ 188 __BITFIELD_FIELD(uint64_t tlbnlu:1, 189 /* OCTEON II - Selects the bit in the counter used for 190 * releasing a PAUSE. This counter trips every 2(8+PAUSETIME) 191 * cycles. If not already released, the cnMIPS II core will 192 * always release a given PAUSE instruction within 193 * 2(8+PAUSETIME). If the counter trip happens to line up, 194 * the cnMIPS II core may release the PAUSE instantly. */ 195 __BITFIELD_FIELD(uint64_t pausetime:3, 196 /* OCTEON II - This field is an extension of 197 * CvmMemCtl[DIDTTO] */ 198 __BITFIELD_FIELD(uint64_t didtto2:1, 199 /* R/W If set, marked write-buffer entries time out 200 * the same as other entries; if clear, marked 201 * write-buffer entries use the maximum timeout. */ 202 __BITFIELD_FIELD(uint64_t dismarkwblongto:1, 203 /* R/W If set, a merged store does not clear the 204 * write-buffer entry timeout state. */ 205 __BITFIELD_FIELD(uint64_t dismrgclrwbto:1, 206 /* R/W Two bits that are the MSBs of the resultant 207 * CVMSEG LM word location for an IOBDMA. The other 8 208 * bits come from the SCRADDR field of the IOBDMA. */ 209 __BITFIELD_FIELD(uint64_t iobdmascrmsb:2, 210 /* R/W If set, SYNCWS and SYNCS only order marked 211 * stores; if clear, SYNCWS and SYNCS only order 212 * unmarked stores. SYNCWSMARKED has no effect when 213 * DISSYNCWS is set. */ 214 __BITFIELD_FIELD(uint64_t syncwsmarked:1, 215 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as 216 * SYNC. */ 217 __BITFIELD_FIELD(uint64_t dissyncws:1, 218 /* R/W If set, no stall happens on write buffer 219 * full. */ 220 __BITFIELD_FIELD(uint64_t diswbfst:1, 221 /* R/W If set (and SX set), supervisor-level 222 * loads/stores can use XKPHYS addresses with 223 * VA<48>==0 */ 224 __BITFIELD_FIELD(uint64_t xkmemenas:1, 225 /* R/W If set (and UX set), user-level loads/stores 226 * can use XKPHYS addresses with VA<48>==0 */ 227 __BITFIELD_FIELD(uint64_t xkmemenau:1, 228 /* R/W If set (and SX set), supervisor-level 229 * loads/stores can use XKPHYS addresses with 230 * VA<48>==1 */ 231 __BITFIELD_FIELD(uint64_t xkioenas:1, 232 /* R/W If set (and UX set), user-level loads/stores 233 * can use XKPHYS addresses with VA<48>==1 */ 234 __BITFIELD_FIELD(uint64_t xkioenau:1, 235 /* R/W If set, all stores act as SYNCW (NOMERGE must 236 * be set when this is set) RW, reset to 0. */ 237 __BITFIELD_FIELD(uint64_t allsyncw:1, 238 /* R/W If set, no stores merge, and all stores reach 239 * the coherent bus in order. */ 240 __BITFIELD_FIELD(uint64_t nomerge:1, 241 /* R/W Selects the bit in the counter used for DID 242 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 = 243 * 214. Actual time-out is between 1x and 2x this 244 * interval. For example, with DIDTTO=3, expiration 245 * interval is between 16K and 32K. */ 246 __BITFIELD_FIELD(uint64_t didtto:2, 247 /* R/W If set, the (mem) CSR clock never turns off. */ 248 __BITFIELD_FIELD(uint64_t csrckalwys:1, 249 /* R/W If set, mclk never turns off. */ 250 __BITFIELD_FIELD(uint64_t mclkalwys:1, 251 /* R/W Selects the bit in the counter used for write 252 * buffer flush time-outs (WBFLT+11) is the bit 253 * position in an internal counter used to determine 254 * expiration. The write buffer expires between 1x and 255 * 2x this interval. For example, with WBFLT = 0, a 256 * write buffer expires between 2K and 4K cycles after 257 * the write buffer entry is allocated. */ 258 __BITFIELD_FIELD(uint64_t wbfltime:3, 259 /* R/W If set, do not put Istream in the L2 cache. */ 260 __BITFIELD_FIELD(uint64_t istrnol2:1, 261 /* R/W The write buffer threshold. */ 262 __BITFIELD_FIELD(uint64_t wbthresh:4, 263 /* Reserved */ 264 __BITFIELD_FIELD(uint64_t reserved2:2, 265 /* R/W If set, CVMSEG is available for loads/stores in 266 * kernel/debug mode. */ 267 __BITFIELD_FIELD(uint64_t cvmsegenak:1, 268 /* R/W If set, CVMSEG is available for loads/stores in 269 * supervisor mode. */ 270 __BITFIELD_FIELD(uint64_t cvmsegenas:1, 271 /* R/W If set, CVMSEG is available for loads/stores in 272 * user mode. */ 273 __BITFIELD_FIELD(uint64_t cvmsegenau:1, 274 /* R/W Size of local memory in cache blocks, 54 (6912 275 * bytes) is max legal value. */ 276 __BITFIELD_FIELD(uint64_t lmemsz:6, 277 ;))))))))))))))))))))))))))))))))) 278 } s; 279 }; 280 281 extern void octeon_check_cpu_bist(void); 282 283 int octeon_prune_device_tree(void); 284 extern const char __dtb_octeon_3xxx_begin; 285 extern const char __dtb_octeon_68xx_begin; 286 287 /** 288 * Write a 32bit value to the Octeon NPI register space 289 * 290 * @address: Address to write to 291 * @val: Value to write 292 */ 293 static inline void octeon_npi_write32(uint64_t address, uint32_t val) 294 { 295 cvmx_write64_uint32(address ^ 4, val); 296 cvmx_read64_uint32(address ^ 4); 297 } 298 299 #ifdef CONFIG_SMP 300 void octeon_setup_smp(void); 301 #else 302 static inline void octeon_setup_smp(void) {} 303 #endif 304 305 struct irq_domain; 306 struct device_node; 307 struct irq_data; 308 struct irq_chip; 309 void octeon_ciu3_mbox_send(int cpu, unsigned int mbox); 310 int octeon_irq_ciu3_xlat(struct irq_domain *d, 311 struct device_node *node, 312 const u32 *intspec, 313 unsigned int intsize, 314 unsigned long *out_hwirq, 315 unsigned int *out_type); 316 void octeon_irq_ciu3_enable(struct irq_data *data); 317 void octeon_irq_ciu3_disable(struct irq_data *data); 318 void octeon_irq_ciu3_ack(struct irq_data *data); 319 void octeon_irq_ciu3_mask(struct irq_data *data); 320 void octeon_irq_ciu3_mask_ack(struct irq_data *data); 321 int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq, 322 irq_hw_number_t hw, struct irq_chip *chip); 323 324 /* Octeon multiplier save/restore routines from octeon_switch.S */ 325 void octeon_mult_save(void); 326 void octeon_mult_restore(void); 327 void octeon_mult_save_end(void); 328 void octeon_mult_restore_end(void); 329 void octeon_mult_save3(void); 330 void octeon_mult_save3_end(void); 331 void octeon_mult_save2(void); 332 void octeon_mult_save2_end(void); 333 void octeon_mult_restore3(void); 334 void octeon_mult_restore3_end(void); 335 void octeon_mult_restore2(void); 336 void octeon_mult_restore2_end(void); 337 338 /** 339 * Read a 32bit value from the Octeon NPI register space 340 * 341 * @address: Address to read 342 * Returns The result 343 */ 344 static inline uint32_t octeon_npi_read32(uint64_t address) 345 { 346 return cvmx_read64_uint32(address ^ 4); 347 } 348 349 extern struct cvmx_bootinfo *octeon_bootinfo; 350 351 extern uint64_t octeon_bootloader_entry_addr; 352 353 extern void (*octeon_irq_setup_secondary)(void); 354 355 typedef void (*octeon_irq_ip4_handler_t)(void); 356 void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); 357 358 extern void octeon_fixup_irqs(void); 359 360 extern struct semaphore octeon_bootbus_sem; 361 362 struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block); 363 364 #endif /* __ASM_OCTEON_OCTEON_H */ 365