1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004-2008 Cavium Networks 7 */ 8 #ifndef __ASM_OCTEON_OCTEON_H 9 #define __ASM_OCTEON_OCTEON_H 10 11 #include <asm/octeon/cvmx.h> 12 13 extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size, 14 uint64_t alignment, 15 uint64_t min_addr, 16 uint64_t max_addr, 17 int do_locking); 18 extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment, 19 int do_locking); 20 extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment, 21 uint64_t min_addr, uint64_t max_addr, 22 int do_locking); 23 extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment, 24 char *name); 25 extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, 26 uint64_t max_addr, uint64_t align, 27 char *name); 28 extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address, 29 char *name); 30 extern int octeon_bootmem_free_named(char *name); 31 extern void octeon_bootmem_lock(void); 32 extern void octeon_bootmem_unlock(void); 33 34 extern int octeon_is_simulation(void); 35 extern int octeon_is_pci_host(void); 36 extern int octeon_usb_is_ref_clk(void); 37 extern uint64_t octeon_get_clock_rate(void); 38 extern u64 octeon_get_io_clock_rate(void); 39 extern const char *octeon_board_type_string(void); 40 extern const char *octeon_get_pci_interrupts(void); 41 extern int octeon_get_southbridge_interrupt(void); 42 extern int octeon_get_boot_coremask(void); 43 extern int octeon_get_boot_num_arguments(void); 44 extern const char *octeon_get_boot_argument(int arg); 45 extern void octeon_hal_setup_reserved32(void); 46 extern void octeon_user_io_init(void); 47 struct octeon_cop2_state; 48 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); 49 extern void octeon_crypto_disable(struct octeon_cop2_state *state, 50 unsigned long flags); 51 extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); 52 53 extern void octeon_init_cvmcount(void); 54 extern void octeon_setup_delays(void); 55 extern void octeon_io_clk_delay(unsigned long); 56 57 #define OCTEON_ARGV_MAX_ARGS 64 58 #define OCTOEN_SERIAL_LEN 20 59 60 struct octeon_boot_descriptor { 61 /* Start of block referenced by assembly code - do not change! */ 62 uint32_t desc_version; 63 uint32_t desc_size; 64 uint64_t stack_top; 65 uint64_t heap_base; 66 uint64_t heap_end; 67 /* Only used by bootloader */ 68 uint64_t entry_point; 69 uint64_t desc_vaddr; 70 /* End of This block referenced by assembly code - do not change! */ 71 uint32_t exception_base_addr; 72 uint32_t stack_size; 73 uint32_t heap_size; 74 /* Argc count for application. */ 75 uint32_t argc; 76 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 77 78 #define BOOT_FLAG_INIT_CORE (1 << 0) 79 #define OCTEON_BL_FLAG_DEBUG (1 << 1) 80 #define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) 81 /* If set, use uart1 for console */ 82 #define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) 83 /* If set, use PCI console */ 84 #define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) 85 /* Call exit on break on serial port */ 86 #define OCTEON_BL_FLAG_BREAK (1 << 5) 87 88 uint32_t flags; 89 uint32_t core_mask; 90 /* DRAM size in megabyes. */ 91 uint32_t dram_size; 92 /* physical address of free memory descriptor block. */ 93 uint32_t phy_mem_desc_addr; 94 /* used to pass flags from app to debugger. */ 95 uint32_t debugger_flags_base_addr; 96 /* CPU clock speed, in hz. */ 97 uint32_t eclock_hz; 98 /* DRAM clock speed, in hz. */ 99 uint32_t dclock_hz; 100 /* SPI4 clock in hz. */ 101 uint32_t spi_clock_hz; 102 uint16_t board_type; 103 uint8_t board_rev_major; 104 uint8_t board_rev_minor; 105 uint16_t chip_type; 106 uint8_t chip_rev_major; 107 uint8_t chip_rev_minor; 108 char board_serial_number[OCTOEN_SERIAL_LEN]; 109 uint8_t mac_addr_base[6]; 110 uint8_t mac_addr_count; 111 uint64_t cvmx_desc_vaddr; 112 }; 113 114 union octeon_cvmemctl { 115 uint64_t u64; 116 struct { 117 /* RO 1 = BIST fail, 0 = BIST pass */ 118 uint64_t tlbbist:1; 119 /* RO 1 = BIST fail, 0 = BIST pass */ 120 uint64_t l1cbist:1; 121 /* RO 1 = BIST fail, 0 = BIST pass */ 122 uint64_t l1dbist:1; 123 /* RO 1 = BIST fail, 0 = BIST pass */ 124 uint64_t dcmbist:1; 125 /* RO 1 = BIST fail, 0 = BIST pass */ 126 uint64_t ptgbist:1; 127 /* RO 1 = BIST fail, 0 = BIST pass */ 128 uint64_t wbfbist:1; 129 /* Reserved */ 130 uint64_t reserved:22; 131 /* R/W If set, marked write-buffer entries time out 132 * the same as as other entries; if clear, marked 133 * write-buffer entries use the maximum timeout. */ 134 uint64_t dismarkwblongto:1; 135 /* R/W If set, a merged store does not clear the 136 * write-buffer entry timeout state. */ 137 uint64_t dismrgclrwbto:1; 138 /* R/W Two bits that are the MSBs of the resultant 139 * CVMSEG LM word location for an IOBDMA. The other 8 140 * bits come from the SCRADDR field of the IOBDMA. */ 141 uint64_t iobdmascrmsb:2; 142 /* R/W If set, SYNCWS and SYNCS only order marked 143 * stores; if clear, SYNCWS and SYNCS only order 144 * unmarked stores. SYNCWSMARKED has no effect when 145 * DISSYNCWS is set. */ 146 uint64_t syncwsmarked:1; 147 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as 148 * SYNC. */ 149 uint64_t dissyncws:1; 150 /* R/W If set, no stall happens on write buffer 151 * full. */ 152 uint64_t diswbfst:1; 153 /* R/W If set (and SX set), supervisor-level 154 * loads/stores can use XKPHYS addresses with 155 * VA<48>==0 */ 156 uint64_t xkmemenas:1; 157 /* R/W If set (and UX set), user-level loads/stores 158 * can use XKPHYS addresses with VA<48>==0 */ 159 uint64_t xkmemenau:1; 160 /* R/W If set (and SX set), supervisor-level 161 * loads/stores can use XKPHYS addresses with 162 * VA<48>==1 */ 163 uint64_t xkioenas:1; 164 /* R/W If set (and UX set), user-level loads/stores 165 * can use XKPHYS addresses with VA<48>==1 */ 166 uint64_t xkioenau:1; 167 /* R/W If set, all stores act as SYNCW (NOMERGE must 168 * be set when this is set) RW, reset to 0. */ 169 uint64_t allsyncw:1; 170 /* R/W If set, no stores merge, and all stores reach 171 * the coherent bus in order. */ 172 uint64_t nomerge:1; 173 /* R/W Selects the bit in the counter used for DID 174 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 = 175 * 214. Actual time-out is between 1x and 2x this 176 * interval. For example, with DIDTTO=3, expiration 177 * interval is between 16K and 32K. */ 178 uint64_t didtto:2; 179 /* R/W If set, the (mem) CSR clock never turns off. */ 180 uint64_t csrckalwys:1; 181 /* R/W If set, mclk never turns off. */ 182 uint64_t mclkalwys:1; 183 /* R/W Selects the bit in the counter used for write 184 * buffer flush time-outs (WBFLT+11) is the bit 185 * position in an internal counter used to determine 186 * expiration. The write buffer expires between 1x and 187 * 2x this interval. For example, with WBFLT = 0, a 188 * write buffer expires between 2K and 4K cycles after 189 * the write buffer entry is allocated. */ 190 uint64_t wbfltime:3; 191 /* R/W If set, do not put Istream in the L2 cache. */ 192 uint64_t istrnol2:1; 193 /* R/W The write buffer threshold. */ 194 uint64_t wbthresh:4; 195 /* Reserved */ 196 uint64_t reserved2:2; 197 /* R/W If set, CVMSEG is available for loads/stores in 198 * kernel/debug mode. */ 199 uint64_t cvmsegenak:1; 200 /* R/W If set, CVMSEG is available for loads/stores in 201 * supervisor mode. */ 202 uint64_t cvmsegenas:1; 203 /* R/W If set, CVMSEG is available for loads/stores in 204 * user mode. */ 205 uint64_t cvmsegenau:1; 206 /* R/W Size of local memory in cache blocks, 54 (6912 207 * bytes) is max legal value. */ 208 uint64_t lmemsz:6; 209 } s; 210 }; 211 212 extern void octeon_write_lcd(const char *s); 213 extern void octeon_check_cpu_bist(void); 214 extern int octeon_get_boot_uart(void); 215 216 struct uart_port; 217 extern unsigned int octeon_serial_in(struct uart_port *, int); 218 extern void octeon_serial_out(struct uart_port *, int, int); 219 220 /** 221 * Write a 32bit value to the Octeon NPI register space 222 * 223 * @address: Address to write to 224 * @val: Value to write 225 */ 226 static inline void octeon_npi_write32(uint64_t address, uint32_t val) 227 { 228 cvmx_write64_uint32(address ^ 4, val); 229 cvmx_read64_uint32(address ^ 4); 230 } 231 232 233 /** 234 * Read a 32bit value from the Octeon NPI register space 235 * 236 * @address: Address to read 237 * Returns The result 238 */ 239 static inline uint32_t octeon_npi_read32(uint64_t address) 240 { 241 return cvmx_read64_uint32(address ^ 4); 242 } 243 244 extern struct cvmx_bootinfo *octeon_bootinfo; 245 246 extern uint64_t octeon_bootloader_entry_addr; 247 248 extern void (*octeon_irq_setup_secondary)(void); 249 250 typedef void (*octeon_irq_ip4_handler_t)(void); 251 void octeon_irq_set_ip4_handler(octeon_irq_ip4_handler_t); 252 253 extern void octeon_fixup_irqs(void); 254 255 #endif /* __ASM_OCTEON_OCTEON_H */ 256