1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2011 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_SRIOX_DEFS_H__ 29 #define __CVMX_SRIOX_DEFS_H__ 30 31 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull) 32 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull) 33 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull) 34 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull) 35 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull) 36 #define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull) 37 #define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) 38 #define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) 39 #define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8) 40 #define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull) 41 #define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull) 42 #define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull) 43 #define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull) 44 #define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull) 45 #define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull) 46 #define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull) 47 #define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull) 48 #define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull) 49 #define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull) 50 #define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull) 51 #define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull) 52 #define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull) 53 #define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull) 54 #define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull) 55 #define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull) 56 #define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 57 #define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 58 #define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 59 #define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 60 #define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 61 #define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull) 62 #define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64) 63 #define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) 64 #define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull) 65 #define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull) 66 #define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull) 67 #define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8) 68 #define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull) 69 #define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull) 70 #define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull) 71 #define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull) 72 #define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull) 73 #define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull) 74 #define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull) 75 #define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull) 76 #define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull) 77 #define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull) 78 79 union cvmx_sriox_acc_ctrl { 80 uint64_t u64; 81 struct cvmx_sriox_acc_ctrl_s { 82 uint64_t reserved_7_63:57; 83 uint64_t deny_adr2:1; 84 uint64_t deny_adr1:1; 85 uint64_t deny_adr0:1; 86 uint64_t reserved_3_3:1; 87 uint64_t deny_bar2:1; 88 uint64_t deny_bar1:1; 89 uint64_t deny_bar0:1; 90 } s; 91 struct cvmx_sriox_acc_ctrl_cn63xx { 92 uint64_t reserved_3_63:61; 93 uint64_t deny_bar2:1; 94 uint64_t deny_bar1:1; 95 uint64_t deny_bar0:1; 96 } cn63xx; 97 struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1; 98 struct cvmx_sriox_acc_ctrl_s cn66xx; 99 }; 100 101 union cvmx_sriox_asmbly_id { 102 uint64_t u64; 103 struct cvmx_sriox_asmbly_id_s { 104 uint64_t reserved_32_63:32; 105 uint64_t assy_id:16; 106 uint64_t assy_ven:16; 107 } s; 108 struct cvmx_sriox_asmbly_id_s cn63xx; 109 struct cvmx_sriox_asmbly_id_s cn63xxp1; 110 struct cvmx_sriox_asmbly_id_s cn66xx; 111 }; 112 113 union cvmx_sriox_asmbly_info { 114 uint64_t u64; 115 struct cvmx_sriox_asmbly_info_s { 116 uint64_t reserved_32_63:32; 117 uint64_t assy_rev:16; 118 uint64_t reserved_0_15:16; 119 } s; 120 struct cvmx_sriox_asmbly_info_s cn63xx; 121 struct cvmx_sriox_asmbly_info_s cn63xxp1; 122 struct cvmx_sriox_asmbly_info_s cn66xx; 123 }; 124 125 union cvmx_sriox_bell_resp_ctrl { 126 uint64_t u64; 127 struct cvmx_sriox_bell_resp_ctrl_s { 128 uint64_t reserved_6_63:58; 129 uint64_t rp1_sid:1; 130 uint64_t rp0_sid:2; 131 uint64_t rp1_pid:1; 132 uint64_t rp0_pid:2; 133 } s; 134 struct cvmx_sriox_bell_resp_ctrl_s cn63xx; 135 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1; 136 struct cvmx_sriox_bell_resp_ctrl_s cn66xx; 137 }; 138 139 union cvmx_sriox_bist_status { 140 uint64_t u64; 141 struct cvmx_sriox_bist_status_s { 142 uint64_t reserved_45_63:19; 143 uint64_t lram:1; 144 uint64_t mram:2; 145 uint64_t cram:2; 146 uint64_t bell:2; 147 uint64_t otag:2; 148 uint64_t itag:1; 149 uint64_t ofree:1; 150 uint64_t rtn:2; 151 uint64_t obulk:4; 152 uint64_t optrs:4; 153 uint64_t oarb2:2; 154 uint64_t rxbuf2:2; 155 uint64_t oarb:2; 156 uint64_t ispf:1; 157 uint64_t ospf:1; 158 uint64_t txbuf:2; 159 uint64_t rxbuf:2; 160 uint64_t imsg:5; 161 uint64_t omsg:7; 162 } s; 163 struct cvmx_sriox_bist_status_cn63xx { 164 uint64_t reserved_44_63:20; 165 uint64_t mram:2; 166 uint64_t cram:2; 167 uint64_t bell:2; 168 uint64_t otag:2; 169 uint64_t itag:1; 170 uint64_t ofree:1; 171 uint64_t rtn:2; 172 uint64_t obulk:4; 173 uint64_t optrs:4; 174 uint64_t oarb2:2; 175 uint64_t rxbuf2:2; 176 uint64_t oarb:2; 177 uint64_t ispf:1; 178 uint64_t ospf:1; 179 uint64_t txbuf:2; 180 uint64_t rxbuf:2; 181 uint64_t imsg:5; 182 uint64_t omsg:7; 183 } cn63xx; 184 struct cvmx_sriox_bist_status_cn63xxp1 { 185 uint64_t reserved_44_63:20; 186 uint64_t mram:2; 187 uint64_t cram:2; 188 uint64_t bell:2; 189 uint64_t otag:2; 190 uint64_t itag:1; 191 uint64_t ofree:1; 192 uint64_t rtn:2; 193 uint64_t obulk:4; 194 uint64_t optrs:4; 195 uint64_t reserved_20_23:4; 196 uint64_t oarb:2; 197 uint64_t ispf:1; 198 uint64_t ospf:1; 199 uint64_t txbuf:2; 200 uint64_t rxbuf:2; 201 uint64_t imsg:5; 202 uint64_t omsg:7; 203 } cn63xxp1; 204 struct cvmx_sriox_bist_status_s cn66xx; 205 }; 206 207 union cvmx_sriox_imsg_ctrl { 208 uint64_t u64; 209 struct cvmx_sriox_imsg_ctrl_s { 210 uint64_t reserved_32_63:32; 211 uint64_t to_mode:1; 212 uint64_t reserved_30_30:1; 213 uint64_t rsp_thr:6; 214 uint64_t reserved_22_23:2; 215 uint64_t rp1_sid:1; 216 uint64_t rp0_sid:2; 217 uint64_t rp1_pid:1; 218 uint64_t rp0_pid:2; 219 uint64_t reserved_15_15:1; 220 uint64_t prt_sel:3; 221 uint64_t lttr:4; 222 uint64_t prio:4; 223 uint64_t mbox:4; 224 } s; 225 struct cvmx_sriox_imsg_ctrl_s cn63xx; 226 struct cvmx_sriox_imsg_ctrl_s cn63xxp1; 227 struct cvmx_sriox_imsg_ctrl_s cn66xx; 228 }; 229 230 union cvmx_sriox_imsg_inst_hdrx { 231 uint64_t u64; 232 struct cvmx_sriox_imsg_inst_hdrx_s { 233 uint64_t r:1; 234 uint64_t reserved_58_62:5; 235 uint64_t pm:2; 236 uint64_t reserved_55_55:1; 237 uint64_t sl:7; 238 uint64_t reserved_46_47:2; 239 uint64_t nqos:1; 240 uint64_t ngrp:1; 241 uint64_t ntt:1; 242 uint64_t ntag:1; 243 uint64_t reserved_35_41:7; 244 uint64_t rs:1; 245 uint64_t tt:2; 246 uint64_t tag:32; 247 } s; 248 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx; 249 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1; 250 struct cvmx_sriox_imsg_inst_hdrx_s cn66xx; 251 }; 252 253 union cvmx_sriox_imsg_qos_grpx { 254 uint64_t u64; 255 struct cvmx_sriox_imsg_qos_grpx_s { 256 uint64_t reserved_63_63:1; 257 uint64_t qos7:3; 258 uint64_t grp7:4; 259 uint64_t reserved_55_55:1; 260 uint64_t qos6:3; 261 uint64_t grp6:4; 262 uint64_t reserved_47_47:1; 263 uint64_t qos5:3; 264 uint64_t grp5:4; 265 uint64_t reserved_39_39:1; 266 uint64_t qos4:3; 267 uint64_t grp4:4; 268 uint64_t reserved_31_31:1; 269 uint64_t qos3:3; 270 uint64_t grp3:4; 271 uint64_t reserved_23_23:1; 272 uint64_t qos2:3; 273 uint64_t grp2:4; 274 uint64_t reserved_15_15:1; 275 uint64_t qos1:3; 276 uint64_t grp1:4; 277 uint64_t reserved_7_7:1; 278 uint64_t qos0:3; 279 uint64_t grp0:4; 280 } s; 281 struct cvmx_sriox_imsg_qos_grpx_s cn63xx; 282 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1; 283 struct cvmx_sriox_imsg_qos_grpx_s cn66xx; 284 }; 285 286 union cvmx_sriox_imsg_statusx { 287 uint64_t u64; 288 struct cvmx_sriox_imsg_statusx_s { 289 uint64_t val1:1; 290 uint64_t err1:1; 291 uint64_t toe1:1; 292 uint64_t toc1:1; 293 uint64_t prt1:1; 294 uint64_t reserved_58_58:1; 295 uint64_t tt1:1; 296 uint64_t dis1:1; 297 uint64_t seg1:4; 298 uint64_t mbox1:2; 299 uint64_t lttr1:2; 300 uint64_t sid1:16; 301 uint64_t val0:1; 302 uint64_t err0:1; 303 uint64_t toe0:1; 304 uint64_t toc0:1; 305 uint64_t prt0:1; 306 uint64_t reserved_26_26:1; 307 uint64_t tt0:1; 308 uint64_t dis0:1; 309 uint64_t seg0:4; 310 uint64_t mbox0:2; 311 uint64_t lttr0:2; 312 uint64_t sid0:16; 313 } s; 314 struct cvmx_sriox_imsg_statusx_s cn63xx; 315 struct cvmx_sriox_imsg_statusx_s cn63xxp1; 316 struct cvmx_sriox_imsg_statusx_s cn66xx; 317 }; 318 319 union cvmx_sriox_imsg_vport_thr { 320 uint64_t u64; 321 struct cvmx_sriox_imsg_vport_thr_s { 322 uint64_t reserved_54_63:10; 323 uint64_t max_tot:6; 324 uint64_t reserved_46_47:2; 325 uint64_t max_s1:6; 326 uint64_t reserved_38_39:2; 327 uint64_t max_s0:6; 328 uint64_t sp_vport:1; 329 uint64_t reserved_20_30:11; 330 uint64_t buf_thr:4; 331 uint64_t reserved_14_15:2; 332 uint64_t max_p1:6; 333 uint64_t reserved_6_7:2; 334 uint64_t max_p0:6; 335 } s; 336 struct cvmx_sriox_imsg_vport_thr_s cn63xx; 337 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1; 338 struct cvmx_sriox_imsg_vport_thr_s cn66xx; 339 }; 340 341 union cvmx_sriox_imsg_vport_thr2 { 342 uint64_t u64; 343 struct cvmx_sriox_imsg_vport_thr2_s { 344 uint64_t reserved_46_63:18; 345 uint64_t max_s3:6; 346 uint64_t reserved_38_39:2; 347 uint64_t max_s2:6; 348 uint64_t reserved_0_31:32; 349 } s; 350 struct cvmx_sriox_imsg_vport_thr2_s cn66xx; 351 }; 352 353 union cvmx_sriox_int2_enable { 354 uint64_t u64; 355 struct cvmx_sriox_int2_enable_s { 356 uint64_t reserved_1_63:63; 357 uint64_t pko_rst:1; 358 } s; 359 struct cvmx_sriox_int2_enable_s cn63xx; 360 struct cvmx_sriox_int2_enable_s cn66xx; 361 }; 362 363 union cvmx_sriox_int2_reg { 364 uint64_t u64; 365 struct cvmx_sriox_int2_reg_s { 366 uint64_t reserved_32_63:32; 367 uint64_t int_sum:1; 368 uint64_t reserved_1_30:30; 369 uint64_t pko_rst:1; 370 } s; 371 struct cvmx_sriox_int2_reg_s cn63xx; 372 struct cvmx_sriox_int2_reg_s cn66xx; 373 }; 374 375 union cvmx_sriox_int_enable { 376 uint64_t u64; 377 struct cvmx_sriox_int_enable_s { 378 uint64_t reserved_27_63:37; 379 uint64_t zero_pkt:1; 380 uint64_t ttl_tout:1; 381 uint64_t fail:1; 382 uint64_t degrade:1; 383 uint64_t mac_buf:1; 384 uint64_t f_error:1; 385 uint64_t rtry_err:1; 386 uint64_t pko_err:1; 387 uint64_t omsg_err:1; 388 uint64_t omsg1:1; 389 uint64_t omsg0:1; 390 uint64_t link_up:1; 391 uint64_t link_dwn:1; 392 uint64_t phy_erb:1; 393 uint64_t log_erb:1; 394 uint64_t soft_rx:1; 395 uint64_t soft_tx:1; 396 uint64_t mce_rx:1; 397 uint64_t mce_tx:1; 398 uint64_t wr_done:1; 399 uint64_t sli_err:1; 400 uint64_t deny_wr:1; 401 uint64_t bar_err:1; 402 uint64_t maint_op:1; 403 uint64_t rxbell:1; 404 uint64_t bell_err:1; 405 uint64_t txbell:1; 406 } s; 407 struct cvmx_sriox_int_enable_s cn63xx; 408 struct cvmx_sriox_int_enable_cn63xxp1 { 409 uint64_t reserved_22_63:42; 410 uint64_t f_error:1; 411 uint64_t rtry_err:1; 412 uint64_t pko_err:1; 413 uint64_t omsg_err:1; 414 uint64_t omsg1:1; 415 uint64_t omsg0:1; 416 uint64_t link_up:1; 417 uint64_t link_dwn:1; 418 uint64_t phy_erb:1; 419 uint64_t log_erb:1; 420 uint64_t soft_rx:1; 421 uint64_t soft_tx:1; 422 uint64_t mce_rx:1; 423 uint64_t mce_tx:1; 424 uint64_t wr_done:1; 425 uint64_t sli_err:1; 426 uint64_t deny_wr:1; 427 uint64_t bar_err:1; 428 uint64_t maint_op:1; 429 uint64_t rxbell:1; 430 uint64_t bell_err:1; 431 uint64_t txbell:1; 432 } cn63xxp1; 433 struct cvmx_sriox_int_enable_s cn66xx; 434 }; 435 436 union cvmx_sriox_int_info0 { 437 uint64_t u64; 438 struct cvmx_sriox_int_info0_s { 439 uint64_t cmd:4; 440 uint64_t type:4; 441 uint64_t tag:8; 442 uint64_t reserved_42_47:6; 443 uint64_t length:10; 444 uint64_t status:3; 445 uint64_t reserved_16_28:13; 446 uint64_t be0:8; 447 uint64_t be1:8; 448 } s; 449 struct cvmx_sriox_int_info0_s cn63xx; 450 struct cvmx_sriox_int_info0_s cn63xxp1; 451 struct cvmx_sriox_int_info0_s cn66xx; 452 }; 453 454 union cvmx_sriox_int_info1 { 455 uint64_t u64; 456 struct cvmx_sriox_int_info1_s { 457 uint64_t info1:64; 458 } s; 459 struct cvmx_sriox_int_info1_s cn63xx; 460 struct cvmx_sriox_int_info1_s cn63xxp1; 461 struct cvmx_sriox_int_info1_s cn66xx; 462 }; 463 464 union cvmx_sriox_int_info2 { 465 uint64_t u64; 466 struct cvmx_sriox_int_info2_s { 467 uint64_t prio:2; 468 uint64_t tt:1; 469 uint64_t sis:1; 470 uint64_t ssize:4; 471 uint64_t did:16; 472 uint64_t xmbox:4; 473 uint64_t mbox:2; 474 uint64_t letter:2; 475 uint64_t rsrvd:30; 476 uint64_t lns:1; 477 uint64_t intr:1; 478 } s; 479 struct cvmx_sriox_int_info2_s cn63xx; 480 struct cvmx_sriox_int_info2_s cn63xxp1; 481 struct cvmx_sriox_int_info2_s cn66xx; 482 }; 483 484 union cvmx_sriox_int_info3 { 485 uint64_t u64; 486 struct cvmx_sriox_int_info3_s { 487 uint64_t prio:2; 488 uint64_t tt:2; 489 uint64_t type:4; 490 uint64_t other:48; 491 uint64_t reserved_0_7:8; 492 } s; 493 struct cvmx_sriox_int_info3_s cn63xx; 494 struct cvmx_sriox_int_info3_s cn63xxp1; 495 struct cvmx_sriox_int_info3_s cn66xx; 496 }; 497 498 union cvmx_sriox_int_reg { 499 uint64_t u64; 500 struct cvmx_sriox_int_reg_s { 501 uint64_t reserved_32_63:32; 502 uint64_t int2_sum:1; 503 uint64_t reserved_27_30:4; 504 uint64_t zero_pkt:1; 505 uint64_t ttl_tout:1; 506 uint64_t fail:1; 507 uint64_t degrad:1; 508 uint64_t mac_buf:1; 509 uint64_t f_error:1; 510 uint64_t rtry_err:1; 511 uint64_t pko_err:1; 512 uint64_t omsg_err:1; 513 uint64_t omsg1:1; 514 uint64_t omsg0:1; 515 uint64_t link_up:1; 516 uint64_t link_dwn:1; 517 uint64_t phy_erb:1; 518 uint64_t log_erb:1; 519 uint64_t soft_rx:1; 520 uint64_t soft_tx:1; 521 uint64_t mce_rx:1; 522 uint64_t mce_tx:1; 523 uint64_t wr_done:1; 524 uint64_t sli_err:1; 525 uint64_t deny_wr:1; 526 uint64_t bar_err:1; 527 uint64_t maint_op:1; 528 uint64_t rxbell:1; 529 uint64_t bell_err:1; 530 uint64_t txbell:1; 531 } s; 532 struct cvmx_sriox_int_reg_s cn63xx; 533 struct cvmx_sriox_int_reg_cn63xxp1 { 534 uint64_t reserved_22_63:42; 535 uint64_t f_error:1; 536 uint64_t rtry_err:1; 537 uint64_t pko_err:1; 538 uint64_t omsg_err:1; 539 uint64_t omsg1:1; 540 uint64_t omsg0:1; 541 uint64_t link_up:1; 542 uint64_t link_dwn:1; 543 uint64_t phy_erb:1; 544 uint64_t log_erb:1; 545 uint64_t soft_rx:1; 546 uint64_t soft_tx:1; 547 uint64_t mce_rx:1; 548 uint64_t mce_tx:1; 549 uint64_t wr_done:1; 550 uint64_t sli_err:1; 551 uint64_t deny_wr:1; 552 uint64_t bar_err:1; 553 uint64_t maint_op:1; 554 uint64_t rxbell:1; 555 uint64_t bell_err:1; 556 uint64_t txbell:1; 557 } cn63xxp1; 558 struct cvmx_sriox_int_reg_s cn66xx; 559 }; 560 561 union cvmx_sriox_ip_feature { 562 uint64_t u64; 563 struct cvmx_sriox_ip_feature_s { 564 uint64_t ops:32; 565 uint64_t reserved_15_31:17; 566 uint64_t no_vmin:1; 567 uint64_t a66:1; 568 uint64_t a50:1; 569 uint64_t reserved_11_11:1; 570 uint64_t tx_flow:1; 571 uint64_t pt_width:2; 572 uint64_t tx_pol:4; 573 uint64_t rx_pol:4; 574 } s; 575 struct cvmx_sriox_ip_feature_cn63xx { 576 uint64_t ops:32; 577 uint64_t reserved_14_31:18; 578 uint64_t a66:1; 579 uint64_t a50:1; 580 uint64_t reserved_11_11:1; 581 uint64_t tx_flow:1; 582 uint64_t pt_width:2; 583 uint64_t tx_pol:4; 584 uint64_t rx_pol:4; 585 } cn63xx; 586 struct cvmx_sriox_ip_feature_cn63xx cn63xxp1; 587 struct cvmx_sriox_ip_feature_s cn66xx; 588 }; 589 590 union cvmx_sriox_mac_buffers { 591 uint64_t u64; 592 struct cvmx_sriox_mac_buffers_s { 593 uint64_t reserved_56_63:8; 594 uint64_t tx_enb:8; 595 uint64_t reserved_44_47:4; 596 uint64_t tx_inuse:4; 597 uint64_t tx_stat:8; 598 uint64_t reserved_24_31:8; 599 uint64_t rx_enb:8; 600 uint64_t reserved_12_15:4; 601 uint64_t rx_inuse:4; 602 uint64_t rx_stat:8; 603 } s; 604 struct cvmx_sriox_mac_buffers_s cn63xx; 605 struct cvmx_sriox_mac_buffers_s cn66xx; 606 }; 607 608 union cvmx_sriox_maint_op { 609 uint64_t u64; 610 struct cvmx_sriox_maint_op_s { 611 uint64_t wr_data:32; 612 uint64_t reserved_27_31:5; 613 uint64_t fail:1; 614 uint64_t pending:1; 615 uint64_t op:1; 616 uint64_t addr:24; 617 } s; 618 struct cvmx_sriox_maint_op_s cn63xx; 619 struct cvmx_sriox_maint_op_s cn63xxp1; 620 struct cvmx_sriox_maint_op_s cn66xx; 621 }; 622 623 union cvmx_sriox_maint_rd_data { 624 uint64_t u64; 625 struct cvmx_sriox_maint_rd_data_s { 626 uint64_t reserved_33_63:31; 627 uint64_t valid:1; 628 uint64_t rd_data:32; 629 } s; 630 struct cvmx_sriox_maint_rd_data_s cn63xx; 631 struct cvmx_sriox_maint_rd_data_s cn63xxp1; 632 struct cvmx_sriox_maint_rd_data_s cn66xx; 633 }; 634 635 union cvmx_sriox_mce_tx_ctl { 636 uint64_t u64; 637 struct cvmx_sriox_mce_tx_ctl_s { 638 uint64_t reserved_1_63:63; 639 uint64_t mce:1; 640 } s; 641 struct cvmx_sriox_mce_tx_ctl_s cn63xx; 642 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1; 643 struct cvmx_sriox_mce_tx_ctl_s cn66xx; 644 }; 645 646 union cvmx_sriox_mem_op_ctrl { 647 uint64_t u64; 648 struct cvmx_sriox_mem_op_ctrl_s { 649 uint64_t reserved_10_63:54; 650 uint64_t rr_ro:1; 651 uint64_t w_ro:1; 652 uint64_t reserved_6_7:2; 653 uint64_t rp1_sid:1; 654 uint64_t rp0_sid:2; 655 uint64_t rp1_pid:1; 656 uint64_t rp0_pid:2; 657 } s; 658 struct cvmx_sriox_mem_op_ctrl_s cn63xx; 659 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1; 660 struct cvmx_sriox_mem_op_ctrl_s cn66xx; 661 }; 662 663 union cvmx_sriox_omsg_ctrlx { 664 uint64_t u64; 665 struct cvmx_sriox_omsg_ctrlx_s { 666 uint64_t testmode:1; 667 uint64_t reserved_37_62:26; 668 uint64_t silo_max:5; 669 uint64_t rtry_thr:16; 670 uint64_t rtry_en:1; 671 uint64_t reserved_11_14:4; 672 uint64_t idm_tt:1; 673 uint64_t idm_sis:1; 674 uint64_t idm_did:1; 675 uint64_t lttr_sp:4; 676 uint64_t lttr_mp:4; 677 } s; 678 struct cvmx_sriox_omsg_ctrlx_s cn63xx; 679 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 { 680 uint64_t testmode:1; 681 uint64_t reserved_32_62:31; 682 uint64_t rtry_thr:16; 683 uint64_t rtry_en:1; 684 uint64_t reserved_11_14:4; 685 uint64_t idm_tt:1; 686 uint64_t idm_sis:1; 687 uint64_t idm_did:1; 688 uint64_t lttr_sp:4; 689 uint64_t lttr_mp:4; 690 } cn63xxp1; 691 struct cvmx_sriox_omsg_ctrlx_s cn66xx; 692 }; 693 694 union cvmx_sriox_omsg_done_countsx { 695 uint64_t u64; 696 struct cvmx_sriox_omsg_done_countsx_s { 697 uint64_t reserved_32_63:32; 698 uint64_t bad:16; 699 uint64_t good:16; 700 } s; 701 struct cvmx_sriox_omsg_done_countsx_s cn63xx; 702 struct cvmx_sriox_omsg_done_countsx_s cn66xx; 703 }; 704 705 union cvmx_sriox_omsg_fmp_mrx { 706 uint64_t u64; 707 struct cvmx_sriox_omsg_fmp_mrx_s { 708 uint64_t reserved_15_63:49; 709 uint64_t ctlr_sp:1; 710 uint64_t ctlr_fmp:1; 711 uint64_t ctlr_nmp:1; 712 uint64_t id_sp:1; 713 uint64_t id_fmp:1; 714 uint64_t id_nmp:1; 715 uint64_t id_psd:1; 716 uint64_t mbox_sp:1; 717 uint64_t mbox_fmp:1; 718 uint64_t mbox_nmp:1; 719 uint64_t mbox_psd:1; 720 uint64_t all_sp:1; 721 uint64_t all_fmp:1; 722 uint64_t all_nmp:1; 723 uint64_t all_psd:1; 724 } s; 725 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx; 726 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1; 727 struct cvmx_sriox_omsg_fmp_mrx_s cn66xx; 728 }; 729 730 union cvmx_sriox_omsg_nmp_mrx { 731 uint64_t u64; 732 struct cvmx_sriox_omsg_nmp_mrx_s { 733 uint64_t reserved_15_63:49; 734 uint64_t ctlr_sp:1; 735 uint64_t ctlr_fmp:1; 736 uint64_t ctlr_nmp:1; 737 uint64_t id_sp:1; 738 uint64_t id_fmp:1; 739 uint64_t id_nmp:1; 740 uint64_t reserved_8_8:1; 741 uint64_t mbox_sp:1; 742 uint64_t mbox_fmp:1; 743 uint64_t mbox_nmp:1; 744 uint64_t reserved_4_4:1; 745 uint64_t all_sp:1; 746 uint64_t all_fmp:1; 747 uint64_t all_nmp:1; 748 uint64_t reserved_0_0:1; 749 } s; 750 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx; 751 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1; 752 struct cvmx_sriox_omsg_nmp_mrx_s cn66xx; 753 }; 754 755 union cvmx_sriox_omsg_portx { 756 uint64_t u64; 757 struct cvmx_sriox_omsg_portx_s { 758 uint64_t reserved_32_63:32; 759 uint64_t enable:1; 760 uint64_t reserved_3_30:28; 761 uint64_t port:3; 762 } s; 763 struct cvmx_sriox_omsg_portx_cn63xx { 764 uint64_t reserved_32_63:32; 765 uint64_t enable:1; 766 uint64_t reserved_2_30:29; 767 uint64_t port:2; 768 } cn63xx; 769 struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1; 770 struct cvmx_sriox_omsg_portx_s cn66xx; 771 }; 772 773 union cvmx_sriox_omsg_silo_thr { 774 uint64_t u64; 775 struct cvmx_sriox_omsg_silo_thr_s { 776 uint64_t reserved_5_63:59; 777 uint64_t tot_silo:5; 778 } s; 779 struct cvmx_sriox_omsg_silo_thr_s cn63xx; 780 struct cvmx_sriox_omsg_silo_thr_s cn66xx; 781 }; 782 783 union cvmx_sriox_omsg_sp_mrx { 784 uint64_t u64; 785 struct cvmx_sriox_omsg_sp_mrx_s { 786 uint64_t reserved_16_63:48; 787 uint64_t xmbox_sp:1; 788 uint64_t ctlr_sp:1; 789 uint64_t ctlr_fmp:1; 790 uint64_t ctlr_nmp:1; 791 uint64_t id_sp:1; 792 uint64_t id_fmp:1; 793 uint64_t id_nmp:1; 794 uint64_t id_psd:1; 795 uint64_t mbox_sp:1; 796 uint64_t mbox_fmp:1; 797 uint64_t mbox_nmp:1; 798 uint64_t mbox_psd:1; 799 uint64_t all_sp:1; 800 uint64_t all_fmp:1; 801 uint64_t all_nmp:1; 802 uint64_t all_psd:1; 803 } s; 804 struct cvmx_sriox_omsg_sp_mrx_s cn63xx; 805 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1; 806 struct cvmx_sriox_omsg_sp_mrx_s cn66xx; 807 }; 808 809 union cvmx_sriox_priox_in_use { 810 uint64_t u64; 811 struct cvmx_sriox_priox_in_use_s { 812 uint64_t reserved_32_63:32; 813 uint64_t end_cnt:16; 814 uint64_t start_cnt:16; 815 } s; 816 struct cvmx_sriox_priox_in_use_s cn63xx; 817 struct cvmx_sriox_priox_in_use_s cn66xx; 818 }; 819 820 union cvmx_sriox_rx_bell { 821 uint64_t u64; 822 struct cvmx_sriox_rx_bell_s { 823 uint64_t reserved_48_63:16; 824 uint64_t data:16; 825 uint64_t src_id:16; 826 uint64_t count:8; 827 uint64_t reserved_5_7:3; 828 uint64_t dest_id:1; 829 uint64_t id16:1; 830 uint64_t reserved_2_2:1; 831 uint64_t priority:2; 832 } s; 833 struct cvmx_sriox_rx_bell_s cn63xx; 834 struct cvmx_sriox_rx_bell_s cn63xxp1; 835 struct cvmx_sriox_rx_bell_s cn66xx; 836 }; 837 838 union cvmx_sriox_rx_bell_seq { 839 uint64_t u64; 840 struct cvmx_sriox_rx_bell_seq_s { 841 uint64_t reserved_40_63:24; 842 uint64_t count:8; 843 uint64_t seq:32; 844 } s; 845 struct cvmx_sriox_rx_bell_seq_s cn63xx; 846 struct cvmx_sriox_rx_bell_seq_s cn63xxp1; 847 struct cvmx_sriox_rx_bell_seq_s cn66xx; 848 }; 849 850 union cvmx_sriox_rx_status { 851 uint64_t u64; 852 struct cvmx_sriox_rx_status_s { 853 uint64_t rtn_pr3:8; 854 uint64_t rtn_pr2:8; 855 uint64_t rtn_pr1:8; 856 uint64_t reserved_28_39:12; 857 uint64_t mbox:4; 858 uint64_t comp:8; 859 uint64_t reserved_13_15:3; 860 uint64_t n_post:5; 861 uint64_t post:8; 862 } s; 863 struct cvmx_sriox_rx_status_s cn63xx; 864 struct cvmx_sriox_rx_status_s cn63xxp1; 865 struct cvmx_sriox_rx_status_s cn66xx; 866 }; 867 868 union cvmx_sriox_s2m_typex { 869 uint64_t u64; 870 struct cvmx_sriox_s2m_typex_s { 871 uint64_t reserved_19_63:45; 872 uint64_t wr_op:3; 873 uint64_t reserved_15_15:1; 874 uint64_t rd_op:3; 875 uint64_t wr_prior:2; 876 uint64_t rd_prior:2; 877 uint64_t reserved_6_7:2; 878 uint64_t src_id:1; 879 uint64_t id16:1; 880 uint64_t reserved_2_3:2; 881 uint64_t iaow_sel:2; 882 } s; 883 struct cvmx_sriox_s2m_typex_s cn63xx; 884 struct cvmx_sriox_s2m_typex_s cn63xxp1; 885 struct cvmx_sriox_s2m_typex_s cn66xx; 886 }; 887 888 union cvmx_sriox_seq { 889 uint64_t u64; 890 struct cvmx_sriox_seq_s { 891 uint64_t reserved_32_63:32; 892 uint64_t seq:32; 893 } s; 894 struct cvmx_sriox_seq_s cn63xx; 895 struct cvmx_sriox_seq_s cn63xxp1; 896 struct cvmx_sriox_seq_s cn66xx; 897 }; 898 899 union cvmx_sriox_status_reg { 900 uint64_t u64; 901 struct cvmx_sriox_status_reg_s { 902 uint64_t reserved_2_63:62; 903 uint64_t access:1; 904 uint64_t srio:1; 905 } s; 906 struct cvmx_sriox_status_reg_s cn63xx; 907 struct cvmx_sriox_status_reg_s cn63xxp1; 908 struct cvmx_sriox_status_reg_s cn66xx; 909 }; 910 911 union cvmx_sriox_tag_ctrl { 912 uint64_t u64; 913 struct cvmx_sriox_tag_ctrl_s { 914 uint64_t reserved_17_63:47; 915 uint64_t o_clr:1; 916 uint64_t reserved_13_15:3; 917 uint64_t otag:5; 918 uint64_t reserved_5_7:3; 919 uint64_t itag:5; 920 } s; 921 struct cvmx_sriox_tag_ctrl_s cn63xx; 922 struct cvmx_sriox_tag_ctrl_s cn63xxp1; 923 struct cvmx_sriox_tag_ctrl_s cn66xx; 924 }; 925 926 union cvmx_sriox_tlp_credits { 927 uint64_t u64; 928 struct cvmx_sriox_tlp_credits_s { 929 uint64_t reserved_28_63:36; 930 uint64_t mbox:4; 931 uint64_t comp:8; 932 uint64_t reserved_13_15:3; 933 uint64_t n_post:5; 934 uint64_t post:8; 935 } s; 936 struct cvmx_sriox_tlp_credits_s cn63xx; 937 struct cvmx_sriox_tlp_credits_s cn63xxp1; 938 struct cvmx_sriox_tlp_credits_s cn66xx; 939 }; 940 941 union cvmx_sriox_tx_bell { 942 uint64_t u64; 943 struct cvmx_sriox_tx_bell_s { 944 uint64_t reserved_48_63:16; 945 uint64_t data:16; 946 uint64_t dest_id:16; 947 uint64_t reserved_9_15:7; 948 uint64_t pending:1; 949 uint64_t reserved_5_7:3; 950 uint64_t src_id:1; 951 uint64_t id16:1; 952 uint64_t reserved_2_2:1; 953 uint64_t priority:2; 954 } s; 955 struct cvmx_sriox_tx_bell_s cn63xx; 956 struct cvmx_sriox_tx_bell_s cn63xxp1; 957 struct cvmx_sriox_tx_bell_s cn66xx; 958 }; 959 960 union cvmx_sriox_tx_bell_info { 961 uint64_t u64; 962 struct cvmx_sriox_tx_bell_info_s { 963 uint64_t reserved_48_63:16; 964 uint64_t data:16; 965 uint64_t dest_id:16; 966 uint64_t reserved_8_15:8; 967 uint64_t timeout:1; 968 uint64_t error:1; 969 uint64_t retry:1; 970 uint64_t src_id:1; 971 uint64_t id16:1; 972 uint64_t reserved_2_2:1; 973 uint64_t priority:2; 974 } s; 975 struct cvmx_sriox_tx_bell_info_s cn63xx; 976 struct cvmx_sriox_tx_bell_info_s cn63xxp1; 977 struct cvmx_sriox_tx_bell_info_s cn66xx; 978 }; 979 980 union cvmx_sriox_tx_ctrl { 981 uint64_t u64; 982 struct cvmx_sriox_tx_ctrl_s { 983 uint64_t reserved_53_63:11; 984 uint64_t tag_th2:5; 985 uint64_t reserved_45_47:3; 986 uint64_t tag_th1:5; 987 uint64_t reserved_37_39:3; 988 uint64_t tag_th0:5; 989 uint64_t reserved_20_31:12; 990 uint64_t tx_th2:4; 991 uint64_t reserved_12_15:4; 992 uint64_t tx_th1:4; 993 uint64_t reserved_4_7:4; 994 uint64_t tx_th0:4; 995 } s; 996 struct cvmx_sriox_tx_ctrl_s cn63xx; 997 struct cvmx_sriox_tx_ctrl_s cn63xxp1; 998 struct cvmx_sriox_tx_ctrl_s cn66xx; 999 }; 1000 1001 union cvmx_sriox_tx_emphasis { 1002 uint64_t u64; 1003 struct cvmx_sriox_tx_emphasis_s { 1004 uint64_t reserved_4_63:60; 1005 uint64_t emph:4; 1006 } s; 1007 struct cvmx_sriox_tx_emphasis_s cn63xx; 1008 struct cvmx_sriox_tx_emphasis_s cn66xx; 1009 }; 1010 1011 union cvmx_sriox_tx_status { 1012 uint64_t u64; 1013 struct cvmx_sriox_tx_status_s { 1014 uint64_t reserved_32_63:32; 1015 uint64_t s2m_pr3:8; 1016 uint64_t s2m_pr2:8; 1017 uint64_t s2m_pr1:8; 1018 uint64_t s2m_pr0:8; 1019 } s; 1020 struct cvmx_sriox_tx_status_s cn63xx; 1021 struct cvmx_sriox_tx_status_s cn63xxp1; 1022 struct cvmx_sriox_tx_status_s cn66xx; 1023 }; 1024 1025 union cvmx_sriox_wr_done_counts { 1026 uint64_t u64; 1027 struct cvmx_sriox_wr_done_counts_s { 1028 uint64_t reserved_32_63:32; 1029 uint64_t bad:16; 1030 uint64_t good:16; 1031 } s; 1032 struct cvmx_sriox_wr_done_counts_s cn63xx; 1033 struct cvmx_sriox_wr_done_counts_s cn66xx; 1034 }; 1035 1036 #endif 1037