1ac6d9b3aSChandrakala Chavva /***********************license start*************** 2ac6d9b3aSChandrakala Chavva * Author: Cavium Inc. 3ac6d9b3aSChandrakala Chavva * 4ac6d9b3aSChandrakala Chavva * Contact: support@cavium.com 5ac6d9b3aSChandrakala Chavva * This file is part of the OCTEON SDK 6ac6d9b3aSChandrakala Chavva * 7ac6d9b3aSChandrakala Chavva * Copyright (c) 2003-2014 Cavium Inc. 8ac6d9b3aSChandrakala Chavva * 9ac6d9b3aSChandrakala Chavva * This file is free software; you can redistribute it and/or modify 10ac6d9b3aSChandrakala Chavva * it under the terms of the GNU General Public License, Version 2, as 11ac6d9b3aSChandrakala Chavva * published by the Free Software Foundation. 12ac6d9b3aSChandrakala Chavva * 13ac6d9b3aSChandrakala Chavva * This file is distributed in the hope that it will be useful, but 14ac6d9b3aSChandrakala Chavva * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15ac6d9b3aSChandrakala Chavva * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16ac6d9b3aSChandrakala Chavva * NONINFRINGEMENT. See the GNU General Public License for more 17ac6d9b3aSChandrakala Chavva * details. 18ac6d9b3aSChandrakala Chavva * 19ac6d9b3aSChandrakala Chavva * You should have received a copy of the GNU General Public License 20ac6d9b3aSChandrakala Chavva * along with this file; if not, write to the Free Software 21ac6d9b3aSChandrakala Chavva * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22ac6d9b3aSChandrakala Chavva * or visit http://www.gnu.org/licenses/. 23ac6d9b3aSChandrakala Chavva * 24ac6d9b3aSChandrakala Chavva * This file may also be available under a different license from Cavium. 25ac6d9b3aSChandrakala Chavva * Contact Cavium Inc. for more information 26ac6d9b3aSChandrakala Chavva ***********************license end**************************************/ 27ac6d9b3aSChandrakala Chavva 28ac6d9b3aSChandrakala Chavva #ifndef __CVMX_RST_DEFS_H__ 29ac6d9b3aSChandrakala Chavva #define __CVMX_RST_DEFS_H__ 30ac6d9b3aSChandrakala Chavva 31ac6d9b3aSChandrakala Chavva #define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull)) 32ac6d9b3aSChandrakala Chavva #define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull)) 33ac6d9b3aSChandrakala Chavva #define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull)) 34ac6d9b3aSChandrakala Chavva #define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8) 35ac6d9b3aSChandrakala Chavva #define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull)) 36ac6d9b3aSChandrakala Chavva #define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull)) 37ac6d9b3aSChandrakala Chavva #define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull)) 38ac6d9b3aSChandrakala Chavva #define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull)) 39ac6d9b3aSChandrakala Chavva #define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull)) 40ac6d9b3aSChandrakala Chavva #define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull)) 41ac6d9b3aSChandrakala Chavva #define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8) 42ac6d9b3aSChandrakala Chavva #define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull)) 43ac6d9b3aSChandrakala Chavva 44ac6d9b3aSChandrakala Chavva union cvmx_rst_boot { 45ac6d9b3aSChandrakala Chavva uint64_t u64; 46ac6d9b3aSChandrakala Chavva struct cvmx_rst_boot_s { 47ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 48ac6d9b3aSChandrakala Chavva uint64_t chipkill:1; 49ac6d9b3aSChandrakala Chavva uint64_t jtcsrdis:1; 50ac6d9b3aSChandrakala Chavva uint64_t ejtagdis:1; 51ac6d9b3aSChandrakala Chavva uint64_t romen:1; 52ac6d9b3aSChandrakala Chavva uint64_t ckill_ppdis:1; 53ac6d9b3aSChandrakala Chavva uint64_t jt_tstmode:1; 54ac6d9b3aSChandrakala Chavva uint64_t vrm_err:1; 55ac6d9b3aSChandrakala Chavva uint64_t reserved_37_56:20; 56ac6d9b3aSChandrakala Chavva uint64_t c_mul:7; 57ac6d9b3aSChandrakala Chavva uint64_t pnr_mul:6; 58ac6d9b3aSChandrakala Chavva uint64_t reserved_21_23:3; 59ac6d9b3aSChandrakala Chavva uint64_t lboot_oci:3; 60ac6d9b3aSChandrakala Chavva uint64_t lboot_ext:6; 61ac6d9b3aSChandrakala Chavva uint64_t lboot:10; 62ac6d9b3aSChandrakala Chavva uint64_t rboot:1; 63ac6d9b3aSChandrakala Chavva uint64_t rboot_pin:1; 64ac6d9b3aSChandrakala Chavva #else 65ac6d9b3aSChandrakala Chavva uint64_t rboot_pin:1; 66ac6d9b3aSChandrakala Chavva uint64_t rboot:1; 67ac6d9b3aSChandrakala Chavva uint64_t lboot:10; 68ac6d9b3aSChandrakala Chavva uint64_t lboot_ext:6; 69ac6d9b3aSChandrakala Chavva uint64_t lboot_oci:3; 70ac6d9b3aSChandrakala Chavva uint64_t reserved_21_23:3; 71ac6d9b3aSChandrakala Chavva uint64_t pnr_mul:6; 72ac6d9b3aSChandrakala Chavva uint64_t c_mul:7; 73ac6d9b3aSChandrakala Chavva uint64_t reserved_37_56:20; 74ac6d9b3aSChandrakala Chavva uint64_t vrm_err:1; 75ac6d9b3aSChandrakala Chavva uint64_t jt_tstmode:1; 76ac6d9b3aSChandrakala Chavva uint64_t ckill_ppdis:1; 77ac6d9b3aSChandrakala Chavva uint64_t romen:1; 78ac6d9b3aSChandrakala Chavva uint64_t ejtagdis:1; 79ac6d9b3aSChandrakala Chavva uint64_t jtcsrdis:1; 80ac6d9b3aSChandrakala Chavva uint64_t chipkill:1; 81ac6d9b3aSChandrakala Chavva #endif 82ac6d9b3aSChandrakala Chavva } s; 83ac6d9b3aSChandrakala Chavva struct cvmx_rst_boot_s cn70xx; 84ac6d9b3aSChandrakala Chavva struct cvmx_rst_boot_s cn70xxp1; 85ac6d9b3aSChandrakala Chavva struct cvmx_rst_boot_s cn78xx; 86ac6d9b3aSChandrakala Chavva }; 87ac6d9b3aSChandrakala Chavva 88ac6d9b3aSChandrakala Chavva union cvmx_rst_cfg { 89ac6d9b3aSChandrakala Chavva uint64_t u64; 90ac6d9b3aSChandrakala Chavva struct cvmx_rst_cfg_s { 91ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 92ac6d9b3aSChandrakala Chavva uint64_t bist_delay:58; 93ac6d9b3aSChandrakala Chavva uint64_t reserved_3_5:3; 94ac6d9b3aSChandrakala Chavva uint64_t cntl_clr_bist:1; 95ac6d9b3aSChandrakala Chavva uint64_t warm_clr_bist:1; 96ac6d9b3aSChandrakala Chavva uint64_t soft_clr_bist:1; 97ac6d9b3aSChandrakala Chavva #else 98ac6d9b3aSChandrakala Chavva uint64_t soft_clr_bist:1; 99ac6d9b3aSChandrakala Chavva uint64_t warm_clr_bist:1; 100ac6d9b3aSChandrakala Chavva uint64_t cntl_clr_bist:1; 101ac6d9b3aSChandrakala Chavva uint64_t reserved_3_5:3; 102ac6d9b3aSChandrakala Chavva uint64_t bist_delay:58; 103ac6d9b3aSChandrakala Chavva #endif 104ac6d9b3aSChandrakala Chavva } s; 105ac6d9b3aSChandrakala Chavva struct cvmx_rst_cfg_s cn70xx; 106ac6d9b3aSChandrakala Chavva struct cvmx_rst_cfg_s cn70xxp1; 107ac6d9b3aSChandrakala Chavva struct cvmx_rst_cfg_s cn78xx; 108ac6d9b3aSChandrakala Chavva }; 109ac6d9b3aSChandrakala Chavva 110ac6d9b3aSChandrakala Chavva union cvmx_rst_ckill { 111ac6d9b3aSChandrakala Chavva uint64_t u64; 112ac6d9b3aSChandrakala Chavva struct cvmx_rst_ckill_s { 113ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 114ac6d9b3aSChandrakala Chavva uint64_t reserved_47_63:17; 115ac6d9b3aSChandrakala Chavva uint64_t timer:47; 116ac6d9b3aSChandrakala Chavva #else 117ac6d9b3aSChandrakala Chavva uint64_t timer:47; 118ac6d9b3aSChandrakala Chavva uint64_t reserved_47_63:17; 119ac6d9b3aSChandrakala Chavva #endif 120ac6d9b3aSChandrakala Chavva } s; 121ac6d9b3aSChandrakala Chavva struct cvmx_rst_ckill_s cn70xx; 122ac6d9b3aSChandrakala Chavva struct cvmx_rst_ckill_s cn70xxp1; 123ac6d9b3aSChandrakala Chavva struct cvmx_rst_ckill_s cn78xx; 124ac6d9b3aSChandrakala Chavva }; 125ac6d9b3aSChandrakala Chavva 126ac6d9b3aSChandrakala Chavva union cvmx_rst_ctlx { 127ac6d9b3aSChandrakala Chavva uint64_t u64; 128ac6d9b3aSChandrakala Chavva struct cvmx_rst_ctlx_s { 129ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 130ac6d9b3aSChandrakala Chavva uint64_t reserved_10_63:54; 131ac6d9b3aSChandrakala Chavva uint64_t prst_link:1; 132ac6d9b3aSChandrakala Chavva uint64_t rst_done:1; 133ac6d9b3aSChandrakala Chavva uint64_t rst_link:1; 134ac6d9b3aSChandrakala Chavva uint64_t host_mode:1; 135ac6d9b3aSChandrakala Chavva uint64_t reserved_4_5:2; 136ac6d9b3aSChandrakala Chavva uint64_t rst_drv:1; 137ac6d9b3aSChandrakala Chavva uint64_t rst_rcv:1; 138ac6d9b3aSChandrakala Chavva uint64_t rst_chip:1; 139ac6d9b3aSChandrakala Chavva uint64_t rst_val:1; 140ac6d9b3aSChandrakala Chavva #else 141ac6d9b3aSChandrakala Chavva uint64_t rst_val:1; 142ac6d9b3aSChandrakala Chavva uint64_t rst_chip:1; 143ac6d9b3aSChandrakala Chavva uint64_t rst_rcv:1; 144ac6d9b3aSChandrakala Chavva uint64_t rst_drv:1; 145ac6d9b3aSChandrakala Chavva uint64_t reserved_4_5:2; 146ac6d9b3aSChandrakala Chavva uint64_t host_mode:1; 147ac6d9b3aSChandrakala Chavva uint64_t rst_link:1; 148ac6d9b3aSChandrakala Chavva uint64_t rst_done:1; 149ac6d9b3aSChandrakala Chavva uint64_t prst_link:1; 150ac6d9b3aSChandrakala Chavva uint64_t reserved_10_63:54; 151ac6d9b3aSChandrakala Chavva #endif 152ac6d9b3aSChandrakala Chavva } s; 153ac6d9b3aSChandrakala Chavva struct cvmx_rst_ctlx_s cn70xx; 154ac6d9b3aSChandrakala Chavva struct cvmx_rst_ctlx_s cn70xxp1; 155ac6d9b3aSChandrakala Chavva struct cvmx_rst_ctlx_s cn78xx; 156ac6d9b3aSChandrakala Chavva }; 157ac6d9b3aSChandrakala Chavva 158ac6d9b3aSChandrakala Chavva union cvmx_rst_delay { 159ac6d9b3aSChandrakala Chavva uint64_t u64; 160ac6d9b3aSChandrakala Chavva struct cvmx_rst_delay_s { 161ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 162ac6d9b3aSChandrakala Chavva uint64_t reserved_32_63:32; 163ac6d9b3aSChandrakala Chavva uint64_t warm_rst_dly:16; 164ac6d9b3aSChandrakala Chavva uint64_t soft_rst_dly:16; 165ac6d9b3aSChandrakala Chavva #else 166ac6d9b3aSChandrakala Chavva uint64_t soft_rst_dly:16; 167ac6d9b3aSChandrakala Chavva uint64_t warm_rst_dly:16; 168ac6d9b3aSChandrakala Chavva uint64_t reserved_32_63:32; 169ac6d9b3aSChandrakala Chavva #endif 170ac6d9b3aSChandrakala Chavva } s; 171ac6d9b3aSChandrakala Chavva struct cvmx_rst_delay_s cn70xx; 172ac6d9b3aSChandrakala Chavva struct cvmx_rst_delay_s cn70xxp1; 173ac6d9b3aSChandrakala Chavva struct cvmx_rst_delay_s cn78xx; 174ac6d9b3aSChandrakala Chavva }; 175ac6d9b3aSChandrakala Chavva 176ac6d9b3aSChandrakala Chavva union cvmx_rst_eco { 177ac6d9b3aSChandrakala Chavva uint64_t u64; 178ac6d9b3aSChandrakala Chavva struct cvmx_rst_eco_s { 179ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 180ac6d9b3aSChandrakala Chavva uint64_t reserved_32_63:32; 181ac6d9b3aSChandrakala Chavva uint64_t eco_rw:32; 182ac6d9b3aSChandrakala Chavva #else 183ac6d9b3aSChandrakala Chavva uint64_t eco_rw:32; 184ac6d9b3aSChandrakala Chavva uint64_t reserved_32_63:32; 185ac6d9b3aSChandrakala Chavva #endif 186ac6d9b3aSChandrakala Chavva } s; 187ac6d9b3aSChandrakala Chavva struct cvmx_rst_eco_s cn78xx; 188ac6d9b3aSChandrakala Chavva }; 189ac6d9b3aSChandrakala Chavva 190ac6d9b3aSChandrakala Chavva union cvmx_rst_int { 191ac6d9b3aSChandrakala Chavva uint64_t u64; 192ac6d9b3aSChandrakala Chavva struct cvmx_rst_int_s { 193ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 194ac6d9b3aSChandrakala Chavva uint64_t reserved_12_63:52; 195ac6d9b3aSChandrakala Chavva uint64_t perst:4; 196ac6d9b3aSChandrakala Chavva uint64_t reserved_4_7:4; 197ac6d9b3aSChandrakala Chavva uint64_t rst_link:4; 198ac6d9b3aSChandrakala Chavva #else 199ac6d9b3aSChandrakala Chavva uint64_t rst_link:4; 200ac6d9b3aSChandrakala Chavva uint64_t reserved_4_7:4; 201ac6d9b3aSChandrakala Chavva uint64_t perst:4; 202ac6d9b3aSChandrakala Chavva uint64_t reserved_12_63:52; 203ac6d9b3aSChandrakala Chavva #endif 204ac6d9b3aSChandrakala Chavva } s; 205ac6d9b3aSChandrakala Chavva struct cvmx_rst_int_cn70xx { 206ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 207ac6d9b3aSChandrakala Chavva uint64_t reserved_11_63:53; 208ac6d9b3aSChandrakala Chavva uint64_t perst:3; 209ac6d9b3aSChandrakala Chavva uint64_t reserved_3_7:5; 210ac6d9b3aSChandrakala Chavva uint64_t rst_link:3; 211ac6d9b3aSChandrakala Chavva #else 212ac6d9b3aSChandrakala Chavva uint64_t rst_link:3; 213ac6d9b3aSChandrakala Chavva uint64_t reserved_3_7:5; 214ac6d9b3aSChandrakala Chavva uint64_t perst:3; 215ac6d9b3aSChandrakala Chavva uint64_t reserved_11_63:53; 216ac6d9b3aSChandrakala Chavva #endif 217ac6d9b3aSChandrakala Chavva } cn70xx; 218ac6d9b3aSChandrakala Chavva struct cvmx_rst_int_cn70xx cn70xxp1; 219ac6d9b3aSChandrakala Chavva struct cvmx_rst_int_s cn78xx; 220ac6d9b3aSChandrakala Chavva }; 221ac6d9b3aSChandrakala Chavva 222ac6d9b3aSChandrakala Chavva union cvmx_rst_ocx { 223ac6d9b3aSChandrakala Chavva uint64_t u64; 224ac6d9b3aSChandrakala Chavva struct cvmx_rst_ocx_s { 225ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 226ac6d9b3aSChandrakala Chavva uint64_t reserved_3_63:61; 227ac6d9b3aSChandrakala Chavva uint64_t rst_link:3; 228ac6d9b3aSChandrakala Chavva #else 229ac6d9b3aSChandrakala Chavva uint64_t rst_link:3; 230ac6d9b3aSChandrakala Chavva uint64_t reserved_3_63:61; 231ac6d9b3aSChandrakala Chavva #endif 232ac6d9b3aSChandrakala Chavva } s; 233ac6d9b3aSChandrakala Chavva struct cvmx_rst_ocx_s cn78xx; 234ac6d9b3aSChandrakala Chavva }; 235ac6d9b3aSChandrakala Chavva 236ac6d9b3aSChandrakala Chavva union cvmx_rst_power_dbg { 237ac6d9b3aSChandrakala Chavva uint64_t u64; 238ac6d9b3aSChandrakala Chavva struct cvmx_rst_power_dbg_s { 239ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 240ac6d9b3aSChandrakala Chavva uint64_t reserved_3_63:61; 241ac6d9b3aSChandrakala Chavva uint64_t str:3; 242ac6d9b3aSChandrakala Chavva #else 243ac6d9b3aSChandrakala Chavva uint64_t str:3; 244ac6d9b3aSChandrakala Chavva uint64_t reserved_3_63:61; 245ac6d9b3aSChandrakala Chavva #endif 246ac6d9b3aSChandrakala Chavva } s; 247ac6d9b3aSChandrakala Chavva struct cvmx_rst_power_dbg_s cn78xx; 248ac6d9b3aSChandrakala Chavva }; 249ac6d9b3aSChandrakala Chavva 250ac6d9b3aSChandrakala Chavva union cvmx_rst_pp_power { 251ac6d9b3aSChandrakala Chavva uint64_t u64; 252ac6d9b3aSChandrakala Chavva struct cvmx_rst_pp_power_s { 253ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 254ac6d9b3aSChandrakala Chavva uint64_t reserved_48_63:16; 255ac6d9b3aSChandrakala Chavva uint64_t gate:48; 256ac6d9b3aSChandrakala Chavva #else 257ac6d9b3aSChandrakala Chavva uint64_t gate:48; 258ac6d9b3aSChandrakala Chavva uint64_t reserved_48_63:16; 259ac6d9b3aSChandrakala Chavva #endif 260ac6d9b3aSChandrakala Chavva } s; 261ac6d9b3aSChandrakala Chavva struct cvmx_rst_pp_power_cn70xx { 262ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 263ac6d9b3aSChandrakala Chavva uint64_t reserved_4_63:60; 264ac6d9b3aSChandrakala Chavva uint64_t gate:4; 265ac6d9b3aSChandrakala Chavva #else 266ac6d9b3aSChandrakala Chavva uint64_t gate:4; 267ac6d9b3aSChandrakala Chavva uint64_t reserved_4_63:60; 268ac6d9b3aSChandrakala Chavva #endif 269ac6d9b3aSChandrakala Chavva } cn70xx; 270ac6d9b3aSChandrakala Chavva struct cvmx_rst_pp_power_cn70xx cn70xxp1; 271ac6d9b3aSChandrakala Chavva struct cvmx_rst_pp_power_s cn78xx; 272ac6d9b3aSChandrakala Chavva }; 273ac6d9b3aSChandrakala Chavva 274ac6d9b3aSChandrakala Chavva union cvmx_rst_soft_prstx { 275ac6d9b3aSChandrakala Chavva uint64_t u64; 276ac6d9b3aSChandrakala Chavva struct cvmx_rst_soft_prstx_s { 277ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 278ac6d9b3aSChandrakala Chavva uint64_t reserved_1_63:63; 279ac6d9b3aSChandrakala Chavva uint64_t soft_prst:1; 280ac6d9b3aSChandrakala Chavva #else 281ac6d9b3aSChandrakala Chavva uint64_t soft_prst:1; 282ac6d9b3aSChandrakala Chavva uint64_t reserved_1_63:63; 283ac6d9b3aSChandrakala Chavva #endif 284ac6d9b3aSChandrakala Chavva } s; 285ac6d9b3aSChandrakala Chavva struct cvmx_rst_soft_prstx_s cn70xx; 286ac6d9b3aSChandrakala Chavva struct cvmx_rst_soft_prstx_s cn70xxp1; 287ac6d9b3aSChandrakala Chavva struct cvmx_rst_soft_prstx_s cn78xx; 288ac6d9b3aSChandrakala Chavva }; 289ac6d9b3aSChandrakala Chavva 290ac6d9b3aSChandrakala Chavva union cvmx_rst_soft_rst { 291ac6d9b3aSChandrakala Chavva uint64_t u64; 292ac6d9b3aSChandrakala Chavva struct cvmx_rst_soft_rst_s { 293ac6d9b3aSChandrakala Chavva #ifdef __BIG_ENDIAN_BITFIELD 294ac6d9b3aSChandrakala Chavva uint64_t reserved_1_63:63; 295ac6d9b3aSChandrakala Chavva uint64_t soft_rst:1; 296ac6d9b3aSChandrakala Chavva #else 297ac6d9b3aSChandrakala Chavva uint64_t soft_rst:1; 298ac6d9b3aSChandrakala Chavva uint64_t reserved_1_63:63; 299ac6d9b3aSChandrakala Chavva #endif 300ac6d9b3aSChandrakala Chavva } s; 301ac6d9b3aSChandrakala Chavva struct cvmx_rst_soft_rst_s cn70xx; 302ac6d9b3aSChandrakala Chavva struct cvmx_rst_soft_rst_s cn70xxp1; 303ac6d9b3aSChandrakala Chavva struct cvmx_rst_soft_rst_s cn78xx; 304ac6d9b3aSChandrakala Chavva }; 305ac6d9b3aSChandrakala Chavva 306ac6d9b3aSChandrakala Chavva #endif 307