1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2012 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_POW_DEFS_H__
29 #define __CVMX_POW_DEFS_H__
30 
31 #define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
32 #define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
33 #define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
34 #define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
35 #define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
36 #define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
37 #define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
38 #define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
39 #define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
40 #define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
41 #define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
42 #define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
43 #define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
44 #define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
45 #define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
46 #define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
47 #define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
48 #define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
49 #define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
50 #define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
51 #define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
52 #define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
53 #define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
54 
55 #define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
56 #define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
57 #define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
58 #define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
59 #define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)
60 
61 union cvmx_pow_bist_stat {
62 	uint64_t u64;
63 	struct cvmx_pow_bist_stat_s {
64 #ifdef __BIG_ENDIAN_BITFIELD
65 		uint64_t reserved_32_63:32;
66 		uint64_t pp:16;
67 		uint64_t reserved_0_15:16;
68 #else
69 		uint64_t reserved_0_15:16;
70 		uint64_t pp:16;
71 		uint64_t reserved_32_63:32;
72 #endif
73 	} s;
74 	struct cvmx_pow_bist_stat_cn30xx {
75 #ifdef __BIG_ENDIAN_BITFIELD
76 		uint64_t reserved_17_63:47;
77 		uint64_t pp:1;
78 		uint64_t reserved_9_15:7;
79 		uint64_t cam:1;
80 		uint64_t nbt1:1;
81 		uint64_t nbt0:1;
82 		uint64_t index:1;
83 		uint64_t fidx:1;
84 		uint64_t nbr1:1;
85 		uint64_t nbr0:1;
86 		uint64_t pend:1;
87 		uint64_t adr:1;
88 #else
89 		uint64_t adr:1;
90 		uint64_t pend:1;
91 		uint64_t nbr0:1;
92 		uint64_t nbr1:1;
93 		uint64_t fidx:1;
94 		uint64_t index:1;
95 		uint64_t nbt0:1;
96 		uint64_t nbt1:1;
97 		uint64_t cam:1;
98 		uint64_t reserved_9_15:7;
99 		uint64_t pp:1;
100 		uint64_t reserved_17_63:47;
101 #endif
102 	} cn30xx;
103 	struct cvmx_pow_bist_stat_cn31xx {
104 #ifdef __BIG_ENDIAN_BITFIELD
105 		uint64_t reserved_18_63:46;
106 		uint64_t pp:2;
107 		uint64_t reserved_9_15:7;
108 		uint64_t cam:1;
109 		uint64_t nbt1:1;
110 		uint64_t nbt0:1;
111 		uint64_t index:1;
112 		uint64_t fidx:1;
113 		uint64_t nbr1:1;
114 		uint64_t nbr0:1;
115 		uint64_t pend:1;
116 		uint64_t adr:1;
117 #else
118 		uint64_t adr:1;
119 		uint64_t pend:1;
120 		uint64_t nbr0:1;
121 		uint64_t nbr1:1;
122 		uint64_t fidx:1;
123 		uint64_t index:1;
124 		uint64_t nbt0:1;
125 		uint64_t nbt1:1;
126 		uint64_t cam:1;
127 		uint64_t reserved_9_15:7;
128 		uint64_t pp:2;
129 		uint64_t reserved_18_63:46;
130 #endif
131 	} cn31xx;
132 	struct cvmx_pow_bist_stat_cn38xx {
133 #ifdef __BIG_ENDIAN_BITFIELD
134 		uint64_t reserved_32_63:32;
135 		uint64_t pp:16;
136 		uint64_t reserved_10_15:6;
137 		uint64_t cam:1;
138 		uint64_t nbt:1;
139 		uint64_t index:1;
140 		uint64_t fidx:1;
141 		uint64_t nbr1:1;
142 		uint64_t nbr0:1;
143 		uint64_t pend1:1;
144 		uint64_t pend0:1;
145 		uint64_t adr1:1;
146 		uint64_t adr0:1;
147 #else
148 		uint64_t adr0:1;
149 		uint64_t adr1:1;
150 		uint64_t pend0:1;
151 		uint64_t pend1:1;
152 		uint64_t nbr0:1;
153 		uint64_t nbr1:1;
154 		uint64_t fidx:1;
155 		uint64_t index:1;
156 		uint64_t nbt:1;
157 		uint64_t cam:1;
158 		uint64_t reserved_10_15:6;
159 		uint64_t pp:16;
160 		uint64_t reserved_32_63:32;
161 #endif
162 	} cn38xx;
163 	struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
164 	struct cvmx_pow_bist_stat_cn31xx cn50xx;
165 	struct cvmx_pow_bist_stat_cn52xx {
166 #ifdef __BIG_ENDIAN_BITFIELD
167 		uint64_t reserved_20_63:44;
168 		uint64_t pp:4;
169 		uint64_t reserved_9_15:7;
170 		uint64_t cam:1;
171 		uint64_t nbt1:1;
172 		uint64_t nbt0:1;
173 		uint64_t index:1;
174 		uint64_t fidx:1;
175 		uint64_t nbr1:1;
176 		uint64_t nbr0:1;
177 		uint64_t pend:1;
178 		uint64_t adr:1;
179 #else
180 		uint64_t adr:1;
181 		uint64_t pend:1;
182 		uint64_t nbr0:1;
183 		uint64_t nbr1:1;
184 		uint64_t fidx:1;
185 		uint64_t index:1;
186 		uint64_t nbt0:1;
187 		uint64_t nbt1:1;
188 		uint64_t cam:1;
189 		uint64_t reserved_9_15:7;
190 		uint64_t pp:4;
191 		uint64_t reserved_20_63:44;
192 #endif
193 	} cn52xx;
194 	struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
195 	struct cvmx_pow_bist_stat_cn56xx {
196 #ifdef __BIG_ENDIAN_BITFIELD
197 		uint64_t reserved_28_63:36;
198 		uint64_t pp:12;
199 		uint64_t reserved_10_15:6;
200 		uint64_t cam:1;
201 		uint64_t nbt:1;
202 		uint64_t index:1;
203 		uint64_t fidx:1;
204 		uint64_t nbr1:1;
205 		uint64_t nbr0:1;
206 		uint64_t pend1:1;
207 		uint64_t pend0:1;
208 		uint64_t adr1:1;
209 		uint64_t adr0:1;
210 #else
211 		uint64_t adr0:1;
212 		uint64_t adr1:1;
213 		uint64_t pend0:1;
214 		uint64_t pend1:1;
215 		uint64_t nbr0:1;
216 		uint64_t nbr1:1;
217 		uint64_t fidx:1;
218 		uint64_t index:1;
219 		uint64_t nbt:1;
220 		uint64_t cam:1;
221 		uint64_t reserved_10_15:6;
222 		uint64_t pp:12;
223 		uint64_t reserved_28_63:36;
224 #endif
225 	} cn56xx;
226 	struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
227 	struct cvmx_pow_bist_stat_cn38xx cn58xx;
228 	struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
229 	struct cvmx_pow_bist_stat_cn61xx {
230 #ifdef __BIG_ENDIAN_BITFIELD
231 		uint64_t reserved_20_63:44;
232 		uint64_t pp:4;
233 		uint64_t reserved_12_15:4;
234 		uint64_t cam:1;
235 		uint64_t nbr:3;
236 		uint64_t nbt:4;
237 		uint64_t index:1;
238 		uint64_t fidx:1;
239 		uint64_t pend:1;
240 		uint64_t adr:1;
241 #else
242 		uint64_t adr:1;
243 		uint64_t pend:1;
244 		uint64_t fidx:1;
245 		uint64_t index:1;
246 		uint64_t nbt:4;
247 		uint64_t nbr:3;
248 		uint64_t cam:1;
249 		uint64_t reserved_12_15:4;
250 		uint64_t pp:4;
251 		uint64_t reserved_20_63:44;
252 #endif
253 	} cn61xx;
254 	struct cvmx_pow_bist_stat_cn63xx {
255 #ifdef __BIG_ENDIAN_BITFIELD
256 		uint64_t reserved_22_63:42;
257 		uint64_t pp:6;
258 		uint64_t reserved_12_15:4;
259 		uint64_t cam:1;
260 		uint64_t nbr:3;
261 		uint64_t nbt:4;
262 		uint64_t index:1;
263 		uint64_t fidx:1;
264 		uint64_t pend:1;
265 		uint64_t adr:1;
266 #else
267 		uint64_t adr:1;
268 		uint64_t pend:1;
269 		uint64_t fidx:1;
270 		uint64_t index:1;
271 		uint64_t nbt:4;
272 		uint64_t nbr:3;
273 		uint64_t cam:1;
274 		uint64_t reserved_12_15:4;
275 		uint64_t pp:6;
276 		uint64_t reserved_22_63:42;
277 #endif
278 	} cn63xx;
279 	struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
280 	struct cvmx_pow_bist_stat_cn66xx {
281 #ifdef __BIG_ENDIAN_BITFIELD
282 		uint64_t reserved_26_63:38;
283 		uint64_t pp:10;
284 		uint64_t reserved_12_15:4;
285 		uint64_t cam:1;
286 		uint64_t nbr:3;
287 		uint64_t nbt:4;
288 		uint64_t index:1;
289 		uint64_t fidx:1;
290 		uint64_t pend:1;
291 		uint64_t adr:1;
292 #else
293 		uint64_t adr:1;
294 		uint64_t pend:1;
295 		uint64_t fidx:1;
296 		uint64_t index:1;
297 		uint64_t nbt:4;
298 		uint64_t nbr:3;
299 		uint64_t cam:1;
300 		uint64_t reserved_12_15:4;
301 		uint64_t pp:10;
302 		uint64_t reserved_26_63:38;
303 #endif
304 	} cn66xx;
305 	struct cvmx_pow_bist_stat_cn61xx cnf71xx;
306 };
307 
308 union cvmx_pow_ds_pc {
309 	uint64_t u64;
310 	struct cvmx_pow_ds_pc_s {
311 #ifdef __BIG_ENDIAN_BITFIELD
312 		uint64_t reserved_32_63:32;
313 		uint64_t ds_pc:32;
314 #else
315 		uint64_t ds_pc:32;
316 		uint64_t reserved_32_63:32;
317 #endif
318 	} s;
319 	struct cvmx_pow_ds_pc_s cn30xx;
320 	struct cvmx_pow_ds_pc_s cn31xx;
321 	struct cvmx_pow_ds_pc_s cn38xx;
322 	struct cvmx_pow_ds_pc_s cn38xxp2;
323 	struct cvmx_pow_ds_pc_s cn50xx;
324 	struct cvmx_pow_ds_pc_s cn52xx;
325 	struct cvmx_pow_ds_pc_s cn52xxp1;
326 	struct cvmx_pow_ds_pc_s cn56xx;
327 	struct cvmx_pow_ds_pc_s cn56xxp1;
328 	struct cvmx_pow_ds_pc_s cn58xx;
329 	struct cvmx_pow_ds_pc_s cn58xxp1;
330 	struct cvmx_pow_ds_pc_s cn61xx;
331 	struct cvmx_pow_ds_pc_s cn63xx;
332 	struct cvmx_pow_ds_pc_s cn63xxp1;
333 	struct cvmx_pow_ds_pc_s cn66xx;
334 	struct cvmx_pow_ds_pc_s cnf71xx;
335 };
336 
337 union cvmx_pow_ecc_err {
338 	uint64_t u64;
339 	struct cvmx_pow_ecc_err_s {
340 #ifdef __BIG_ENDIAN_BITFIELD
341 		uint64_t reserved_45_63:19;
342 		uint64_t iop_ie:13;
343 		uint64_t reserved_29_31:3;
344 		uint64_t iop:13;
345 		uint64_t reserved_14_15:2;
346 		uint64_t rpe_ie:1;
347 		uint64_t rpe:1;
348 		uint64_t reserved_9_11:3;
349 		uint64_t syn:5;
350 		uint64_t dbe_ie:1;
351 		uint64_t sbe_ie:1;
352 		uint64_t dbe:1;
353 		uint64_t sbe:1;
354 #else
355 		uint64_t sbe:1;
356 		uint64_t dbe:1;
357 		uint64_t sbe_ie:1;
358 		uint64_t dbe_ie:1;
359 		uint64_t syn:5;
360 		uint64_t reserved_9_11:3;
361 		uint64_t rpe:1;
362 		uint64_t rpe_ie:1;
363 		uint64_t reserved_14_15:2;
364 		uint64_t iop:13;
365 		uint64_t reserved_29_31:3;
366 		uint64_t iop_ie:13;
367 		uint64_t reserved_45_63:19;
368 #endif
369 	} s;
370 	struct cvmx_pow_ecc_err_s cn30xx;
371 	struct cvmx_pow_ecc_err_cn31xx {
372 #ifdef __BIG_ENDIAN_BITFIELD
373 		uint64_t reserved_14_63:50;
374 		uint64_t rpe_ie:1;
375 		uint64_t rpe:1;
376 		uint64_t reserved_9_11:3;
377 		uint64_t syn:5;
378 		uint64_t dbe_ie:1;
379 		uint64_t sbe_ie:1;
380 		uint64_t dbe:1;
381 		uint64_t sbe:1;
382 #else
383 		uint64_t sbe:1;
384 		uint64_t dbe:1;
385 		uint64_t sbe_ie:1;
386 		uint64_t dbe_ie:1;
387 		uint64_t syn:5;
388 		uint64_t reserved_9_11:3;
389 		uint64_t rpe:1;
390 		uint64_t rpe_ie:1;
391 		uint64_t reserved_14_63:50;
392 #endif
393 	} cn31xx;
394 	struct cvmx_pow_ecc_err_s cn38xx;
395 	struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
396 	struct cvmx_pow_ecc_err_s cn50xx;
397 	struct cvmx_pow_ecc_err_s cn52xx;
398 	struct cvmx_pow_ecc_err_s cn52xxp1;
399 	struct cvmx_pow_ecc_err_s cn56xx;
400 	struct cvmx_pow_ecc_err_s cn56xxp1;
401 	struct cvmx_pow_ecc_err_s cn58xx;
402 	struct cvmx_pow_ecc_err_s cn58xxp1;
403 	struct cvmx_pow_ecc_err_s cn61xx;
404 	struct cvmx_pow_ecc_err_s cn63xx;
405 	struct cvmx_pow_ecc_err_s cn63xxp1;
406 	struct cvmx_pow_ecc_err_s cn66xx;
407 	struct cvmx_pow_ecc_err_s cnf71xx;
408 };
409 
410 union cvmx_pow_int_ctl {
411 	uint64_t u64;
412 	struct cvmx_pow_int_ctl_s {
413 #ifdef __BIG_ENDIAN_BITFIELD
414 		uint64_t reserved_6_63:58;
415 		uint64_t pfr_dis:1;
416 		uint64_t nbr_thr:5;
417 #else
418 		uint64_t nbr_thr:5;
419 		uint64_t pfr_dis:1;
420 		uint64_t reserved_6_63:58;
421 #endif
422 	} s;
423 	struct cvmx_pow_int_ctl_s cn30xx;
424 	struct cvmx_pow_int_ctl_s cn31xx;
425 	struct cvmx_pow_int_ctl_s cn38xx;
426 	struct cvmx_pow_int_ctl_s cn38xxp2;
427 	struct cvmx_pow_int_ctl_s cn50xx;
428 	struct cvmx_pow_int_ctl_s cn52xx;
429 	struct cvmx_pow_int_ctl_s cn52xxp1;
430 	struct cvmx_pow_int_ctl_s cn56xx;
431 	struct cvmx_pow_int_ctl_s cn56xxp1;
432 	struct cvmx_pow_int_ctl_s cn58xx;
433 	struct cvmx_pow_int_ctl_s cn58xxp1;
434 	struct cvmx_pow_int_ctl_s cn61xx;
435 	struct cvmx_pow_int_ctl_s cn63xx;
436 	struct cvmx_pow_int_ctl_s cn63xxp1;
437 	struct cvmx_pow_int_ctl_s cn66xx;
438 	struct cvmx_pow_int_ctl_s cnf71xx;
439 };
440 
441 union cvmx_pow_iq_cntx {
442 	uint64_t u64;
443 	struct cvmx_pow_iq_cntx_s {
444 #ifdef __BIG_ENDIAN_BITFIELD
445 		uint64_t reserved_32_63:32;
446 		uint64_t iq_cnt:32;
447 #else
448 		uint64_t iq_cnt:32;
449 		uint64_t reserved_32_63:32;
450 #endif
451 	} s;
452 	struct cvmx_pow_iq_cntx_s cn30xx;
453 	struct cvmx_pow_iq_cntx_s cn31xx;
454 	struct cvmx_pow_iq_cntx_s cn38xx;
455 	struct cvmx_pow_iq_cntx_s cn38xxp2;
456 	struct cvmx_pow_iq_cntx_s cn50xx;
457 	struct cvmx_pow_iq_cntx_s cn52xx;
458 	struct cvmx_pow_iq_cntx_s cn52xxp1;
459 	struct cvmx_pow_iq_cntx_s cn56xx;
460 	struct cvmx_pow_iq_cntx_s cn56xxp1;
461 	struct cvmx_pow_iq_cntx_s cn58xx;
462 	struct cvmx_pow_iq_cntx_s cn58xxp1;
463 	struct cvmx_pow_iq_cntx_s cn61xx;
464 	struct cvmx_pow_iq_cntx_s cn63xx;
465 	struct cvmx_pow_iq_cntx_s cn63xxp1;
466 	struct cvmx_pow_iq_cntx_s cn66xx;
467 	struct cvmx_pow_iq_cntx_s cnf71xx;
468 };
469 
470 union cvmx_pow_iq_com_cnt {
471 	uint64_t u64;
472 	struct cvmx_pow_iq_com_cnt_s {
473 #ifdef __BIG_ENDIAN_BITFIELD
474 		uint64_t reserved_32_63:32;
475 		uint64_t iq_cnt:32;
476 #else
477 		uint64_t iq_cnt:32;
478 		uint64_t reserved_32_63:32;
479 #endif
480 	} s;
481 	struct cvmx_pow_iq_com_cnt_s cn30xx;
482 	struct cvmx_pow_iq_com_cnt_s cn31xx;
483 	struct cvmx_pow_iq_com_cnt_s cn38xx;
484 	struct cvmx_pow_iq_com_cnt_s cn38xxp2;
485 	struct cvmx_pow_iq_com_cnt_s cn50xx;
486 	struct cvmx_pow_iq_com_cnt_s cn52xx;
487 	struct cvmx_pow_iq_com_cnt_s cn52xxp1;
488 	struct cvmx_pow_iq_com_cnt_s cn56xx;
489 	struct cvmx_pow_iq_com_cnt_s cn56xxp1;
490 	struct cvmx_pow_iq_com_cnt_s cn58xx;
491 	struct cvmx_pow_iq_com_cnt_s cn58xxp1;
492 	struct cvmx_pow_iq_com_cnt_s cn61xx;
493 	struct cvmx_pow_iq_com_cnt_s cn63xx;
494 	struct cvmx_pow_iq_com_cnt_s cn63xxp1;
495 	struct cvmx_pow_iq_com_cnt_s cn66xx;
496 	struct cvmx_pow_iq_com_cnt_s cnf71xx;
497 };
498 
499 union cvmx_pow_iq_int {
500 	uint64_t u64;
501 	struct cvmx_pow_iq_int_s {
502 #ifdef __BIG_ENDIAN_BITFIELD
503 		uint64_t reserved_8_63:56;
504 		uint64_t iq_int:8;
505 #else
506 		uint64_t iq_int:8;
507 		uint64_t reserved_8_63:56;
508 #endif
509 	} s;
510 	struct cvmx_pow_iq_int_s cn52xx;
511 	struct cvmx_pow_iq_int_s cn52xxp1;
512 	struct cvmx_pow_iq_int_s cn56xx;
513 	struct cvmx_pow_iq_int_s cn56xxp1;
514 	struct cvmx_pow_iq_int_s cn61xx;
515 	struct cvmx_pow_iq_int_s cn63xx;
516 	struct cvmx_pow_iq_int_s cn63xxp1;
517 	struct cvmx_pow_iq_int_s cn66xx;
518 	struct cvmx_pow_iq_int_s cnf71xx;
519 };
520 
521 union cvmx_pow_iq_int_en {
522 	uint64_t u64;
523 	struct cvmx_pow_iq_int_en_s {
524 #ifdef __BIG_ENDIAN_BITFIELD
525 		uint64_t reserved_8_63:56;
526 		uint64_t int_en:8;
527 #else
528 		uint64_t int_en:8;
529 		uint64_t reserved_8_63:56;
530 #endif
531 	} s;
532 	struct cvmx_pow_iq_int_en_s cn52xx;
533 	struct cvmx_pow_iq_int_en_s cn52xxp1;
534 	struct cvmx_pow_iq_int_en_s cn56xx;
535 	struct cvmx_pow_iq_int_en_s cn56xxp1;
536 	struct cvmx_pow_iq_int_en_s cn61xx;
537 	struct cvmx_pow_iq_int_en_s cn63xx;
538 	struct cvmx_pow_iq_int_en_s cn63xxp1;
539 	struct cvmx_pow_iq_int_en_s cn66xx;
540 	struct cvmx_pow_iq_int_en_s cnf71xx;
541 };
542 
543 union cvmx_pow_iq_thrx {
544 	uint64_t u64;
545 	struct cvmx_pow_iq_thrx_s {
546 #ifdef __BIG_ENDIAN_BITFIELD
547 		uint64_t reserved_32_63:32;
548 		uint64_t iq_thr:32;
549 #else
550 		uint64_t iq_thr:32;
551 		uint64_t reserved_32_63:32;
552 #endif
553 	} s;
554 	struct cvmx_pow_iq_thrx_s cn52xx;
555 	struct cvmx_pow_iq_thrx_s cn52xxp1;
556 	struct cvmx_pow_iq_thrx_s cn56xx;
557 	struct cvmx_pow_iq_thrx_s cn56xxp1;
558 	struct cvmx_pow_iq_thrx_s cn61xx;
559 	struct cvmx_pow_iq_thrx_s cn63xx;
560 	struct cvmx_pow_iq_thrx_s cn63xxp1;
561 	struct cvmx_pow_iq_thrx_s cn66xx;
562 	struct cvmx_pow_iq_thrx_s cnf71xx;
563 };
564 
565 union cvmx_pow_nos_cnt {
566 	uint64_t u64;
567 	struct cvmx_pow_nos_cnt_s {
568 #ifdef __BIG_ENDIAN_BITFIELD
569 		uint64_t reserved_12_63:52;
570 		uint64_t nos_cnt:12;
571 #else
572 		uint64_t nos_cnt:12;
573 		uint64_t reserved_12_63:52;
574 #endif
575 	} s;
576 	struct cvmx_pow_nos_cnt_cn30xx {
577 #ifdef __BIG_ENDIAN_BITFIELD
578 		uint64_t reserved_7_63:57;
579 		uint64_t nos_cnt:7;
580 #else
581 		uint64_t nos_cnt:7;
582 		uint64_t reserved_7_63:57;
583 #endif
584 	} cn30xx;
585 	struct cvmx_pow_nos_cnt_cn31xx {
586 #ifdef __BIG_ENDIAN_BITFIELD
587 		uint64_t reserved_9_63:55;
588 		uint64_t nos_cnt:9;
589 #else
590 		uint64_t nos_cnt:9;
591 		uint64_t reserved_9_63:55;
592 #endif
593 	} cn31xx;
594 	struct cvmx_pow_nos_cnt_s cn38xx;
595 	struct cvmx_pow_nos_cnt_s cn38xxp2;
596 	struct cvmx_pow_nos_cnt_cn31xx cn50xx;
597 	struct cvmx_pow_nos_cnt_cn52xx {
598 #ifdef __BIG_ENDIAN_BITFIELD
599 		uint64_t reserved_10_63:54;
600 		uint64_t nos_cnt:10;
601 #else
602 		uint64_t nos_cnt:10;
603 		uint64_t reserved_10_63:54;
604 #endif
605 	} cn52xx;
606 	struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
607 	struct cvmx_pow_nos_cnt_s cn56xx;
608 	struct cvmx_pow_nos_cnt_s cn56xxp1;
609 	struct cvmx_pow_nos_cnt_s cn58xx;
610 	struct cvmx_pow_nos_cnt_s cn58xxp1;
611 	struct cvmx_pow_nos_cnt_cn52xx cn61xx;
612 	struct cvmx_pow_nos_cnt_cn63xx {
613 #ifdef __BIG_ENDIAN_BITFIELD
614 		uint64_t reserved_11_63:53;
615 		uint64_t nos_cnt:11;
616 #else
617 		uint64_t nos_cnt:11;
618 		uint64_t reserved_11_63:53;
619 #endif
620 	} cn63xx;
621 	struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
622 	struct cvmx_pow_nos_cnt_cn63xx cn66xx;
623 	struct cvmx_pow_nos_cnt_cn52xx cnf71xx;
624 };
625 
626 union cvmx_pow_nw_tim {
627 	uint64_t u64;
628 	struct cvmx_pow_nw_tim_s {
629 #ifdef __BIG_ENDIAN_BITFIELD
630 		uint64_t reserved_10_63:54;
631 		uint64_t nw_tim:10;
632 #else
633 		uint64_t nw_tim:10;
634 		uint64_t reserved_10_63:54;
635 #endif
636 	} s;
637 	struct cvmx_pow_nw_tim_s cn30xx;
638 	struct cvmx_pow_nw_tim_s cn31xx;
639 	struct cvmx_pow_nw_tim_s cn38xx;
640 	struct cvmx_pow_nw_tim_s cn38xxp2;
641 	struct cvmx_pow_nw_tim_s cn50xx;
642 	struct cvmx_pow_nw_tim_s cn52xx;
643 	struct cvmx_pow_nw_tim_s cn52xxp1;
644 	struct cvmx_pow_nw_tim_s cn56xx;
645 	struct cvmx_pow_nw_tim_s cn56xxp1;
646 	struct cvmx_pow_nw_tim_s cn58xx;
647 	struct cvmx_pow_nw_tim_s cn58xxp1;
648 	struct cvmx_pow_nw_tim_s cn61xx;
649 	struct cvmx_pow_nw_tim_s cn63xx;
650 	struct cvmx_pow_nw_tim_s cn63xxp1;
651 	struct cvmx_pow_nw_tim_s cn66xx;
652 	struct cvmx_pow_nw_tim_s cnf71xx;
653 };
654 
655 union cvmx_pow_pf_rst_msk {
656 	uint64_t u64;
657 	struct cvmx_pow_pf_rst_msk_s {
658 #ifdef __BIG_ENDIAN_BITFIELD
659 		uint64_t reserved_8_63:56;
660 		uint64_t rst_msk:8;
661 #else
662 		uint64_t rst_msk:8;
663 		uint64_t reserved_8_63:56;
664 #endif
665 	} s;
666 	struct cvmx_pow_pf_rst_msk_s cn50xx;
667 	struct cvmx_pow_pf_rst_msk_s cn52xx;
668 	struct cvmx_pow_pf_rst_msk_s cn52xxp1;
669 	struct cvmx_pow_pf_rst_msk_s cn56xx;
670 	struct cvmx_pow_pf_rst_msk_s cn56xxp1;
671 	struct cvmx_pow_pf_rst_msk_s cn58xx;
672 	struct cvmx_pow_pf_rst_msk_s cn58xxp1;
673 	struct cvmx_pow_pf_rst_msk_s cn61xx;
674 	struct cvmx_pow_pf_rst_msk_s cn63xx;
675 	struct cvmx_pow_pf_rst_msk_s cn63xxp1;
676 	struct cvmx_pow_pf_rst_msk_s cn66xx;
677 	struct cvmx_pow_pf_rst_msk_s cnf71xx;
678 };
679 
680 union cvmx_pow_pp_grp_mskx {
681 	uint64_t u64;
682 	struct cvmx_pow_pp_grp_mskx_s {
683 #ifdef __BIG_ENDIAN_BITFIELD
684 		uint64_t reserved_48_63:16;
685 		uint64_t qos7_pri:4;
686 		uint64_t qos6_pri:4;
687 		uint64_t qos5_pri:4;
688 		uint64_t qos4_pri:4;
689 		uint64_t qos3_pri:4;
690 		uint64_t qos2_pri:4;
691 		uint64_t qos1_pri:4;
692 		uint64_t qos0_pri:4;
693 		uint64_t grp_msk:16;
694 #else
695 		uint64_t grp_msk:16;
696 		uint64_t qos0_pri:4;
697 		uint64_t qos1_pri:4;
698 		uint64_t qos2_pri:4;
699 		uint64_t qos3_pri:4;
700 		uint64_t qos4_pri:4;
701 		uint64_t qos5_pri:4;
702 		uint64_t qos6_pri:4;
703 		uint64_t qos7_pri:4;
704 		uint64_t reserved_48_63:16;
705 #endif
706 	} s;
707 	struct cvmx_pow_pp_grp_mskx_cn30xx {
708 #ifdef __BIG_ENDIAN_BITFIELD
709 		uint64_t reserved_16_63:48;
710 		uint64_t grp_msk:16;
711 #else
712 		uint64_t grp_msk:16;
713 		uint64_t reserved_16_63:48;
714 #endif
715 	} cn30xx;
716 	struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
717 	struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
718 	struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;
719 	struct cvmx_pow_pp_grp_mskx_s cn50xx;
720 	struct cvmx_pow_pp_grp_mskx_s cn52xx;
721 	struct cvmx_pow_pp_grp_mskx_s cn52xxp1;
722 	struct cvmx_pow_pp_grp_mskx_s cn56xx;
723 	struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
724 	struct cvmx_pow_pp_grp_mskx_s cn58xx;
725 	struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
726 	struct cvmx_pow_pp_grp_mskx_s cn61xx;
727 	struct cvmx_pow_pp_grp_mskx_s cn63xx;
728 	struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
729 	struct cvmx_pow_pp_grp_mskx_s cn66xx;
730 	struct cvmx_pow_pp_grp_mskx_s cnf71xx;
731 };
732 
733 union cvmx_pow_qos_rndx {
734 	uint64_t u64;
735 	struct cvmx_pow_qos_rndx_s {
736 #ifdef __BIG_ENDIAN_BITFIELD
737 		uint64_t reserved_32_63:32;
738 		uint64_t rnd_p3:8;
739 		uint64_t rnd_p2:8;
740 		uint64_t rnd_p1:8;
741 		uint64_t rnd:8;
742 #else
743 		uint64_t rnd:8;
744 		uint64_t rnd_p1:8;
745 		uint64_t rnd_p2:8;
746 		uint64_t rnd_p3:8;
747 		uint64_t reserved_32_63:32;
748 #endif
749 	} s;
750 	struct cvmx_pow_qos_rndx_s cn30xx;
751 	struct cvmx_pow_qos_rndx_s cn31xx;
752 	struct cvmx_pow_qos_rndx_s cn38xx;
753 	struct cvmx_pow_qos_rndx_s cn38xxp2;
754 	struct cvmx_pow_qos_rndx_s cn50xx;
755 	struct cvmx_pow_qos_rndx_s cn52xx;
756 	struct cvmx_pow_qos_rndx_s cn52xxp1;
757 	struct cvmx_pow_qos_rndx_s cn56xx;
758 	struct cvmx_pow_qos_rndx_s cn56xxp1;
759 	struct cvmx_pow_qos_rndx_s cn58xx;
760 	struct cvmx_pow_qos_rndx_s cn58xxp1;
761 	struct cvmx_pow_qos_rndx_s cn61xx;
762 	struct cvmx_pow_qos_rndx_s cn63xx;
763 	struct cvmx_pow_qos_rndx_s cn63xxp1;
764 	struct cvmx_pow_qos_rndx_s cn66xx;
765 	struct cvmx_pow_qos_rndx_s cnf71xx;
766 };
767 
768 union cvmx_pow_qos_thrx {
769 	uint64_t u64;
770 	struct cvmx_pow_qos_thrx_s {
771 #ifdef __BIG_ENDIAN_BITFIELD
772 		uint64_t reserved_60_63:4;
773 		uint64_t des_cnt:12;
774 		uint64_t buf_cnt:12;
775 		uint64_t free_cnt:12;
776 		uint64_t reserved_23_23:1;
777 		uint64_t max_thr:11;
778 		uint64_t reserved_11_11:1;
779 		uint64_t min_thr:11;
780 #else
781 		uint64_t min_thr:11;
782 		uint64_t reserved_11_11:1;
783 		uint64_t max_thr:11;
784 		uint64_t reserved_23_23:1;
785 		uint64_t free_cnt:12;
786 		uint64_t buf_cnt:12;
787 		uint64_t des_cnt:12;
788 		uint64_t reserved_60_63:4;
789 #endif
790 	} s;
791 	struct cvmx_pow_qos_thrx_cn30xx {
792 #ifdef __BIG_ENDIAN_BITFIELD
793 		uint64_t reserved_55_63:9;
794 		uint64_t des_cnt:7;
795 		uint64_t reserved_43_47:5;
796 		uint64_t buf_cnt:7;
797 		uint64_t reserved_31_35:5;
798 		uint64_t free_cnt:7;
799 		uint64_t reserved_18_23:6;
800 		uint64_t max_thr:6;
801 		uint64_t reserved_6_11:6;
802 		uint64_t min_thr:6;
803 #else
804 		uint64_t min_thr:6;
805 		uint64_t reserved_6_11:6;
806 		uint64_t max_thr:6;
807 		uint64_t reserved_18_23:6;
808 		uint64_t free_cnt:7;
809 		uint64_t reserved_31_35:5;
810 		uint64_t buf_cnt:7;
811 		uint64_t reserved_43_47:5;
812 		uint64_t des_cnt:7;
813 		uint64_t reserved_55_63:9;
814 #endif
815 	} cn30xx;
816 	struct cvmx_pow_qos_thrx_cn31xx {
817 #ifdef __BIG_ENDIAN_BITFIELD
818 		uint64_t reserved_57_63:7;
819 		uint64_t des_cnt:9;
820 		uint64_t reserved_45_47:3;
821 		uint64_t buf_cnt:9;
822 		uint64_t reserved_33_35:3;
823 		uint64_t free_cnt:9;
824 		uint64_t reserved_20_23:4;
825 		uint64_t max_thr:8;
826 		uint64_t reserved_8_11:4;
827 		uint64_t min_thr:8;
828 #else
829 		uint64_t min_thr:8;
830 		uint64_t reserved_8_11:4;
831 		uint64_t max_thr:8;
832 		uint64_t reserved_20_23:4;
833 		uint64_t free_cnt:9;
834 		uint64_t reserved_33_35:3;
835 		uint64_t buf_cnt:9;
836 		uint64_t reserved_45_47:3;
837 		uint64_t des_cnt:9;
838 		uint64_t reserved_57_63:7;
839 #endif
840 	} cn31xx;
841 	struct cvmx_pow_qos_thrx_s cn38xx;
842 	struct cvmx_pow_qos_thrx_s cn38xxp2;
843 	struct cvmx_pow_qos_thrx_cn31xx cn50xx;
844 	struct cvmx_pow_qos_thrx_cn52xx {
845 #ifdef __BIG_ENDIAN_BITFIELD
846 		uint64_t reserved_58_63:6;
847 		uint64_t des_cnt:10;
848 		uint64_t reserved_46_47:2;
849 		uint64_t buf_cnt:10;
850 		uint64_t reserved_34_35:2;
851 		uint64_t free_cnt:10;
852 		uint64_t reserved_21_23:3;
853 		uint64_t max_thr:9;
854 		uint64_t reserved_9_11:3;
855 		uint64_t min_thr:9;
856 #else
857 		uint64_t min_thr:9;
858 		uint64_t reserved_9_11:3;
859 		uint64_t max_thr:9;
860 		uint64_t reserved_21_23:3;
861 		uint64_t free_cnt:10;
862 		uint64_t reserved_34_35:2;
863 		uint64_t buf_cnt:10;
864 		uint64_t reserved_46_47:2;
865 		uint64_t des_cnt:10;
866 		uint64_t reserved_58_63:6;
867 #endif
868 	} cn52xx;
869 	struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
870 	struct cvmx_pow_qos_thrx_s cn56xx;
871 	struct cvmx_pow_qos_thrx_s cn56xxp1;
872 	struct cvmx_pow_qos_thrx_s cn58xx;
873 	struct cvmx_pow_qos_thrx_s cn58xxp1;
874 	struct cvmx_pow_qos_thrx_cn52xx cn61xx;
875 	struct cvmx_pow_qos_thrx_cn63xx {
876 #ifdef __BIG_ENDIAN_BITFIELD
877 		uint64_t reserved_59_63:5;
878 		uint64_t des_cnt:11;
879 		uint64_t reserved_47_47:1;
880 		uint64_t buf_cnt:11;
881 		uint64_t reserved_35_35:1;
882 		uint64_t free_cnt:11;
883 		uint64_t reserved_22_23:2;
884 		uint64_t max_thr:10;
885 		uint64_t reserved_10_11:2;
886 		uint64_t min_thr:10;
887 #else
888 		uint64_t min_thr:10;
889 		uint64_t reserved_10_11:2;
890 		uint64_t max_thr:10;
891 		uint64_t reserved_22_23:2;
892 		uint64_t free_cnt:11;
893 		uint64_t reserved_35_35:1;
894 		uint64_t buf_cnt:11;
895 		uint64_t reserved_47_47:1;
896 		uint64_t des_cnt:11;
897 		uint64_t reserved_59_63:5;
898 #endif
899 	} cn63xx;
900 	struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
901 	struct cvmx_pow_qos_thrx_cn63xx cn66xx;
902 	struct cvmx_pow_qos_thrx_cn52xx cnf71xx;
903 };
904 
905 union cvmx_pow_ts_pc {
906 	uint64_t u64;
907 	struct cvmx_pow_ts_pc_s {
908 #ifdef __BIG_ENDIAN_BITFIELD
909 		uint64_t reserved_32_63:32;
910 		uint64_t ts_pc:32;
911 #else
912 		uint64_t ts_pc:32;
913 		uint64_t reserved_32_63:32;
914 #endif
915 	} s;
916 	struct cvmx_pow_ts_pc_s cn30xx;
917 	struct cvmx_pow_ts_pc_s cn31xx;
918 	struct cvmx_pow_ts_pc_s cn38xx;
919 	struct cvmx_pow_ts_pc_s cn38xxp2;
920 	struct cvmx_pow_ts_pc_s cn50xx;
921 	struct cvmx_pow_ts_pc_s cn52xx;
922 	struct cvmx_pow_ts_pc_s cn52xxp1;
923 	struct cvmx_pow_ts_pc_s cn56xx;
924 	struct cvmx_pow_ts_pc_s cn56xxp1;
925 	struct cvmx_pow_ts_pc_s cn58xx;
926 	struct cvmx_pow_ts_pc_s cn58xxp1;
927 	struct cvmx_pow_ts_pc_s cn61xx;
928 	struct cvmx_pow_ts_pc_s cn63xx;
929 	struct cvmx_pow_ts_pc_s cn63xxp1;
930 	struct cvmx_pow_ts_pc_s cn66xx;
931 	struct cvmx_pow_ts_pc_s cnf71xx;
932 };
933 
934 union cvmx_pow_wa_com_pc {
935 	uint64_t u64;
936 	struct cvmx_pow_wa_com_pc_s {
937 #ifdef __BIG_ENDIAN_BITFIELD
938 		uint64_t reserved_32_63:32;
939 		uint64_t wa_pc:32;
940 #else
941 		uint64_t wa_pc:32;
942 		uint64_t reserved_32_63:32;
943 #endif
944 	} s;
945 	struct cvmx_pow_wa_com_pc_s cn30xx;
946 	struct cvmx_pow_wa_com_pc_s cn31xx;
947 	struct cvmx_pow_wa_com_pc_s cn38xx;
948 	struct cvmx_pow_wa_com_pc_s cn38xxp2;
949 	struct cvmx_pow_wa_com_pc_s cn50xx;
950 	struct cvmx_pow_wa_com_pc_s cn52xx;
951 	struct cvmx_pow_wa_com_pc_s cn52xxp1;
952 	struct cvmx_pow_wa_com_pc_s cn56xx;
953 	struct cvmx_pow_wa_com_pc_s cn56xxp1;
954 	struct cvmx_pow_wa_com_pc_s cn58xx;
955 	struct cvmx_pow_wa_com_pc_s cn58xxp1;
956 	struct cvmx_pow_wa_com_pc_s cn61xx;
957 	struct cvmx_pow_wa_com_pc_s cn63xx;
958 	struct cvmx_pow_wa_com_pc_s cn63xxp1;
959 	struct cvmx_pow_wa_com_pc_s cn66xx;
960 	struct cvmx_pow_wa_com_pc_s cnf71xx;
961 };
962 
963 union cvmx_pow_wa_pcx {
964 	uint64_t u64;
965 	struct cvmx_pow_wa_pcx_s {
966 #ifdef __BIG_ENDIAN_BITFIELD
967 		uint64_t reserved_32_63:32;
968 		uint64_t wa_pc:32;
969 #else
970 		uint64_t wa_pc:32;
971 		uint64_t reserved_32_63:32;
972 #endif
973 	} s;
974 	struct cvmx_pow_wa_pcx_s cn30xx;
975 	struct cvmx_pow_wa_pcx_s cn31xx;
976 	struct cvmx_pow_wa_pcx_s cn38xx;
977 	struct cvmx_pow_wa_pcx_s cn38xxp2;
978 	struct cvmx_pow_wa_pcx_s cn50xx;
979 	struct cvmx_pow_wa_pcx_s cn52xx;
980 	struct cvmx_pow_wa_pcx_s cn52xxp1;
981 	struct cvmx_pow_wa_pcx_s cn56xx;
982 	struct cvmx_pow_wa_pcx_s cn56xxp1;
983 	struct cvmx_pow_wa_pcx_s cn58xx;
984 	struct cvmx_pow_wa_pcx_s cn58xxp1;
985 	struct cvmx_pow_wa_pcx_s cn61xx;
986 	struct cvmx_pow_wa_pcx_s cn63xx;
987 	struct cvmx_pow_wa_pcx_s cn63xxp1;
988 	struct cvmx_pow_wa_pcx_s cn66xx;
989 	struct cvmx_pow_wa_pcx_s cnf71xx;
990 };
991 
992 union cvmx_pow_wq_int {
993 	uint64_t u64;
994 	struct cvmx_pow_wq_int_s {
995 #ifdef __BIG_ENDIAN_BITFIELD
996 		uint64_t reserved_32_63:32;
997 		uint64_t iq_dis:16;
998 		uint64_t wq_int:16;
999 #else
1000 		uint64_t wq_int:16;
1001 		uint64_t iq_dis:16;
1002 		uint64_t reserved_32_63:32;
1003 #endif
1004 	} s;
1005 	struct cvmx_pow_wq_int_s cn30xx;
1006 	struct cvmx_pow_wq_int_s cn31xx;
1007 	struct cvmx_pow_wq_int_s cn38xx;
1008 	struct cvmx_pow_wq_int_s cn38xxp2;
1009 	struct cvmx_pow_wq_int_s cn50xx;
1010 	struct cvmx_pow_wq_int_s cn52xx;
1011 	struct cvmx_pow_wq_int_s cn52xxp1;
1012 	struct cvmx_pow_wq_int_s cn56xx;
1013 	struct cvmx_pow_wq_int_s cn56xxp1;
1014 	struct cvmx_pow_wq_int_s cn58xx;
1015 	struct cvmx_pow_wq_int_s cn58xxp1;
1016 	struct cvmx_pow_wq_int_s cn61xx;
1017 	struct cvmx_pow_wq_int_s cn63xx;
1018 	struct cvmx_pow_wq_int_s cn63xxp1;
1019 	struct cvmx_pow_wq_int_s cn66xx;
1020 	struct cvmx_pow_wq_int_s cnf71xx;
1021 };
1022 
1023 union cvmx_pow_wq_int_cntx {
1024 	uint64_t u64;
1025 	struct cvmx_pow_wq_int_cntx_s {
1026 #ifdef __BIG_ENDIAN_BITFIELD
1027 		uint64_t reserved_28_63:36;
1028 		uint64_t tc_cnt:4;
1029 		uint64_t ds_cnt:12;
1030 		uint64_t iq_cnt:12;
1031 #else
1032 		uint64_t iq_cnt:12;
1033 		uint64_t ds_cnt:12;
1034 		uint64_t tc_cnt:4;
1035 		uint64_t reserved_28_63:36;
1036 #endif
1037 	} s;
1038 	struct cvmx_pow_wq_int_cntx_cn30xx {
1039 #ifdef __BIG_ENDIAN_BITFIELD
1040 		uint64_t reserved_28_63:36;
1041 		uint64_t tc_cnt:4;
1042 		uint64_t reserved_19_23:5;
1043 		uint64_t ds_cnt:7;
1044 		uint64_t reserved_7_11:5;
1045 		uint64_t iq_cnt:7;
1046 #else
1047 		uint64_t iq_cnt:7;
1048 		uint64_t reserved_7_11:5;
1049 		uint64_t ds_cnt:7;
1050 		uint64_t reserved_19_23:5;
1051 		uint64_t tc_cnt:4;
1052 		uint64_t reserved_28_63:36;
1053 #endif
1054 	} cn30xx;
1055 	struct cvmx_pow_wq_int_cntx_cn31xx {
1056 #ifdef __BIG_ENDIAN_BITFIELD
1057 		uint64_t reserved_28_63:36;
1058 		uint64_t tc_cnt:4;
1059 		uint64_t reserved_21_23:3;
1060 		uint64_t ds_cnt:9;
1061 		uint64_t reserved_9_11:3;
1062 		uint64_t iq_cnt:9;
1063 #else
1064 		uint64_t iq_cnt:9;
1065 		uint64_t reserved_9_11:3;
1066 		uint64_t ds_cnt:9;
1067 		uint64_t reserved_21_23:3;
1068 		uint64_t tc_cnt:4;
1069 		uint64_t reserved_28_63:36;
1070 #endif
1071 	} cn31xx;
1072 	struct cvmx_pow_wq_int_cntx_s cn38xx;
1073 	struct cvmx_pow_wq_int_cntx_s cn38xxp2;
1074 	struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
1075 	struct cvmx_pow_wq_int_cntx_cn52xx {
1076 #ifdef __BIG_ENDIAN_BITFIELD
1077 		uint64_t reserved_28_63:36;
1078 		uint64_t tc_cnt:4;
1079 		uint64_t reserved_22_23:2;
1080 		uint64_t ds_cnt:10;
1081 		uint64_t reserved_10_11:2;
1082 		uint64_t iq_cnt:10;
1083 #else
1084 		uint64_t iq_cnt:10;
1085 		uint64_t reserved_10_11:2;
1086 		uint64_t ds_cnt:10;
1087 		uint64_t reserved_22_23:2;
1088 		uint64_t tc_cnt:4;
1089 		uint64_t reserved_28_63:36;
1090 #endif
1091 	} cn52xx;
1092 	struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
1093 	struct cvmx_pow_wq_int_cntx_s cn56xx;
1094 	struct cvmx_pow_wq_int_cntx_s cn56xxp1;
1095 	struct cvmx_pow_wq_int_cntx_s cn58xx;
1096 	struct cvmx_pow_wq_int_cntx_s cn58xxp1;
1097 	struct cvmx_pow_wq_int_cntx_cn52xx cn61xx;
1098 	struct cvmx_pow_wq_int_cntx_cn63xx {
1099 #ifdef __BIG_ENDIAN_BITFIELD
1100 		uint64_t reserved_28_63:36;
1101 		uint64_t tc_cnt:4;
1102 		uint64_t reserved_23_23:1;
1103 		uint64_t ds_cnt:11;
1104 		uint64_t reserved_11_11:1;
1105 		uint64_t iq_cnt:11;
1106 #else
1107 		uint64_t iq_cnt:11;
1108 		uint64_t reserved_11_11:1;
1109 		uint64_t ds_cnt:11;
1110 		uint64_t reserved_23_23:1;
1111 		uint64_t tc_cnt:4;
1112 		uint64_t reserved_28_63:36;
1113 #endif
1114 	} cn63xx;
1115 	struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
1116 	struct cvmx_pow_wq_int_cntx_cn63xx cn66xx;
1117 	struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx;
1118 };
1119 
1120 union cvmx_pow_wq_int_pc {
1121 	uint64_t u64;
1122 	struct cvmx_pow_wq_int_pc_s {
1123 #ifdef __BIG_ENDIAN_BITFIELD
1124 		uint64_t reserved_60_63:4;
1125 		uint64_t pc:28;
1126 		uint64_t reserved_28_31:4;
1127 		uint64_t pc_thr:20;
1128 		uint64_t reserved_0_7:8;
1129 #else
1130 		uint64_t reserved_0_7:8;
1131 		uint64_t pc_thr:20;
1132 		uint64_t reserved_28_31:4;
1133 		uint64_t pc:28;
1134 		uint64_t reserved_60_63:4;
1135 #endif
1136 	} s;
1137 	struct cvmx_pow_wq_int_pc_s cn30xx;
1138 	struct cvmx_pow_wq_int_pc_s cn31xx;
1139 	struct cvmx_pow_wq_int_pc_s cn38xx;
1140 	struct cvmx_pow_wq_int_pc_s cn38xxp2;
1141 	struct cvmx_pow_wq_int_pc_s cn50xx;
1142 	struct cvmx_pow_wq_int_pc_s cn52xx;
1143 	struct cvmx_pow_wq_int_pc_s cn52xxp1;
1144 	struct cvmx_pow_wq_int_pc_s cn56xx;
1145 	struct cvmx_pow_wq_int_pc_s cn56xxp1;
1146 	struct cvmx_pow_wq_int_pc_s cn58xx;
1147 	struct cvmx_pow_wq_int_pc_s cn58xxp1;
1148 	struct cvmx_pow_wq_int_pc_s cn61xx;
1149 	struct cvmx_pow_wq_int_pc_s cn63xx;
1150 	struct cvmx_pow_wq_int_pc_s cn63xxp1;
1151 	struct cvmx_pow_wq_int_pc_s cn66xx;
1152 	struct cvmx_pow_wq_int_pc_s cnf71xx;
1153 };
1154 
1155 union cvmx_pow_wq_int_thrx {
1156 	uint64_t u64;
1157 	struct cvmx_pow_wq_int_thrx_s {
1158 #ifdef __BIG_ENDIAN_BITFIELD
1159 		uint64_t reserved_29_63:35;
1160 		uint64_t tc_en:1;
1161 		uint64_t tc_thr:4;
1162 		uint64_t reserved_23_23:1;
1163 		uint64_t ds_thr:11;
1164 		uint64_t reserved_11_11:1;
1165 		uint64_t iq_thr:11;
1166 #else
1167 		uint64_t iq_thr:11;
1168 		uint64_t reserved_11_11:1;
1169 		uint64_t ds_thr:11;
1170 		uint64_t reserved_23_23:1;
1171 		uint64_t tc_thr:4;
1172 		uint64_t tc_en:1;
1173 		uint64_t reserved_29_63:35;
1174 #endif
1175 	} s;
1176 	struct cvmx_pow_wq_int_thrx_cn30xx {
1177 #ifdef __BIG_ENDIAN_BITFIELD
1178 		uint64_t reserved_29_63:35;
1179 		uint64_t tc_en:1;
1180 		uint64_t tc_thr:4;
1181 		uint64_t reserved_18_23:6;
1182 		uint64_t ds_thr:6;
1183 		uint64_t reserved_6_11:6;
1184 		uint64_t iq_thr:6;
1185 #else
1186 		uint64_t iq_thr:6;
1187 		uint64_t reserved_6_11:6;
1188 		uint64_t ds_thr:6;
1189 		uint64_t reserved_18_23:6;
1190 		uint64_t tc_thr:4;
1191 		uint64_t tc_en:1;
1192 		uint64_t reserved_29_63:35;
1193 #endif
1194 	} cn30xx;
1195 	struct cvmx_pow_wq_int_thrx_cn31xx {
1196 #ifdef __BIG_ENDIAN_BITFIELD
1197 		uint64_t reserved_29_63:35;
1198 		uint64_t tc_en:1;
1199 		uint64_t tc_thr:4;
1200 		uint64_t reserved_20_23:4;
1201 		uint64_t ds_thr:8;
1202 		uint64_t reserved_8_11:4;
1203 		uint64_t iq_thr:8;
1204 #else
1205 		uint64_t iq_thr:8;
1206 		uint64_t reserved_8_11:4;
1207 		uint64_t ds_thr:8;
1208 		uint64_t reserved_20_23:4;
1209 		uint64_t tc_thr:4;
1210 		uint64_t tc_en:1;
1211 		uint64_t reserved_29_63:35;
1212 #endif
1213 	} cn31xx;
1214 	struct cvmx_pow_wq_int_thrx_s cn38xx;
1215 	struct cvmx_pow_wq_int_thrx_s cn38xxp2;
1216 	struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
1217 	struct cvmx_pow_wq_int_thrx_cn52xx {
1218 #ifdef __BIG_ENDIAN_BITFIELD
1219 		uint64_t reserved_29_63:35;
1220 		uint64_t tc_en:1;
1221 		uint64_t tc_thr:4;
1222 		uint64_t reserved_21_23:3;
1223 		uint64_t ds_thr:9;
1224 		uint64_t reserved_9_11:3;
1225 		uint64_t iq_thr:9;
1226 #else
1227 		uint64_t iq_thr:9;
1228 		uint64_t reserved_9_11:3;
1229 		uint64_t ds_thr:9;
1230 		uint64_t reserved_21_23:3;
1231 		uint64_t tc_thr:4;
1232 		uint64_t tc_en:1;
1233 		uint64_t reserved_29_63:35;
1234 #endif
1235 	} cn52xx;
1236 	struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
1237 	struct cvmx_pow_wq_int_thrx_s cn56xx;
1238 	struct cvmx_pow_wq_int_thrx_s cn56xxp1;
1239 	struct cvmx_pow_wq_int_thrx_s cn58xx;
1240 	struct cvmx_pow_wq_int_thrx_s cn58xxp1;
1241 	struct cvmx_pow_wq_int_thrx_cn52xx cn61xx;
1242 	struct cvmx_pow_wq_int_thrx_cn63xx {
1243 #ifdef __BIG_ENDIAN_BITFIELD
1244 		uint64_t reserved_29_63:35;
1245 		uint64_t tc_en:1;
1246 		uint64_t tc_thr:4;
1247 		uint64_t reserved_22_23:2;
1248 		uint64_t ds_thr:10;
1249 		uint64_t reserved_10_11:2;
1250 		uint64_t iq_thr:10;
1251 #else
1252 		uint64_t iq_thr:10;
1253 		uint64_t reserved_10_11:2;
1254 		uint64_t ds_thr:10;
1255 		uint64_t reserved_22_23:2;
1256 		uint64_t tc_thr:4;
1257 		uint64_t tc_en:1;
1258 		uint64_t reserved_29_63:35;
1259 #endif
1260 	} cn63xx;
1261 	struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
1262 	struct cvmx_pow_wq_int_thrx_cn63xx cn66xx;
1263 	struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx;
1264 };
1265 
1266 union cvmx_pow_ws_pcx {
1267 	uint64_t u64;
1268 	struct cvmx_pow_ws_pcx_s {
1269 #ifdef __BIG_ENDIAN_BITFIELD
1270 		uint64_t reserved_32_63:32;
1271 		uint64_t ws_pc:32;
1272 #else
1273 		uint64_t ws_pc:32;
1274 		uint64_t reserved_32_63:32;
1275 #endif
1276 	} s;
1277 	struct cvmx_pow_ws_pcx_s cn30xx;
1278 	struct cvmx_pow_ws_pcx_s cn31xx;
1279 	struct cvmx_pow_ws_pcx_s cn38xx;
1280 	struct cvmx_pow_ws_pcx_s cn38xxp2;
1281 	struct cvmx_pow_ws_pcx_s cn50xx;
1282 	struct cvmx_pow_ws_pcx_s cn52xx;
1283 	struct cvmx_pow_ws_pcx_s cn52xxp1;
1284 	struct cvmx_pow_ws_pcx_s cn56xx;
1285 	struct cvmx_pow_ws_pcx_s cn56xxp1;
1286 	struct cvmx_pow_ws_pcx_s cn58xx;
1287 	struct cvmx_pow_ws_pcx_s cn58xxp1;
1288 	struct cvmx_pow_ws_pcx_s cn61xx;
1289 	struct cvmx_pow_ws_pcx_s cn63xx;
1290 	struct cvmx_pow_ws_pcx_s cn63xxp1;
1291 	struct cvmx_pow_ws_pcx_s cn66xx;
1292 	struct cvmx_pow_ws_pcx_s cnf71xx;
1293 };
1294 
1295 union cvmx_sso_wq_int_thrx {
1296 	uint64_t u64;
1297 	struct {
1298 #ifdef __BIG_ENDIAN_BITFIELD
1299 		uint64_t reserved_33_63:31;
1300 		uint64_t tc_en:1;
1301 		uint64_t tc_thr:4;
1302 		uint64_t reserved_26_27:2;
1303 		uint64_t ds_thr:12;
1304 		uint64_t reserved_12_13:2;
1305 		uint64_t iq_thr:12;
1306 #else
1307 		uint64_t iq_thr:12;
1308 		uint64_t reserved_12_13:2;
1309 		uint64_t ds_thr:12;
1310 		uint64_t reserved_26_27:2;
1311 		uint64_t tc_thr:4;
1312 		uint64_t tc_en:1;
1313 		uint64_t reserved_33_63:31;
1314 #endif
1315 	} s;
1316 };
1317 
1318 #endif
1319