1 /***********************license start***************
2  * Author: Cavium Networks
3  *
4  * Contact: support@caviumnetworks.com
5  * This file is part of the OCTEON SDK
6  *
7  * Copyright (c) 2003-2008 Cavium Networks
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more
17  * details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this file; if not, write to the Free Software
21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22  * or visit http://www.gnu.org/licenses/.
23  *
24  * This file may also be available under a different license from Cavium.
25  * Contact Cavium Networks for more information
26  ***********************license end**************************************/
27 
28 #ifndef __CVMX_NPEI_DEFS_H__
29 #define __CVMX_NPEI_DEFS_H__
30 
31 #define CVMX_NPEI_BAR1_INDEXX(offset) \
32 	 (0x0000000000000000ull + (((offset) & 31) * 16))
33 #define CVMX_NPEI_BIST_STATUS \
34 	 (0x0000000000000580ull)
35 #define CVMX_NPEI_BIST_STATUS2 \
36 	 (0x0000000000000680ull)
37 #define CVMX_NPEI_CTL_PORT0 \
38 	 (0x0000000000000250ull)
39 #define CVMX_NPEI_CTL_PORT1 \
40 	 (0x0000000000000260ull)
41 #define CVMX_NPEI_CTL_STATUS \
42 	 (0x0000000000000570ull)
43 #define CVMX_NPEI_CTL_STATUS2 \
44 	 (0x0000000000003C00ull)
45 #define CVMX_NPEI_DATA_OUT_CNT \
46 	 (0x00000000000005F0ull)
47 #define CVMX_NPEI_DBG_DATA \
48 	 (0x0000000000000510ull)
49 #define CVMX_NPEI_DBG_SELECT \
50 	 (0x0000000000000500ull)
51 #define CVMX_NPEI_DMA0_INT_LEVEL \
52 	 (0x00000000000005C0ull)
53 #define CVMX_NPEI_DMA1_INT_LEVEL \
54 	 (0x00000000000005D0ull)
55 #define CVMX_NPEI_DMAX_COUNTS(offset) \
56 	 (0x0000000000000450ull + (((offset) & 7) * 16))
57 #define CVMX_NPEI_DMAX_DBELL(offset) \
58 	 (0x00000000000003B0ull + (((offset) & 7) * 16))
59 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
60 	 (0x0000000000000400ull + (((offset) & 7) * 16))
61 #define CVMX_NPEI_DMAX_NADDR(offset) \
62 	 (0x00000000000004A0ull + (((offset) & 7) * 16))
63 #define CVMX_NPEI_DMA_CNTS \
64 	 (0x00000000000005E0ull)
65 #define CVMX_NPEI_DMA_CONTROL \
66 	 (0x00000000000003A0ull)
67 #define CVMX_NPEI_INT_A_ENB \
68 	 (0x0000000000000560ull)
69 #define CVMX_NPEI_INT_A_ENB2 \
70 	 (0x0000000000003CE0ull)
71 #define CVMX_NPEI_INT_A_SUM \
72 	 (0x0000000000000550ull)
73 #define CVMX_NPEI_INT_ENB \
74 	 (0x0000000000000540ull)
75 #define CVMX_NPEI_INT_ENB2 \
76 	 (0x0000000000003CD0ull)
77 #define CVMX_NPEI_INT_INFO \
78 	 (0x0000000000000590ull)
79 #define CVMX_NPEI_INT_SUM \
80 	 (0x0000000000000530ull)
81 #define CVMX_NPEI_INT_SUM2 \
82 	 (0x0000000000003CC0ull)
83 #define CVMX_NPEI_LAST_WIN_RDATA0 \
84 	 (0x0000000000000600ull)
85 #define CVMX_NPEI_LAST_WIN_RDATA1 \
86 	 (0x0000000000000610ull)
87 #define CVMX_NPEI_MEM_ACCESS_CTL \
88 	 (0x00000000000004F0ull)
89 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
90 	 (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
91 #define CVMX_NPEI_MSI_ENB0 \
92 	 (0x0000000000003C50ull)
93 #define CVMX_NPEI_MSI_ENB1 \
94 	 (0x0000000000003C60ull)
95 #define CVMX_NPEI_MSI_ENB2 \
96 	 (0x0000000000003C70ull)
97 #define CVMX_NPEI_MSI_ENB3 \
98 	 (0x0000000000003C80ull)
99 #define CVMX_NPEI_MSI_RCV0 \
100 	 (0x0000000000003C10ull)
101 #define CVMX_NPEI_MSI_RCV1 \
102 	 (0x0000000000003C20ull)
103 #define CVMX_NPEI_MSI_RCV2 \
104 	 (0x0000000000003C30ull)
105 #define CVMX_NPEI_MSI_RCV3 \
106 	 (0x0000000000003C40ull)
107 #define CVMX_NPEI_MSI_RD_MAP \
108 	 (0x0000000000003CA0ull)
109 #define CVMX_NPEI_MSI_W1C_ENB0 \
110 	 (0x0000000000003CF0ull)
111 #define CVMX_NPEI_MSI_W1C_ENB1 \
112 	 (0x0000000000003D00ull)
113 #define CVMX_NPEI_MSI_W1C_ENB2 \
114 	 (0x0000000000003D10ull)
115 #define CVMX_NPEI_MSI_W1C_ENB3 \
116 	 (0x0000000000003D20ull)
117 #define CVMX_NPEI_MSI_W1S_ENB0 \
118 	 (0x0000000000003D30ull)
119 #define CVMX_NPEI_MSI_W1S_ENB1 \
120 	 (0x0000000000003D40ull)
121 #define CVMX_NPEI_MSI_W1S_ENB2 \
122 	 (0x0000000000003D50ull)
123 #define CVMX_NPEI_MSI_W1S_ENB3 \
124 	 (0x0000000000003D60ull)
125 #define CVMX_NPEI_MSI_WR_MAP \
126 	 (0x0000000000003C90ull)
127 #define CVMX_NPEI_PCIE_CREDIT_CNT \
128 	 (0x0000000000003D70ull)
129 #define CVMX_NPEI_PCIE_MSI_RCV \
130 	 (0x0000000000003CB0ull)
131 #define CVMX_NPEI_PCIE_MSI_RCV_B1 \
132 	 (0x0000000000000650ull)
133 #define CVMX_NPEI_PCIE_MSI_RCV_B2 \
134 	 (0x0000000000000660ull)
135 #define CVMX_NPEI_PCIE_MSI_RCV_B3 \
136 	 (0x0000000000000670ull)
137 #define CVMX_NPEI_PKTX_CNTS(offset) \
138 	 (0x0000000000002400ull + (((offset) & 31) * 16))
139 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
140 	 (0x0000000000002800ull + (((offset) & 31) * 16))
141 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
142 	 (0x0000000000002C00ull + (((offset) & 31) * 16))
143 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
144 	 (0x0000000000003000ull + (((offset) & 31) * 16))
145 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
146 	 (0x0000000000003400ull + (((offset) & 31) * 16))
147 #define CVMX_NPEI_PKTX_IN_BP(offset) \
148 	 (0x0000000000003800ull + (((offset) & 31) * 16))
149 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
150 	 (0x0000000000001400ull + (((offset) & 31) * 16))
151 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
152 	 (0x0000000000001800ull + (((offset) & 31) * 16))
153 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
154 	 (0x0000000000001C00ull + (((offset) & 31) * 16))
155 #define CVMX_NPEI_PKT_CNT_INT \
156 	 (0x0000000000001110ull)
157 #define CVMX_NPEI_PKT_CNT_INT_ENB \
158 	 (0x0000000000001130ull)
159 #define CVMX_NPEI_PKT_DATA_OUT_ES \
160 	 (0x00000000000010B0ull)
161 #define CVMX_NPEI_PKT_DATA_OUT_NS \
162 	 (0x00000000000010A0ull)
163 #define CVMX_NPEI_PKT_DATA_OUT_ROR \
164 	 (0x0000000000001090ull)
165 #define CVMX_NPEI_PKT_DPADDR \
166 	 (0x0000000000001080ull)
167 #define CVMX_NPEI_PKT_INPUT_CONTROL \
168 	 (0x0000000000001150ull)
169 #define CVMX_NPEI_PKT_INSTR_ENB \
170 	 (0x0000000000001000ull)
171 #define CVMX_NPEI_PKT_INSTR_RD_SIZE \
172 	 (0x0000000000001190ull)
173 #define CVMX_NPEI_PKT_INSTR_SIZE \
174 	 (0x0000000000001020ull)
175 #define CVMX_NPEI_PKT_INT_LEVELS \
176 	 (0x0000000000001100ull)
177 #define CVMX_NPEI_PKT_IN_BP \
178 	 (0x00000000000006B0ull)
179 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
180 	 (0x0000000000002000ull + (((offset) & 31) * 16))
181 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
182 	 (0x00000000000006A0ull)
183 #define CVMX_NPEI_PKT_IN_PCIE_PORT \
184 	 (0x00000000000011A0ull)
185 #define CVMX_NPEI_PKT_IPTR \
186 	 (0x0000000000001070ull)
187 #define CVMX_NPEI_PKT_OUTPUT_WMARK \
188 	 (0x0000000000001160ull)
189 #define CVMX_NPEI_PKT_OUT_BMODE \
190 	 (0x00000000000010D0ull)
191 #define CVMX_NPEI_PKT_OUT_ENB \
192 	 (0x0000000000001010ull)
193 #define CVMX_NPEI_PKT_PCIE_PORT \
194 	 (0x00000000000010E0ull)
195 #define CVMX_NPEI_PKT_PORT_IN_RST \
196 	 (0x0000000000000690ull)
197 #define CVMX_NPEI_PKT_SLIST_ES \
198 	 (0x0000000000001050ull)
199 #define CVMX_NPEI_PKT_SLIST_ID_SIZE \
200 	 (0x0000000000001180ull)
201 #define CVMX_NPEI_PKT_SLIST_NS \
202 	 (0x0000000000001040ull)
203 #define CVMX_NPEI_PKT_SLIST_ROR \
204 	 (0x0000000000001030ull)
205 #define CVMX_NPEI_PKT_TIME_INT \
206 	 (0x0000000000001120ull)
207 #define CVMX_NPEI_PKT_TIME_INT_ENB \
208 	 (0x0000000000001140ull)
209 #define CVMX_NPEI_RSL_INT_BLOCKS \
210 	 (0x0000000000000520ull)
211 #define CVMX_NPEI_SCRATCH_1 \
212 	 (0x0000000000000270ull)
213 #define CVMX_NPEI_STATE1 \
214 	 (0x0000000000000620ull)
215 #define CVMX_NPEI_STATE2 \
216 	 (0x0000000000000630ull)
217 #define CVMX_NPEI_STATE3 \
218 	 (0x0000000000000640ull)
219 #define CVMX_NPEI_WINDOW_CTL \
220 	 (0x0000000000000380ull)
221 #define CVMX_NPEI_WIN_RD_ADDR \
222 	 (0x0000000000000210ull)
223 #define CVMX_NPEI_WIN_RD_DATA \
224 	 (0x0000000000000240ull)
225 #define CVMX_NPEI_WIN_WR_ADDR \
226 	 (0x0000000000000200ull)
227 #define CVMX_NPEI_WIN_WR_DATA \
228 	 (0x0000000000000220ull)
229 #define CVMX_NPEI_WIN_WR_MASK \
230 	 (0x0000000000000230ull)
231 
232 union cvmx_npei_bar1_indexx {
233 	uint32_t u32;
234 	struct cvmx_npei_bar1_indexx_s {
235 		uint32_t reserved_18_31:14;
236 		uint32_t addr_idx:14;
237 		uint32_t ca:1;
238 		uint32_t end_swp:2;
239 		uint32_t addr_v:1;
240 	} s;
241 	struct cvmx_npei_bar1_indexx_s cn52xx;
242 	struct cvmx_npei_bar1_indexx_s cn52xxp1;
243 	struct cvmx_npei_bar1_indexx_s cn56xx;
244 	struct cvmx_npei_bar1_indexx_s cn56xxp1;
245 };
246 
247 union cvmx_npei_bist_status {
248 	uint64_t u64;
249 	struct cvmx_npei_bist_status_s {
250 		uint64_t pkt_rdf:1;
251 		uint64_t pkt_pmem:1;
252 		uint64_t pkt_p1:1;
253 		uint64_t reserved_60_60:1;
254 		uint64_t pcr_gim:1;
255 		uint64_t pkt_pif:1;
256 		uint64_t pcsr_int:1;
257 		uint64_t pcsr_im:1;
258 		uint64_t pcsr_cnt:1;
259 		uint64_t pcsr_id:1;
260 		uint64_t pcsr_sl:1;
261 		uint64_t reserved_50_52:3;
262 		uint64_t pkt_ind:1;
263 		uint64_t pkt_slm:1;
264 		uint64_t reserved_36_47:12;
265 		uint64_t d0_pst:1;
266 		uint64_t d1_pst:1;
267 		uint64_t d2_pst:1;
268 		uint64_t d3_pst:1;
269 		uint64_t reserved_31_31:1;
270 		uint64_t n2p0_c:1;
271 		uint64_t n2p0_o:1;
272 		uint64_t n2p1_c:1;
273 		uint64_t n2p1_o:1;
274 		uint64_t cpl_p0:1;
275 		uint64_t cpl_p1:1;
276 		uint64_t p2n1_po:1;
277 		uint64_t p2n1_no:1;
278 		uint64_t p2n1_co:1;
279 		uint64_t p2n0_po:1;
280 		uint64_t p2n0_no:1;
281 		uint64_t p2n0_co:1;
282 		uint64_t p2n0_c0:1;
283 		uint64_t p2n0_c1:1;
284 		uint64_t p2n0_n:1;
285 		uint64_t p2n0_p0:1;
286 		uint64_t p2n0_p1:1;
287 		uint64_t p2n1_c0:1;
288 		uint64_t p2n1_c1:1;
289 		uint64_t p2n1_n:1;
290 		uint64_t p2n1_p0:1;
291 		uint64_t p2n1_p1:1;
292 		uint64_t csm0:1;
293 		uint64_t csm1:1;
294 		uint64_t dif0:1;
295 		uint64_t dif1:1;
296 		uint64_t dif2:1;
297 		uint64_t dif3:1;
298 		uint64_t reserved_2_2:1;
299 		uint64_t msi:1;
300 		uint64_t ncb_cmd:1;
301 	} s;
302 	struct cvmx_npei_bist_status_cn52xx {
303 		uint64_t pkt_rdf:1;
304 		uint64_t pkt_pmem:1;
305 		uint64_t pkt_p1:1;
306 		uint64_t reserved_60_60:1;
307 		uint64_t pcr_gim:1;
308 		uint64_t pkt_pif:1;
309 		uint64_t pcsr_int:1;
310 		uint64_t pcsr_im:1;
311 		uint64_t pcsr_cnt:1;
312 		uint64_t pcsr_id:1;
313 		uint64_t pcsr_sl:1;
314 		uint64_t pkt_imem:1;
315 		uint64_t pkt_pfm:1;
316 		uint64_t pkt_pof:1;
317 		uint64_t reserved_48_49:2;
318 		uint64_t pkt_pop0:1;
319 		uint64_t pkt_pop1:1;
320 		uint64_t d0_mem:1;
321 		uint64_t d1_mem:1;
322 		uint64_t d2_mem:1;
323 		uint64_t d3_mem:1;
324 		uint64_t d4_mem:1;
325 		uint64_t ds_mem:1;
326 		uint64_t reserved_36_39:4;
327 		uint64_t d0_pst:1;
328 		uint64_t d1_pst:1;
329 		uint64_t d2_pst:1;
330 		uint64_t d3_pst:1;
331 		uint64_t d4_pst:1;
332 		uint64_t n2p0_c:1;
333 		uint64_t n2p0_o:1;
334 		uint64_t n2p1_c:1;
335 		uint64_t n2p1_o:1;
336 		uint64_t cpl_p0:1;
337 		uint64_t cpl_p1:1;
338 		uint64_t p2n1_po:1;
339 		uint64_t p2n1_no:1;
340 		uint64_t p2n1_co:1;
341 		uint64_t p2n0_po:1;
342 		uint64_t p2n0_no:1;
343 		uint64_t p2n0_co:1;
344 		uint64_t p2n0_c0:1;
345 		uint64_t p2n0_c1:1;
346 		uint64_t p2n0_n:1;
347 		uint64_t p2n0_p0:1;
348 		uint64_t p2n0_p1:1;
349 		uint64_t p2n1_c0:1;
350 		uint64_t p2n1_c1:1;
351 		uint64_t p2n1_n:1;
352 		uint64_t p2n1_p0:1;
353 		uint64_t p2n1_p1:1;
354 		uint64_t csm0:1;
355 		uint64_t csm1:1;
356 		uint64_t dif0:1;
357 		uint64_t dif1:1;
358 		uint64_t dif2:1;
359 		uint64_t dif3:1;
360 		uint64_t dif4:1;
361 		uint64_t msi:1;
362 		uint64_t ncb_cmd:1;
363 	} cn52xx;
364 	struct cvmx_npei_bist_status_cn52xxp1 {
365 		uint64_t reserved_46_63:18;
366 		uint64_t d0_mem0:1;
367 		uint64_t d1_mem1:1;
368 		uint64_t d2_mem2:1;
369 		uint64_t d3_mem3:1;
370 		uint64_t dr0_mem:1;
371 		uint64_t d0_mem:1;
372 		uint64_t d1_mem:1;
373 		uint64_t d2_mem:1;
374 		uint64_t d3_mem:1;
375 		uint64_t dr1_mem:1;
376 		uint64_t d0_pst:1;
377 		uint64_t d1_pst:1;
378 		uint64_t d2_pst:1;
379 		uint64_t d3_pst:1;
380 		uint64_t dr2_mem:1;
381 		uint64_t n2p0_c:1;
382 		uint64_t n2p0_o:1;
383 		uint64_t n2p1_c:1;
384 		uint64_t n2p1_o:1;
385 		uint64_t cpl_p0:1;
386 		uint64_t cpl_p1:1;
387 		uint64_t p2n1_po:1;
388 		uint64_t p2n1_no:1;
389 		uint64_t p2n1_co:1;
390 		uint64_t p2n0_po:1;
391 		uint64_t p2n0_no:1;
392 		uint64_t p2n0_co:1;
393 		uint64_t p2n0_c0:1;
394 		uint64_t p2n0_c1:1;
395 		uint64_t p2n0_n:1;
396 		uint64_t p2n0_p0:1;
397 		uint64_t p2n0_p1:1;
398 		uint64_t p2n1_c0:1;
399 		uint64_t p2n1_c1:1;
400 		uint64_t p2n1_n:1;
401 		uint64_t p2n1_p0:1;
402 		uint64_t p2n1_p1:1;
403 		uint64_t csm0:1;
404 		uint64_t csm1:1;
405 		uint64_t dif0:1;
406 		uint64_t dif1:1;
407 		uint64_t dif2:1;
408 		uint64_t dif3:1;
409 		uint64_t dr3_mem:1;
410 		uint64_t msi:1;
411 		uint64_t ncb_cmd:1;
412 	} cn52xxp1;
413 	struct cvmx_npei_bist_status_cn56xx {
414 		uint64_t pkt_rdf:1;
415 		uint64_t reserved_60_62:3;
416 		uint64_t pcr_gim:1;
417 		uint64_t pkt_pif:1;
418 		uint64_t pcsr_int:1;
419 		uint64_t pcsr_im:1;
420 		uint64_t pcsr_cnt:1;
421 		uint64_t pcsr_id:1;
422 		uint64_t pcsr_sl:1;
423 		uint64_t pkt_imem:1;
424 		uint64_t pkt_pfm:1;
425 		uint64_t pkt_pof:1;
426 		uint64_t reserved_48_49:2;
427 		uint64_t pkt_pop0:1;
428 		uint64_t pkt_pop1:1;
429 		uint64_t d0_mem:1;
430 		uint64_t d1_mem:1;
431 		uint64_t d2_mem:1;
432 		uint64_t d3_mem:1;
433 		uint64_t d4_mem:1;
434 		uint64_t ds_mem:1;
435 		uint64_t reserved_36_39:4;
436 		uint64_t d0_pst:1;
437 		uint64_t d1_pst:1;
438 		uint64_t d2_pst:1;
439 		uint64_t d3_pst:1;
440 		uint64_t d4_pst:1;
441 		uint64_t n2p0_c:1;
442 		uint64_t n2p0_o:1;
443 		uint64_t n2p1_c:1;
444 		uint64_t n2p1_o:1;
445 		uint64_t cpl_p0:1;
446 		uint64_t cpl_p1:1;
447 		uint64_t p2n1_po:1;
448 		uint64_t p2n1_no:1;
449 		uint64_t p2n1_co:1;
450 		uint64_t p2n0_po:1;
451 		uint64_t p2n0_no:1;
452 		uint64_t p2n0_co:1;
453 		uint64_t p2n0_c0:1;
454 		uint64_t p2n0_c1:1;
455 		uint64_t p2n0_n:1;
456 		uint64_t p2n0_p0:1;
457 		uint64_t p2n0_p1:1;
458 		uint64_t p2n1_c0:1;
459 		uint64_t p2n1_c1:1;
460 		uint64_t p2n1_n:1;
461 		uint64_t p2n1_p0:1;
462 		uint64_t p2n1_p1:1;
463 		uint64_t csm0:1;
464 		uint64_t csm1:1;
465 		uint64_t dif0:1;
466 		uint64_t dif1:1;
467 		uint64_t dif2:1;
468 		uint64_t dif3:1;
469 		uint64_t dif4:1;
470 		uint64_t msi:1;
471 		uint64_t ncb_cmd:1;
472 	} cn56xx;
473 	struct cvmx_npei_bist_status_cn56xxp1 {
474 		uint64_t reserved_58_63:6;
475 		uint64_t pcsr_int:1;
476 		uint64_t pcsr_im:1;
477 		uint64_t pcsr_cnt:1;
478 		uint64_t pcsr_id:1;
479 		uint64_t pcsr_sl:1;
480 		uint64_t pkt_pout:1;
481 		uint64_t pkt_imem:1;
482 		uint64_t pkt_cntm:1;
483 		uint64_t pkt_ind:1;
484 		uint64_t pkt_slm:1;
485 		uint64_t pkt_odf:1;
486 		uint64_t pkt_oif:1;
487 		uint64_t pkt_out:1;
488 		uint64_t pkt_i0:1;
489 		uint64_t pkt_i1:1;
490 		uint64_t pkt_s0:1;
491 		uint64_t pkt_s1:1;
492 		uint64_t d0_mem:1;
493 		uint64_t d1_mem:1;
494 		uint64_t d2_mem:1;
495 		uint64_t d3_mem:1;
496 		uint64_t d4_mem:1;
497 		uint64_t d0_pst:1;
498 		uint64_t d1_pst:1;
499 		uint64_t d2_pst:1;
500 		uint64_t d3_pst:1;
501 		uint64_t d4_pst:1;
502 		uint64_t n2p0_c:1;
503 		uint64_t n2p0_o:1;
504 		uint64_t n2p1_c:1;
505 		uint64_t n2p1_o:1;
506 		uint64_t cpl_p0:1;
507 		uint64_t cpl_p1:1;
508 		uint64_t p2n1_po:1;
509 		uint64_t p2n1_no:1;
510 		uint64_t p2n1_co:1;
511 		uint64_t p2n0_po:1;
512 		uint64_t p2n0_no:1;
513 		uint64_t p2n0_co:1;
514 		uint64_t p2n0_c0:1;
515 		uint64_t p2n0_c1:1;
516 		uint64_t p2n0_n:1;
517 		uint64_t p2n0_p0:1;
518 		uint64_t p2n0_p1:1;
519 		uint64_t p2n1_c0:1;
520 		uint64_t p2n1_c1:1;
521 		uint64_t p2n1_n:1;
522 		uint64_t p2n1_p0:1;
523 		uint64_t p2n1_p1:1;
524 		uint64_t csm0:1;
525 		uint64_t csm1:1;
526 		uint64_t dif0:1;
527 		uint64_t dif1:1;
528 		uint64_t dif2:1;
529 		uint64_t dif3:1;
530 		uint64_t dif4:1;
531 		uint64_t msi:1;
532 		uint64_t ncb_cmd:1;
533 	} cn56xxp1;
534 };
535 
536 union cvmx_npei_bist_status2 {
537 	uint64_t u64;
538 	struct cvmx_npei_bist_status2_s {
539 		uint64_t reserved_5_63:59;
540 		uint64_t psc_p0:1;
541 		uint64_t psc_p1:1;
542 		uint64_t pkt_gd:1;
543 		uint64_t pkt_gl:1;
544 		uint64_t pkt_blk:1;
545 	} s;
546 	struct cvmx_npei_bist_status2_s cn52xx;
547 	struct cvmx_npei_bist_status2_s cn56xx;
548 };
549 
550 union cvmx_npei_ctl_port0 {
551 	uint64_t u64;
552 	struct cvmx_npei_ctl_port0_s {
553 		uint64_t reserved_21_63:43;
554 		uint64_t waitl_com:1;
555 		uint64_t intd:1;
556 		uint64_t intc:1;
557 		uint64_t intb:1;
558 		uint64_t inta:1;
559 		uint64_t intd_map:2;
560 		uint64_t intc_map:2;
561 		uint64_t intb_map:2;
562 		uint64_t inta_map:2;
563 		uint64_t ctlp_ro:1;
564 		uint64_t reserved_6_6:1;
565 		uint64_t ptlp_ro:1;
566 		uint64_t bar2_enb:1;
567 		uint64_t bar2_esx:2;
568 		uint64_t bar2_cax:1;
569 		uint64_t wait_com:1;
570 	} s;
571 	struct cvmx_npei_ctl_port0_s cn52xx;
572 	struct cvmx_npei_ctl_port0_s cn52xxp1;
573 	struct cvmx_npei_ctl_port0_s cn56xx;
574 	struct cvmx_npei_ctl_port0_s cn56xxp1;
575 };
576 
577 union cvmx_npei_ctl_port1 {
578 	uint64_t u64;
579 	struct cvmx_npei_ctl_port1_s {
580 		uint64_t reserved_21_63:43;
581 		uint64_t waitl_com:1;
582 		uint64_t intd:1;
583 		uint64_t intc:1;
584 		uint64_t intb:1;
585 		uint64_t inta:1;
586 		uint64_t intd_map:2;
587 		uint64_t intc_map:2;
588 		uint64_t intb_map:2;
589 		uint64_t inta_map:2;
590 		uint64_t ctlp_ro:1;
591 		uint64_t reserved_6_6:1;
592 		uint64_t ptlp_ro:1;
593 		uint64_t bar2_enb:1;
594 		uint64_t bar2_esx:2;
595 		uint64_t bar2_cax:1;
596 		uint64_t wait_com:1;
597 	} s;
598 	struct cvmx_npei_ctl_port1_s cn52xx;
599 	struct cvmx_npei_ctl_port1_s cn52xxp1;
600 	struct cvmx_npei_ctl_port1_s cn56xx;
601 	struct cvmx_npei_ctl_port1_s cn56xxp1;
602 };
603 
604 union cvmx_npei_ctl_status {
605 	uint64_t u64;
606 	struct cvmx_npei_ctl_status_s {
607 		uint64_t reserved_44_63:20;
608 		uint64_t p1_ntags:6;
609 		uint64_t p0_ntags:6;
610 		uint64_t cfg_rtry:16;
611 		uint64_t ring_en:1;
612 		uint64_t lnk_rst:1;
613 		uint64_t arb:1;
614 		uint64_t pkt_bp:4;
615 		uint64_t host_mode:1;
616 		uint64_t chip_rev:8;
617 	} s;
618 	struct cvmx_npei_ctl_status_s cn52xx;
619 	struct cvmx_npei_ctl_status_cn52xxp1 {
620 		uint64_t reserved_44_63:20;
621 		uint64_t p1_ntags:6;
622 		uint64_t p0_ntags:6;
623 		uint64_t cfg_rtry:16;
624 		uint64_t reserved_15_15:1;
625 		uint64_t lnk_rst:1;
626 		uint64_t arb:1;
627 		uint64_t reserved_9_12:4;
628 		uint64_t host_mode:1;
629 		uint64_t chip_rev:8;
630 	} cn52xxp1;
631 	struct cvmx_npei_ctl_status_s cn56xx;
632 	struct cvmx_npei_ctl_status_cn56xxp1 {
633 		uint64_t reserved_16_63:48;
634 		uint64_t ring_en:1;
635 		uint64_t lnk_rst:1;
636 		uint64_t arb:1;
637 		uint64_t pkt_bp:4;
638 		uint64_t host_mode:1;
639 		uint64_t chip_rev:8;
640 	} cn56xxp1;
641 };
642 
643 union cvmx_npei_ctl_status2 {
644 	uint64_t u64;
645 	struct cvmx_npei_ctl_status2_s {
646 		uint64_t reserved_16_63:48;
647 		uint64_t mps:1;
648 		uint64_t mrrs:3;
649 		uint64_t c1_w_flt:1;
650 		uint64_t c0_w_flt:1;
651 		uint64_t c1_b1_s:3;
652 		uint64_t c0_b1_s:3;
653 		uint64_t c1_wi_d:1;
654 		uint64_t c1_b0_d:1;
655 		uint64_t c0_wi_d:1;
656 		uint64_t c0_b0_d:1;
657 	} s;
658 	struct cvmx_npei_ctl_status2_s cn52xx;
659 	struct cvmx_npei_ctl_status2_s cn52xxp1;
660 	struct cvmx_npei_ctl_status2_s cn56xx;
661 	struct cvmx_npei_ctl_status2_s cn56xxp1;
662 };
663 
664 union cvmx_npei_data_out_cnt {
665 	uint64_t u64;
666 	struct cvmx_npei_data_out_cnt_s {
667 		uint64_t reserved_44_63:20;
668 		uint64_t p1_ucnt:16;
669 		uint64_t p1_fcnt:6;
670 		uint64_t p0_ucnt:16;
671 		uint64_t p0_fcnt:6;
672 	} s;
673 	struct cvmx_npei_data_out_cnt_s cn52xx;
674 	struct cvmx_npei_data_out_cnt_s cn52xxp1;
675 	struct cvmx_npei_data_out_cnt_s cn56xx;
676 	struct cvmx_npei_data_out_cnt_s cn56xxp1;
677 };
678 
679 union cvmx_npei_dbg_data {
680 	uint64_t u64;
681 	struct cvmx_npei_dbg_data_s {
682 		uint64_t reserved_28_63:36;
683 		uint64_t qlm0_rev_lanes:1;
684 		uint64_t reserved_25_26:2;
685 		uint64_t qlm1_spd:2;
686 		uint64_t c_mul:5;
687 		uint64_t dsel_ext:1;
688 		uint64_t data:17;
689 	} s;
690 	struct cvmx_npei_dbg_data_cn52xx {
691 		uint64_t reserved_29_63:35;
692 		uint64_t qlm0_link_width:1;
693 		uint64_t qlm0_rev_lanes:1;
694 		uint64_t qlm1_mode:2;
695 		uint64_t qlm1_spd:2;
696 		uint64_t c_mul:5;
697 		uint64_t dsel_ext:1;
698 		uint64_t data:17;
699 	} cn52xx;
700 	struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
701 	struct cvmx_npei_dbg_data_cn56xx {
702 		uint64_t reserved_29_63:35;
703 		uint64_t qlm2_rev_lanes:1;
704 		uint64_t qlm0_rev_lanes:1;
705 		uint64_t qlm3_spd:2;
706 		uint64_t qlm1_spd:2;
707 		uint64_t c_mul:5;
708 		uint64_t dsel_ext:1;
709 		uint64_t data:17;
710 	} cn56xx;
711 	struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
712 };
713 
714 union cvmx_npei_dbg_select {
715 	uint64_t u64;
716 	struct cvmx_npei_dbg_select_s {
717 		uint64_t reserved_16_63:48;
718 		uint64_t dbg_sel:16;
719 	} s;
720 	struct cvmx_npei_dbg_select_s cn52xx;
721 	struct cvmx_npei_dbg_select_s cn52xxp1;
722 	struct cvmx_npei_dbg_select_s cn56xx;
723 	struct cvmx_npei_dbg_select_s cn56xxp1;
724 };
725 
726 union cvmx_npei_dmax_counts {
727 	uint64_t u64;
728 	struct cvmx_npei_dmax_counts_s {
729 		uint64_t reserved_39_63:25;
730 		uint64_t fcnt:7;
731 		uint64_t dbell:32;
732 	} s;
733 	struct cvmx_npei_dmax_counts_s cn52xx;
734 	struct cvmx_npei_dmax_counts_s cn52xxp1;
735 	struct cvmx_npei_dmax_counts_s cn56xx;
736 	struct cvmx_npei_dmax_counts_s cn56xxp1;
737 };
738 
739 union cvmx_npei_dmax_dbell {
740 	uint32_t u32;
741 	struct cvmx_npei_dmax_dbell_s {
742 		uint32_t reserved_16_31:16;
743 		uint32_t dbell:16;
744 	} s;
745 	struct cvmx_npei_dmax_dbell_s cn52xx;
746 	struct cvmx_npei_dmax_dbell_s cn52xxp1;
747 	struct cvmx_npei_dmax_dbell_s cn56xx;
748 	struct cvmx_npei_dmax_dbell_s cn56xxp1;
749 };
750 
751 union cvmx_npei_dmax_ibuff_saddr {
752 	uint64_t u64;
753 	struct cvmx_npei_dmax_ibuff_saddr_s {
754 		uint64_t reserved_37_63:27;
755 		uint64_t idle:1;
756 		uint64_t saddr:29;
757 		uint64_t reserved_0_6:7;
758 	} s;
759 	struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
760 		uint64_t reserved_36_63:28;
761 		uint64_t saddr:29;
762 		uint64_t reserved_0_6:7;
763 	} cn52xx;
764 	struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
765 	struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
766 	struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
767 };
768 
769 union cvmx_npei_dmax_naddr {
770 	uint64_t u64;
771 	struct cvmx_npei_dmax_naddr_s {
772 		uint64_t reserved_36_63:28;
773 		uint64_t addr:36;
774 	} s;
775 	struct cvmx_npei_dmax_naddr_s cn52xx;
776 	struct cvmx_npei_dmax_naddr_s cn52xxp1;
777 	struct cvmx_npei_dmax_naddr_s cn56xx;
778 	struct cvmx_npei_dmax_naddr_s cn56xxp1;
779 };
780 
781 union cvmx_npei_dma0_int_level {
782 	uint64_t u64;
783 	struct cvmx_npei_dma0_int_level_s {
784 		uint64_t time:32;
785 		uint64_t cnt:32;
786 	} s;
787 	struct cvmx_npei_dma0_int_level_s cn52xx;
788 	struct cvmx_npei_dma0_int_level_s cn52xxp1;
789 	struct cvmx_npei_dma0_int_level_s cn56xx;
790 	struct cvmx_npei_dma0_int_level_s cn56xxp1;
791 };
792 
793 union cvmx_npei_dma1_int_level {
794 	uint64_t u64;
795 	struct cvmx_npei_dma1_int_level_s {
796 		uint64_t time:32;
797 		uint64_t cnt:32;
798 	} s;
799 	struct cvmx_npei_dma1_int_level_s cn52xx;
800 	struct cvmx_npei_dma1_int_level_s cn52xxp1;
801 	struct cvmx_npei_dma1_int_level_s cn56xx;
802 	struct cvmx_npei_dma1_int_level_s cn56xxp1;
803 };
804 
805 union cvmx_npei_dma_cnts {
806 	uint64_t u64;
807 	struct cvmx_npei_dma_cnts_s {
808 		uint64_t dma1:32;
809 		uint64_t dma0:32;
810 	} s;
811 	struct cvmx_npei_dma_cnts_s cn52xx;
812 	struct cvmx_npei_dma_cnts_s cn52xxp1;
813 	struct cvmx_npei_dma_cnts_s cn56xx;
814 	struct cvmx_npei_dma_cnts_s cn56xxp1;
815 };
816 
817 union cvmx_npei_dma_control {
818 	uint64_t u64;
819 	struct cvmx_npei_dma_control_s {
820 		uint64_t reserved_39_63:25;
821 		uint64_t dma4_enb:1;
822 		uint64_t dma3_enb:1;
823 		uint64_t dma2_enb:1;
824 		uint64_t dma1_enb:1;
825 		uint64_t dma0_enb:1;
826 		uint64_t b0_lend:1;
827 		uint64_t dwb_denb:1;
828 		uint64_t dwb_ichk:9;
829 		uint64_t fpa_que:3;
830 		uint64_t o_add1:1;
831 		uint64_t o_ro:1;
832 		uint64_t o_ns:1;
833 		uint64_t o_es:2;
834 		uint64_t o_mode:1;
835 		uint64_t csize:14;
836 	} s;
837 	struct cvmx_npei_dma_control_s cn52xx;
838 	struct cvmx_npei_dma_control_cn52xxp1 {
839 		uint64_t reserved_38_63:26;
840 		uint64_t dma3_enb:1;
841 		uint64_t dma2_enb:1;
842 		uint64_t dma1_enb:1;
843 		uint64_t dma0_enb:1;
844 		uint64_t b0_lend:1;
845 		uint64_t dwb_denb:1;
846 		uint64_t dwb_ichk:9;
847 		uint64_t fpa_que:3;
848 		uint64_t o_add1:1;
849 		uint64_t o_ro:1;
850 		uint64_t o_ns:1;
851 		uint64_t o_es:2;
852 		uint64_t o_mode:1;
853 		uint64_t csize:14;
854 	} cn52xxp1;
855 	struct cvmx_npei_dma_control_s cn56xx;
856 	struct cvmx_npei_dma_control_s cn56xxp1;
857 };
858 
859 union cvmx_npei_int_a_enb {
860 	uint64_t u64;
861 	struct cvmx_npei_int_a_enb_s {
862 		uint64_t reserved_10_63:54;
863 		uint64_t pout_err:1;
864 		uint64_t pin_bp:1;
865 		uint64_t p1_rdlk:1;
866 		uint64_t p0_rdlk:1;
867 		uint64_t pgl_err:1;
868 		uint64_t pdi_err:1;
869 		uint64_t pop_err:1;
870 		uint64_t pins_err:1;
871 		uint64_t dma1_cpl:1;
872 		uint64_t dma0_cpl:1;
873 	} s;
874 	struct cvmx_npei_int_a_enb_cn52xx {
875 		uint64_t reserved_8_63:56;
876 		uint64_t p1_rdlk:1;
877 		uint64_t p0_rdlk:1;
878 		uint64_t pgl_err:1;
879 		uint64_t pdi_err:1;
880 		uint64_t pop_err:1;
881 		uint64_t pins_err:1;
882 		uint64_t dma1_cpl:1;
883 		uint64_t dma0_cpl:1;
884 	} cn52xx;
885 	struct cvmx_npei_int_a_enb_cn52xxp1 {
886 		uint64_t reserved_2_63:62;
887 		uint64_t dma1_cpl:1;
888 		uint64_t dma0_cpl:1;
889 	} cn52xxp1;
890 	struct cvmx_npei_int_a_enb_s cn56xx;
891 };
892 
893 union cvmx_npei_int_a_enb2 {
894 	uint64_t u64;
895 	struct cvmx_npei_int_a_enb2_s {
896 		uint64_t reserved_10_63:54;
897 		uint64_t pout_err:1;
898 		uint64_t pin_bp:1;
899 		uint64_t p1_rdlk:1;
900 		uint64_t p0_rdlk:1;
901 		uint64_t pgl_err:1;
902 		uint64_t pdi_err:1;
903 		uint64_t pop_err:1;
904 		uint64_t pins_err:1;
905 		uint64_t dma1_cpl:1;
906 		uint64_t dma0_cpl:1;
907 	} s;
908 	struct cvmx_npei_int_a_enb2_cn52xx {
909 		uint64_t reserved_8_63:56;
910 		uint64_t p1_rdlk:1;
911 		uint64_t p0_rdlk:1;
912 		uint64_t pgl_err:1;
913 		uint64_t pdi_err:1;
914 		uint64_t pop_err:1;
915 		uint64_t pins_err:1;
916 		uint64_t reserved_0_1:2;
917 	} cn52xx;
918 	struct cvmx_npei_int_a_enb2_cn52xxp1 {
919 		uint64_t reserved_2_63:62;
920 		uint64_t dma1_cpl:1;
921 		uint64_t dma0_cpl:1;
922 	} cn52xxp1;
923 	struct cvmx_npei_int_a_enb2_s cn56xx;
924 };
925 
926 union cvmx_npei_int_a_sum {
927 	uint64_t u64;
928 	struct cvmx_npei_int_a_sum_s {
929 		uint64_t reserved_10_63:54;
930 		uint64_t pout_err:1;
931 		uint64_t pin_bp:1;
932 		uint64_t p1_rdlk:1;
933 		uint64_t p0_rdlk:1;
934 		uint64_t pgl_err:1;
935 		uint64_t pdi_err:1;
936 		uint64_t pop_err:1;
937 		uint64_t pins_err:1;
938 		uint64_t dma1_cpl:1;
939 		uint64_t dma0_cpl:1;
940 	} s;
941 	struct cvmx_npei_int_a_sum_cn52xx {
942 		uint64_t reserved_8_63:56;
943 		uint64_t p1_rdlk:1;
944 		uint64_t p0_rdlk:1;
945 		uint64_t pgl_err:1;
946 		uint64_t pdi_err:1;
947 		uint64_t pop_err:1;
948 		uint64_t pins_err:1;
949 		uint64_t dma1_cpl:1;
950 		uint64_t dma0_cpl:1;
951 	} cn52xx;
952 	struct cvmx_npei_int_a_sum_cn52xxp1 {
953 		uint64_t reserved_2_63:62;
954 		uint64_t dma1_cpl:1;
955 		uint64_t dma0_cpl:1;
956 	} cn52xxp1;
957 	struct cvmx_npei_int_a_sum_s cn56xx;
958 };
959 
960 union cvmx_npei_int_enb {
961 	uint64_t u64;
962 	struct cvmx_npei_int_enb_s {
963 		uint64_t mio_inta:1;
964 		uint64_t reserved_62_62:1;
965 		uint64_t int_a:1;
966 		uint64_t c1_ldwn:1;
967 		uint64_t c0_ldwn:1;
968 		uint64_t c1_exc:1;
969 		uint64_t c0_exc:1;
970 		uint64_t c1_up_wf:1;
971 		uint64_t c0_up_wf:1;
972 		uint64_t c1_un_wf:1;
973 		uint64_t c0_un_wf:1;
974 		uint64_t c1_un_bx:1;
975 		uint64_t c1_un_wi:1;
976 		uint64_t c1_un_b2:1;
977 		uint64_t c1_un_b1:1;
978 		uint64_t c1_un_b0:1;
979 		uint64_t c1_up_bx:1;
980 		uint64_t c1_up_wi:1;
981 		uint64_t c1_up_b2:1;
982 		uint64_t c1_up_b1:1;
983 		uint64_t c1_up_b0:1;
984 		uint64_t c0_un_bx:1;
985 		uint64_t c0_un_wi:1;
986 		uint64_t c0_un_b2:1;
987 		uint64_t c0_un_b1:1;
988 		uint64_t c0_un_b0:1;
989 		uint64_t c0_up_bx:1;
990 		uint64_t c0_up_wi:1;
991 		uint64_t c0_up_b2:1;
992 		uint64_t c0_up_b1:1;
993 		uint64_t c0_up_b0:1;
994 		uint64_t c1_hpint:1;
995 		uint64_t c1_pmei:1;
996 		uint64_t c1_wake:1;
997 		uint64_t crs1_dr:1;
998 		uint64_t c1_se:1;
999 		uint64_t crs1_er:1;
1000 		uint64_t c1_aeri:1;
1001 		uint64_t c0_hpint:1;
1002 		uint64_t c0_pmei:1;
1003 		uint64_t c0_wake:1;
1004 		uint64_t crs0_dr:1;
1005 		uint64_t c0_se:1;
1006 		uint64_t crs0_er:1;
1007 		uint64_t c0_aeri:1;
1008 		uint64_t ptime:1;
1009 		uint64_t pcnt:1;
1010 		uint64_t pidbof:1;
1011 		uint64_t psldbof:1;
1012 		uint64_t dtime1:1;
1013 		uint64_t dtime0:1;
1014 		uint64_t dcnt1:1;
1015 		uint64_t dcnt0:1;
1016 		uint64_t dma1fi:1;
1017 		uint64_t dma0fi:1;
1018 		uint64_t dma4dbo:1;
1019 		uint64_t dma3dbo:1;
1020 		uint64_t dma2dbo:1;
1021 		uint64_t dma1dbo:1;
1022 		uint64_t dma0dbo:1;
1023 		uint64_t iob2big:1;
1024 		uint64_t bar0_to:1;
1025 		uint64_t rml_wto:1;
1026 		uint64_t rml_rto:1;
1027 	} s;
1028 	struct cvmx_npei_int_enb_s cn52xx;
1029 	struct cvmx_npei_int_enb_cn52xxp1 {
1030 		uint64_t mio_inta:1;
1031 		uint64_t reserved_62_62:1;
1032 		uint64_t int_a:1;
1033 		uint64_t c1_ldwn:1;
1034 		uint64_t c0_ldwn:1;
1035 		uint64_t c1_exc:1;
1036 		uint64_t c0_exc:1;
1037 		uint64_t c1_up_wf:1;
1038 		uint64_t c0_up_wf:1;
1039 		uint64_t c1_un_wf:1;
1040 		uint64_t c0_un_wf:1;
1041 		uint64_t c1_un_bx:1;
1042 		uint64_t c1_un_wi:1;
1043 		uint64_t c1_un_b2:1;
1044 		uint64_t c1_un_b1:1;
1045 		uint64_t c1_un_b0:1;
1046 		uint64_t c1_up_bx:1;
1047 		uint64_t c1_up_wi:1;
1048 		uint64_t c1_up_b2:1;
1049 		uint64_t c1_up_b1:1;
1050 		uint64_t c1_up_b0:1;
1051 		uint64_t c0_un_bx:1;
1052 		uint64_t c0_un_wi:1;
1053 		uint64_t c0_un_b2:1;
1054 		uint64_t c0_un_b1:1;
1055 		uint64_t c0_un_b0:1;
1056 		uint64_t c0_up_bx:1;
1057 		uint64_t c0_up_wi:1;
1058 		uint64_t c0_up_b2:1;
1059 		uint64_t c0_up_b1:1;
1060 		uint64_t c0_up_b0:1;
1061 		uint64_t c1_hpint:1;
1062 		uint64_t c1_pmei:1;
1063 		uint64_t c1_wake:1;
1064 		uint64_t crs1_dr:1;
1065 		uint64_t c1_se:1;
1066 		uint64_t crs1_er:1;
1067 		uint64_t c1_aeri:1;
1068 		uint64_t c0_hpint:1;
1069 		uint64_t c0_pmei:1;
1070 		uint64_t c0_wake:1;
1071 		uint64_t crs0_dr:1;
1072 		uint64_t c0_se:1;
1073 		uint64_t crs0_er:1;
1074 		uint64_t c0_aeri:1;
1075 		uint64_t ptime:1;
1076 		uint64_t pcnt:1;
1077 		uint64_t pidbof:1;
1078 		uint64_t psldbof:1;
1079 		uint64_t dtime1:1;
1080 		uint64_t dtime0:1;
1081 		uint64_t dcnt1:1;
1082 		uint64_t dcnt0:1;
1083 		uint64_t dma1fi:1;
1084 		uint64_t dma0fi:1;
1085 		uint64_t reserved_8_8:1;
1086 		uint64_t dma3dbo:1;
1087 		uint64_t dma2dbo:1;
1088 		uint64_t dma1dbo:1;
1089 		uint64_t dma0dbo:1;
1090 		uint64_t iob2big:1;
1091 		uint64_t bar0_to:1;
1092 		uint64_t rml_wto:1;
1093 		uint64_t rml_rto:1;
1094 	} cn52xxp1;
1095 	struct cvmx_npei_int_enb_s cn56xx;
1096 	struct cvmx_npei_int_enb_cn56xxp1 {
1097 		uint64_t mio_inta:1;
1098 		uint64_t reserved_61_62:2;
1099 		uint64_t c1_ldwn:1;
1100 		uint64_t c0_ldwn:1;
1101 		uint64_t c1_exc:1;
1102 		uint64_t c0_exc:1;
1103 		uint64_t c1_up_wf:1;
1104 		uint64_t c0_up_wf:1;
1105 		uint64_t c1_un_wf:1;
1106 		uint64_t c0_un_wf:1;
1107 		uint64_t c1_un_bx:1;
1108 		uint64_t c1_un_wi:1;
1109 		uint64_t c1_un_b2:1;
1110 		uint64_t c1_un_b1:1;
1111 		uint64_t c1_un_b0:1;
1112 		uint64_t c1_up_bx:1;
1113 		uint64_t c1_up_wi:1;
1114 		uint64_t c1_up_b2:1;
1115 		uint64_t c1_up_b1:1;
1116 		uint64_t c1_up_b0:1;
1117 		uint64_t c0_un_bx:1;
1118 		uint64_t c0_un_wi:1;
1119 		uint64_t c0_un_b2:1;
1120 		uint64_t c0_un_b1:1;
1121 		uint64_t c0_un_b0:1;
1122 		uint64_t c0_up_bx:1;
1123 		uint64_t c0_up_wi:1;
1124 		uint64_t c0_up_b2:1;
1125 		uint64_t c0_up_b1:1;
1126 		uint64_t c0_up_b0:1;
1127 		uint64_t c1_hpint:1;
1128 		uint64_t c1_pmei:1;
1129 		uint64_t c1_wake:1;
1130 		uint64_t reserved_29_29:1;
1131 		uint64_t c1_se:1;
1132 		uint64_t reserved_27_27:1;
1133 		uint64_t c1_aeri:1;
1134 		uint64_t c0_hpint:1;
1135 		uint64_t c0_pmei:1;
1136 		uint64_t c0_wake:1;
1137 		uint64_t reserved_22_22:1;
1138 		uint64_t c0_se:1;
1139 		uint64_t reserved_20_20:1;
1140 		uint64_t c0_aeri:1;
1141 		uint64_t ptime:1;
1142 		uint64_t pcnt:1;
1143 		uint64_t pidbof:1;
1144 		uint64_t psldbof:1;
1145 		uint64_t dtime1:1;
1146 		uint64_t dtime0:1;
1147 		uint64_t dcnt1:1;
1148 		uint64_t dcnt0:1;
1149 		uint64_t dma1fi:1;
1150 		uint64_t dma0fi:1;
1151 		uint64_t dma4dbo:1;
1152 		uint64_t dma3dbo:1;
1153 		uint64_t dma2dbo:1;
1154 		uint64_t dma1dbo:1;
1155 		uint64_t dma0dbo:1;
1156 		uint64_t iob2big:1;
1157 		uint64_t bar0_to:1;
1158 		uint64_t rml_wto:1;
1159 		uint64_t rml_rto:1;
1160 	} cn56xxp1;
1161 };
1162 
1163 union cvmx_npei_int_enb2 {
1164 	uint64_t u64;
1165 	struct cvmx_npei_int_enb2_s {
1166 		uint64_t reserved_62_63:2;
1167 		uint64_t int_a:1;
1168 		uint64_t c1_ldwn:1;
1169 		uint64_t c0_ldwn:1;
1170 		uint64_t c1_exc:1;
1171 		uint64_t c0_exc:1;
1172 		uint64_t c1_up_wf:1;
1173 		uint64_t c0_up_wf:1;
1174 		uint64_t c1_un_wf:1;
1175 		uint64_t c0_un_wf:1;
1176 		uint64_t c1_un_bx:1;
1177 		uint64_t c1_un_wi:1;
1178 		uint64_t c1_un_b2:1;
1179 		uint64_t c1_un_b1:1;
1180 		uint64_t c1_un_b0:1;
1181 		uint64_t c1_up_bx:1;
1182 		uint64_t c1_up_wi:1;
1183 		uint64_t c1_up_b2:1;
1184 		uint64_t c1_up_b1:1;
1185 		uint64_t c1_up_b0:1;
1186 		uint64_t c0_un_bx:1;
1187 		uint64_t c0_un_wi:1;
1188 		uint64_t c0_un_b2:1;
1189 		uint64_t c0_un_b1:1;
1190 		uint64_t c0_un_b0:1;
1191 		uint64_t c0_up_bx:1;
1192 		uint64_t c0_up_wi:1;
1193 		uint64_t c0_up_b2:1;
1194 		uint64_t c0_up_b1:1;
1195 		uint64_t c0_up_b0:1;
1196 		uint64_t c1_hpint:1;
1197 		uint64_t c1_pmei:1;
1198 		uint64_t c1_wake:1;
1199 		uint64_t crs1_dr:1;
1200 		uint64_t c1_se:1;
1201 		uint64_t crs1_er:1;
1202 		uint64_t c1_aeri:1;
1203 		uint64_t c0_hpint:1;
1204 		uint64_t c0_pmei:1;
1205 		uint64_t c0_wake:1;
1206 		uint64_t crs0_dr:1;
1207 		uint64_t c0_se:1;
1208 		uint64_t crs0_er:1;
1209 		uint64_t c0_aeri:1;
1210 		uint64_t ptime:1;
1211 		uint64_t pcnt:1;
1212 		uint64_t pidbof:1;
1213 		uint64_t psldbof:1;
1214 		uint64_t dtime1:1;
1215 		uint64_t dtime0:1;
1216 		uint64_t dcnt1:1;
1217 		uint64_t dcnt0:1;
1218 		uint64_t dma1fi:1;
1219 		uint64_t dma0fi:1;
1220 		uint64_t dma4dbo:1;
1221 		uint64_t dma3dbo:1;
1222 		uint64_t dma2dbo:1;
1223 		uint64_t dma1dbo:1;
1224 		uint64_t dma0dbo:1;
1225 		uint64_t iob2big:1;
1226 		uint64_t bar0_to:1;
1227 		uint64_t rml_wto:1;
1228 		uint64_t rml_rto:1;
1229 	} s;
1230 	struct cvmx_npei_int_enb2_s cn52xx;
1231 	struct cvmx_npei_int_enb2_cn52xxp1 {
1232 		uint64_t reserved_62_63:2;
1233 		uint64_t int_a:1;
1234 		uint64_t c1_ldwn:1;
1235 		uint64_t c0_ldwn:1;
1236 		uint64_t c1_exc:1;
1237 		uint64_t c0_exc:1;
1238 		uint64_t c1_up_wf:1;
1239 		uint64_t c0_up_wf:1;
1240 		uint64_t c1_un_wf:1;
1241 		uint64_t c0_un_wf:1;
1242 		uint64_t c1_un_bx:1;
1243 		uint64_t c1_un_wi:1;
1244 		uint64_t c1_un_b2:1;
1245 		uint64_t c1_un_b1:1;
1246 		uint64_t c1_un_b0:1;
1247 		uint64_t c1_up_bx:1;
1248 		uint64_t c1_up_wi:1;
1249 		uint64_t c1_up_b2:1;
1250 		uint64_t c1_up_b1:1;
1251 		uint64_t c1_up_b0:1;
1252 		uint64_t c0_un_bx:1;
1253 		uint64_t c0_un_wi:1;
1254 		uint64_t c0_un_b2:1;
1255 		uint64_t c0_un_b1:1;
1256 		uint64_t c0_un_b0:1;
1257 		uint64_t c0_up_bx:1;
1258 		uint64_t c0_up_wi:1;
1259 		uint64_t c0_up_b2:1;
1260 		uint64_t c0_up_b1:1;
1261 		uint64_t c0_up_b0:1;
1262 		uint64_t c1_hpint:1;
1263 		uint64_t c1_pmei:1;
1264 		uint64_t c1_wake:1;
1265 		uint64_t crs1_dr:1;
1266 		uint64_t c1_se:1;
1267 		uint64_t crs1_er:1;
1268 		uint64_t c1_aeri:1;
1269 		uint64_t c0_hpint:1;
1270 		uint64_t c0_pmei:1;
1271 		uint64_t c0_wake:1;
1272 		uint64_t crs0_dr:1;
1273 		uint64_t c0_se:1;
1274 		uint64_t crs0_er:1;
1275 		uint64_t c0_aeri:1;
1276 		uint64_t ptime:1;
1277 		uint64_t pcnt:1;
1278 		uint64_t pidbof:1;
1279 		uint64_t psldbof:1;
1280 		uint64_t dtime1:1;
1281 		uint64_t dtime0:1;
1282 		uint64_t dcnt1:1;
1283 		uint64_t dcnt0:1;
1284 		uint64_t dma1fi:1;
1285 		uint64_t dma0fi:1;
1286 		uint64_t reserved_8_8:1;
1287 		uint64_t dma3dbo:1;
1288 		uint64_t dma2dbo:1;
1289 		uint64_t dma1dbo:1;
1290 		uint64_t dma0dbo:1;
1291 		uint64_t iob2big:1;
1292 		uint64_t bar0_to:1;
1293 		uint64_t rml_wto:1;
1294 		uint64_t rml_rto:1;
1295 	} cn52xxp1;
1296 	struct cvmx_npei_int_enb2_s cn56xx;
1297 	struct cvmx_npei_int_enb2_cn56xxp1 {
1298 		uint64_t reserved_61_63:3;
1299 		uint64_t c1_ldwn:1;
1300 		uint64_t c0_ldwn:1;
1301 		uint64_t c1_exc:1;
1302 		uint64_t c0_exc:1;
1303 		uint64_t c1_up_wf:1;
1304 		uint64_t c0_up_wf:1;
1305 		uint64_t c1_un_wf:1;
1306 		uint64_t c0_un_wf:1;
1307 		uint64_t c1_un_bx:1;
1308 		uint64_t c1_un_wi:1;
1309 		uint64_t c1_un_b2:1;
1310 		uint64_t c1_un_b1:1;
1311 		uint64_t c1_un_b0:1;
1312 		uint64_t c1_up_bx:1;
1313 		uint64_t c1_up_wi:1;
1314 		uint64_t c1_up_b2:1;
1315 		uint64_t c1_up_b1:1;
1316 		uint64_t c1_up_b0:1;
1317 		uint64_t c0_un_bx:1;
1318 		uint64_t c0_un_wi:1;
1319 		uint64_t c0_un_b2:1;
1320 		uint64_t c0_un_b1:1;
1321 		uint64_t c0_un_b0:1;
1322 		uint64_t c0_up_bx:1;
1323 		uint64_t c0_up_wi:1;
1324 		uint64_t c0_up_b2:1;
1325 		uint64_t c0_up_b1:1;
1326 		uint64_t c0_up_b0:1;
1327 		uint64_t c1_hpint:1;
1328 		uint64_t c1_pmei:1;
1329 		uint64_t c1_wake:1;
1330 		uint64_t reserved_29_29:1;
1331 		uint64_t c1_se:1;
1332 		uint64_t reserved_27_27:1;
1333 		uint64_t c1_aeri:1;
1334 		uint64_t c0_hpint:1;
1335 		uint64_t c0_pmei:1;
1336 		uint64_t c0_wake:1;
1337 		uint64_t reserved_22_22:1;
1338 		uint64_t c0_se:1;
1339 		uint64_t reserved_20_20:1;
1340 		uint64_t c0_aeri:1;
1341 		uint64_t ptime:1;
1342 		uint64_t pcnt:1;
1343 		uint64_t pidbof:1;
1344 		uint64_t psldbof:1;
1345 		uint64_t dtime1:1;
1346 		uint64_t dtime0:1;
1347 		uint64_t dcnt1:1;
1348 		uint64_t dcnt0:1;
1349 		uint64_t dma1fi:1;
1350 		uint64_t dma0fi:1;
1351 		uint64_t dma4dbo:1;
1352 		uint64_t dma3dbo:1;
1353 		uint64_t dma2dbo:1;
1354 		uint64_t dma1dbo:1;
1355 		uint64_t dma0dbo:1;
1356 		uint64_t iob2big:1;
1357 		uint64_t bar0_to:1;
1358 		uint64_t rml_wto:1;
1359 		uint64_t rml_rto:1;
1360 	} cn56xxp1;
1361 };
1362 
1363 union cvmx_npei_int_info {
1364 	uint64_t u64;
1365 	struct cvmx_npei_int_info_s {
1366 		uint64_t reserved_12_63:52;
1367 		uint64_t pidbof:6;
1368 		uint64_t psldbof:6;
1369 	} s;
1370 	struct cvmx_npei_int_info_s cn52xx;
1371 	struct cvmx_npei_int_info_s cn56xx;
1372 	struct cvmx_npei_int_info_s cn56xxp1;
1373 };
1374 
1375 union cvmx_npei_int_sum {
1376 	uint64_t u64;
1377 	struct cvmx_npei_int_sum_s {
1378 		uint64_t mio_inta:1;
1379 		uint64_t reserved_62_62:1;
1380 		uint64_t int_a:1;
1381 		uint64_t c1_ldwn:1;
1382 		uint64_t c0_ldwn:1;
1383 		uint64_t c1_exc:1;
1384 		uint64_t c0_exc:1;
1385 		uint64_t c1_up_wf:1;
1386 		uint64_t c0_up_wf:1;
1387 		uint64_t c1_un_wf:1;
1388 		uint64_t c0_un_wf:1;
1389 		uint64_t c1_un_bx:1;
1390 		uint64_t c1_un_wi:1;
1391 		uint64_t c1_un_b2:1;
1392 		uint64_t c1_un_b1:1;
1393 		uint64_t c1_un_b0:1;
1394 		uint64_t c1_up_bx:1;
1395 		uint64_t c1_up_wi:1;
1396 		uint64_t c1_up_b2:1;
1397 		uint64_t c1_up_b1:1;
1398 		uint64_t c1_up_b0:1;
1399 		uint64_t c0_un_bx:1;
1400 		uint64_t c0_un_wi:1;
1401 		uint64_t c0_un_b2:1;
1402 		uint64_t c0_un_b1:1;
1403 		uint64_t c0_un_b0:1;
1404 		uint64_t c0_up_bx:1;
1405 		uint64_t c0_up_wi:1;
1406 		uint64_t c0_up_b2:1;
1407 		uint64_t c0_up_b1:1;
1408 		uint64_t c0_up_b0:1;
1409 		uint64_t c1_hpint:1;
1410 		uint64_t c1_pmei:1;
1411 		uint64_t c1_wake:1;
1412 		uint64_t crs1_dr:1;
1413 		uint64_t c1_se:1;
1414 		uint64_t crs1_er:1;
1415 		uint64_t c1_aeri:1;
1416 		uint64_t c0_hpint:1;
1417 		uint64_t c0_pmei:1;
1418 		uint64_t c0_wake:1;
1419 		uint64_t crs0_dr:1;
1420 		uint64_t c0_se:1;
1421 		uint64_t crs0_er:1;
1422 		uint64_t c0_aeri:1;
1423 		uint64_t ptime:1;
1424 		uint64_t pcnt:1;
1425 		uint64_t pidbof:1;
1426 		uint64_t psldbof:1;
1427 		uint64_t dtime1:1;
1428 		uint64_t dtime0:1;
1429 		uint64_t dcnt1:1;
1430 		uint64_t dcnt0:1;
1431 		uint64_t dma1fi:1;
1432 		uint64_t dma0fi:1;
1433 		uint64_t dma4dbo:1;
1434 		uint64_t dma3dbo:1;
1435 		uint64_t dma2dbo:1;
1436 		uint64_t dma1dbo:1;
1437 		uint64_t dma0dbo:1;
1438 		uint64_t iob2big:1;
1439 		uint64_t bar0_to:1;
1440 		uint64_t rml_wto:1;
1441 		uint64_t rml_rto:1;
1442 	} s;
1443 	struct cvmx_npei_int_sum_s cn52xx;
1444 	struct cvmx_npei_int_sum_cn52xxp1 {
1445 		uint64_t mio_inta:1;
1446 		uint64_t reserved_62_62:1;
1447 		uint64_t int_a:1;
1448 		uint64_t c1_ldwn:1;
1449 		uint64_t c0_ldwn:1;
1450 		uint64_t c1_exc:1;
1451 		uint64_t c0_exc:1;
1452 		uint64_t c1_up_wf:1;
1453 		uint64_t c0_up_wf:1;
1454 		uint64_t c1_un_wf:1;
1455 		uint64_t c0_un_wf:1;
1456 		uint64_t c1_un_bx:1;
1457 		uint64_t c1_un_wi:1;
1458 		uint64_t c1_un_b2:1;
1459 		uint64_t c1_un_b1:1;
1460 		uint64_t c1_un_b0:1;
1461 		uint64_t c1_up_bx:1;
1462 		uint64_t c1_up_wi:1;
1463 		uint64_t c1_up_b2:1;
1464 		uint64_t c1_up_b1:1;
1465 		uint64_t c1_up_b0:1;
1466 		uint64_t c0_un_bx:1;
1467 		uint64_t c0_un_wi:1;
1468 		uint64_t c0_un_b2:1;
1469 		uint64_t c0_un_b1:1;
1470 		uint64_t c0_un_b0:1;
1471 		uint64_t c0_up_bx:1;
1472 		uint64_t c0_up_wi:1;
1473 		uint64_t c0_up_b2:1;
1474 		uint64_t c0_up_b1:1;
1475 		uint64_t c0_up_b0:1;
1476 		uint64_t c1_hpint:1;
1477 		uint64_t c1_pmei:1;
1478 		uint64_t c1_wake:1;
1479 		uint64_t crs1_dr:1;
1480 		uint64_t c1_se:1;
1481 		uint64_t crs1_er:1;
1482 		uint64_t c1_aeri:1;
1483 		uint64_t c0_hpint:1;
1484 		uint64_t c0_pmei:1;
1485 		uint64_t c0_wake:1;
1486 		uint64_t crs0_dr:1;
1487 		uint64_t c0_se:1;
1488 		uint64_t crs0_er:1;
1489 		uint64_t c0_aeri:1;
1490 		uint64_t reserved_15_18:4;
1491 		uint64_t dtime1:1;
1492 		uint64_t dtime0:1;
1493 		uint64_t dcnt1:1;
1494 		uint64_t dcnt0:1;
1495 		uint64_t dma1fi:1;
1496 		uint64_t dma0fi:1;
1497 		uint64_t reserved_8_8:1;
1498 		uint64_t dma3dbo:1;
1499 		uint64_t dma2dbo:1;
1500 		uint64_t dma1dbo:1;
1501 		uint64_t dma0dbo:1;
1502 		uint64_t iob2big:1;
1503 		uint64_t bar0_to:1;
1504 		uint64_t rml_wto:1;
1505 		uint64_t rml_rto:1;
1506 	} cn52xxp1;
1507 	struct cvmx_npei_int_sum_s cn56xx;
1508 	struct cvmx_npei_int_sum_cn56xxp1 {
1509 		uint64_t mio_inta:1;
1510 		uint64_t reserved_61_62:2;
1511 		uint64_t c1_ldwn:1;
1512 		uint64_t c0_ldwn:1;
1513 		uint64_t c1_exc:1;
1514 		uint64_t c0_exc:1;
1515 		uint64_t c1_up_wf:1;
1516 		uint64_t c0_up_wf:1;
1517 		uint64_t c1_un_wf:1;
1518 		uint64_t c0_un_wf:1;
1519 		uint64_t c1_un_bx:1;
1520 		uint64_t c1_un_wi:1;
1521 		uint64_t c1_un_b2:1;
1522 		uint64_t c1_un_b1:1;
1523 		uint64_t c1_un_b0:1;
1524 		uint64_t c1_up_bx:1;
1525 		uint64_t c1_up_wi:1;
1526 		uint64_t c1_up_b2:1;
1527 		uint64_t c1_up_b1:1;
1528 		uint64_t c1_up_b0:1;
1529 		uint64_t c0_un_bx:1;
1530 		uint64_t c0_un_wi:1;
1531 		uint64_t c0_un_b2:1;
1532 		uint64_t c0_un_b1:1;
1533 		uint64_t c0_un_b0:1;
1534 		uint64_t c0_up_bx:1;
1535 		uint64_t c0_up_wi:1;
1536 		uint64_t c0_up_b2:1;
1537 		uint64_t c0_up_b1:1;
1538 		uint64_t c0_up_b0:1;
1539 		uint64_t c1_hpint:1;
1540 		uint64_t c1_pmei:1;
1541 		uint64_t c1_wake:1;
1542 		uint64_t reserved_29_29:1;
1543 		uint64_t c1_se:1;
1544 		uint64_t reserved_27_27:1;
1545 		uint64_t c1_aeri:1;
1546 		uint64_t c0_hpint:1;
1547 		uint64_t c0_pmei:1;
1548 		uint64_t c0_wake:1;
1549 		uint64_t reserved_22_22:1;
1550 		uint64_t c0_se:1;
1551 		uint64_t reserved_20_20:1;
1552 		uint64_t c0_aeri:1;
1553 		uint64_t ptime:1;
1554 		uint64_t pcnt:1;
1555 		uint64_t pidbof:1;
1556 		uint64_t psldbof:1;
1557 		uint64_t dtime1:1;
1558 		uint64_t dtime0:1;
1559 		uint64_t dcnt1:1;
1560 		uint64_t dcnt0:1;
1561 		uint64_t dma1fi:1;
1562 		uint64_t dma0fi:1;
1563 		uint64_t dma4dbo:1;
1564 		uint64_t dma3dbo:1;
1565 		uint64_t dma2dbo:1;
1566 		uint64_t dma1dbo:1;
1567 		uint64_t dma0dbo:1;
1568 		uint64_t iob2big:1;
1569 		uint64_t bar0_to:1;
1570 		uint64_t rml_wto:1;
1571 		uint64_t rml_rto:1;
1572 	} cn56xxp1;
1573 };
1574 
1575 union cvmx_npei_int_sum2 {
1576 	uint64_t u64;
1577 	struct cvmx_npei_int_sum2_s {
1578 		uint64_t mio_inta:1;
1579 		uint64_t reserved_62_62:1;
1580 		uint64_t int_a:1;
1581 		uint64_t c1_ldwn:1;
1582 		uint64_t c0_ldwn:1;
1583 		uint64_t c1_exc:1;
1584 		uint64_t c0_exc:1;
1585 		uint64_t c1_up_wf:1;
1586 		uint64_t c0_up_wf:1;
1587 		uint64_t c1_un_wf:1;
1588 		uint64_t c0_un_wf:1;
1589 		uint64_t c1_un_bx:1;
1590 		uint64_t c1_un_wi:1;
1591 		uint64_t c1_un_b2:1;
1592 		uint64_t c1_un_b1:1;
1593 		uint64_t c1_un_b0:1;
1594 		uint64_t c1_up_bx:1;
1595 		uint64_t c1_up_wi:1;
1596 		uint64_t c1_up_b2:1;
1597 		uint64_t c1_up_b1:1;
1598 		uint64_t c1_up_b0:1;
1599 		uint64_t c0_un_bx:1;
1600 		uint64_t c0_un_wi:1;
1601 		uint64_t c0_un_b2:1;
1602 		uint64_t c0_un_b1:1;
1603 		uint64_t c0_un_b0:1;
1604 		uint64_t c0_up_bx:1;
1605 		uint64_t c0_up_wi:1;
1606 		uint64_t c0_up_b2:1;
1607 		uint64_t c0_up_b1:1;
1608 		uint64_t c0_up_b0:1;
1609 		uint64_t c1_hpint:1;
1610 		uint64_t c1_pmei:1;
1611 		uint64_t c1_wake:1;
1612 		uint64_t crs1_dr:1;
1613 		uint64_t c1_se:1;
1614 		uint64_t crs1_er:1;
1615 		uint64_t c1_aeri:1;
1616 		uint64_t c0_hpint:1;
1617 		uint64_t c0_pmei:1;
1618 		uint64_t c0_wake:1;
1619 		uint64_t crs0_dr:1;
1620 		uint64_t c0_se:1;
1621 		uint64_t crs0_er:1;
1622 		uint64_t c0_aeri:1;
1623 		uint64_t reserved_15_18:4;
1624 		uint64_t dtime1:1;
1625 		uint64_t dtime0:1;
1626 		uint64_t dcnt1:1;
1627 		uint64_t dcnt0:1;
1628 		uint64_t dma1fi:1;
1629 		uint64_t dma0fi:1;
1630 		uint64_t reserved_8_8:1;
1631 		uint64_t dma3dbo:1;
1632 		uint64_t dma2dbo:1;
1633 		uint64_t dma1dbo:1;
1634 		uint64_t dma0dbo:1;
1635 		uint64_t iob2big:1;
1636 		uint64_t bar0_to:1;
1637 		uint64_t rml_wto:1;
1638 		uint64_t rml_rto:1;
1639 	} s;
1640 	struct cvmx_npei_int_sum2_s cn52xx;
1641 	struct cvmx_npei_int_sum2_s cn52xxp1;
1642 	struct cvmx_npei_int_sum2_s cn56xx;
1643 };
1644 
1645 union cvmx_npei_last_win_rdata0 {
1646 	uint64_t u64;
1647 	struct cvmx_npei_last_win_rdata0_s {
1648 		uint64_t data:64;
1649 	} s;
1650 	struct cvmx_npei_last_win_rdata0_s cn52xx;
1651 	struct cvmx_npei_last_win_rdata0_s cn52xxp1;
1652 	struct cvmx_npei_last_win_rdata0_s cn56xx;
1653 	struct cvmx_npei_last_win_rdata0_s cn56xxp1;
1654 };
1655 
1656 union cvmx_npei_last_win_rdata1 {
1657 	uint64_t u64;
1658 	struct cvmx_npei_last_win_rdata1_s {
1659 		uint64_t data:64;
1660 	} s;
1661 	struct cvmx_npei_last_win_rdata1_s cn52xx;
1662 	struct cvmx_npei_last_win_rdata1_s cn52xxp1;
1663 	struct cvmx_npei_last_win_rdata1_s cn56xx;
1664 	struct cvmx_npei_last_win_rdata1_s cn56xxp1;
1665 };
1666 
1667 union cvmx_npei_mem_access_ctl {
1668 	uint64_t u64;
1669 	struct cvmx_npei_mem_access_ctl_s {
1670 		uint64_t reserved_14_63:50;
1671 		uint64_t max_word:4;
1672 		uint64_t timer:10;
1673 	} s;
1674 	struct cvmx_npei_mem_access_ctl_s cn52xx;
1675 	struct cvmx_npei_mem_access_ctl_s cn52xxp1;
1676 	struct cvmx_npei_mem_access_ctl_s cn56xx;
1677 	struct cvmx_npei_mem_access_ctl_s cn56xxp1;
1678 };
1679 
1680 union cvmx_npei_mem_access_subidx {
1681 	uint64_t u64;
1682 	struct cvmx_npei_mem_access_subidx_s {
1683 		uint64_t reserved_42_63:22;
1684 		uint64_t zero:1;
1685 		uint64_t port:2;
1686 		uint64_t nmerge:1;
1687 		uint64_t esr:2;
1688 		uint64_t esw:2;
1689 		uint64_t nsr:1;
1690 		uint64_t nsw:1;
1691 		uint64_t ror:1;
1692 		uint64_t row:1;
1693 		uint64_t ba:30;
1694 	} s;
1695 	struct cvmx_npei_mem_access_subidx_s cn52xx;
1696 	struct cvmx_npei_mem_access_subidx_s cn52xxp1;
1697 	struct cvmx_npei_mem_access_subidx_s cn56xx;
1698 	struct cvmx_npei_mem_access_subidx_s cn56xxp1;
1699 };
1700 
1701 union cvmx_npei_msi_enb0 {
1702 	uint64_t u64;
1703 	struct cvmx_npei_msi_enb0_s {
1704 		uint64_t enb:64;
1705 	} s;
1706 	struct cvmx_npei_msi_enb0_s cn52xx;
1707 	struct cvmx_npei_msi_enb0_s cn52xxp1;
1708 	struct cvmx_npei_msi_enb0_s cn56xx;
1709 	struct cvmx_npei_msi_enb0_s cn56xxp1;
1710 };
1711 
1712 union cvmx_npei_msi_enb1 {
1713 	uint64_t u64;
1714 	struct cvmx_npei_msi_enb1_s {
1715 		uint64_t enb:64;
1716 	} s;
1717 	struct cvmx_npei_msi_enb1_s cn52xx;
1718 	struct cvmx_npei_msi_enb1_s cn52xxp1;
1719 	struct cvmx_npei_msi_enb1_s cn56xx;
1720 	struct cvmx_npei_msi_enb1_s cn56xxp1;
1721 };
1722 
1723 union cvmx_npei_msi_enb2 {
1724 	uint64_t u64;
1725 	struct cvmx_npei_msi_enb2_s {
1726 		uint64_t enb:64;
1727 	} s;
1728 	struct cvmx_npei_msi_enb2_s cn52xx;
1729 	struct cvmx_npei_msi_enb2_s cn52xxp1;
1730 	struct cvmx_npei_msi_enb2_s cn56xx;
1731 	struct cvmx_npei_msi_enb2_s cn56xxp1;
1732 };
1733 
1734 union cvmx_npei_msi_enb3 {
1735 	uint64_t u64;
1736 	struct cvmx_npei_msi_enb3_s {
1737 		uint64_t enb:64;
1738 	} s;
1739 	struct cvmx_npei_msi_enb3_s cn52xx;
1740 	struct cvmx_npei_msi_enb3_s cn52xxp1;
1741 	struct cvmx_npei_msi_enb3_s cn56xx;
1742 	struct cvmx_npei_msi_enb3_s cn56xxp1;
1743 };
1744 
1745 union cvmx_npei_msi_rcv0 {
1746 	uint64_t u64;
1747 	struct cvmx_npei_msi_rcv0_s {
1748 		uint64_t intr:64;
1749 	} s;
1750 	struct cvmx_npei_msi_rcv0_s cn52xx;
1751 	struct cvmx_npei_msi_rcv0_s cn52xxp1;
1752 	struct cvmx_npei_msi_rcv0_s cn56xx;
1753 	struct cvmx_npei_msi_rcv0_s cn56xxp1;
1754 };
1755 
1756 union cvmx_npei_msi_rcv1 {
1757 	uint64_t u64;
1758 	struct cvmx_npei_msi_rcv1_s {
1759 		uint64_t intr:64;
1760 	} s;
1761 	struct cvmx_npei_msi_rcv1_s cn52xx;
1762 	struct cvmx_npei_msi_rcv1_s cn52xxp1;
1763 	struct cvmx_npei_msi_rcv1_s cn56xx;
1764 	struct cvmx_npei_msi_rcv1_s cn56xxp1;
1765 };
1766 
1767 union cvmx_npei_msi_rcv2 {
1768 	uint64_t u64;
1769 	struct cvmx_npei_msi_rcv2_s {
1770 		uint64_t intr:64;
1771 	} s;
1772 	struct cvmx_npei_msi_rcv2_s cn52xx;
1773 	struct cvmx_npei_msi_rcv2_s cn52xxp1;
1774 	struct cvmx_npei_msi_rcv2_s cn56xx;
1775 	struct cvmx_npei_msi_rcv2_s cn56xxp1;
1776 };
1777 
1778 union cvmx_npei_msi_rcv3 {
1779 	uint64_t u64;
1780 	struct cvmx_npei_msi_rcv3_s {
1781 		uint64_t intr:64;
1782 	} s;
1783 	struct cvmx_npei_msi_rcv3_s cn52xx;
1784 	struct cvmx_npei_msi_rcv3_s cn52xxp1;
1785 	struct cvmx_npei_msi_rcv3_s cn56xx;
1786 	struct cvmx_npei_msi_rcv3_s cn56xxp1;
1787 };
1788 
1789 union cvmx_npei_msi_rd_map {
1790 	uint64_t u64;
1791 	struct cvmx_npei_msi_rd_map_s {
1792 		uint64_t reserved_16_63:48;
1793 		uint64_t rd_int:8;
1794 		uint64_t msi_int:8;
1795 	} s;
1796 	struct cvmx_npei_msi_rd_map_s cn52xx;
1797 	struct cvmx_npei_msi_rd_map_s cn52xxp1;
1798 	struct cvmx_npei_msi_rd_map_s cn56xx;
1799 	struct cvmx_npei_msi_rd_map_s cn56xxp1;
1800 };
1801 
1802 union cvmx_npei_msi_w1c_enb0 {
1803 	uint64_t u64;
1804 	struct cvmx_npei_msi_w1c_enb0_s {
1805 		uint64_t clr:64;
1806 	} s;
1807 	struct cvmx_npei_msi_w1c_enb0_s cn52xx;
1808 	struct cvmx_npei_msi_w1c_enb0_s cn56xx;
1809 };
1810 
1811 union cvmx_npei_msi_w1c_enb1 {
1812 	uint64_t u64;
1813 	struct cvmx_npei_msi_w1c_enb1_s {
1814 		uint64_t clr:64;
1815 	} s;
1816 	struct cvmx_npei_msi_w1c_enb1_s cn52xx;
1817 	struct cvmx_npei_msi_w1c_enb1_s cn56xx;
1818 };
1819 
1820 union cvmx_npei_msi_w1c_enb2 {
1821 	uint64_t u64;
1822 	struct cvmx_npei_msi_w1c_enb2_s {
1823 		uint64_t clr:64;
1824 	} s;
1825 	struct cvmx_npei_msi_w1c_enb2_s cn52xx;
1826 	struct cvmx_npei_msi_w1c_enb2_s cn56xx;
1827 };
1828 
1829 union cvmx_npei_msi_w1c_enb3 {
1830 	uint64_t u64;
1831 	struct cvmx_npei_msi_w1c_enb3_s {
1832 		uint64_t clr:64;
1833 	} s;
1834 	struct cvmx_npei_msi_w1c_enb3_s cn52xx;
1835 	struct cvmx_npei_msi_w1c_enb3_s cn56xx;
1836 };
1837 
1838 union cvmx_npei_msi_w1s_enb0 {
1839 	uint64_t u64;
1840 	struct cvmx_npei_msi_w1s_enb0_s {
1841 		uint64_t set:64;
1842 	} s;
1843 	struct cvmx_npei_msi_w1s_enb0_s cn52xx;
1844 	struct cvmx_npei_msi_w1s_enb0_s cn56xx;
1845 };
1846 
1847 union cvmx_npei_msi_w1s_enb1 {
1848 	uint64_t u64;
1849 	struct cvmx_npei_msi_w1s_enb1_s {
1850 		uint64_t set:64;
1851 	} s;
1852 	struct cvmx_npei_msi_w1s_enb1_s cn52xx;
1853 	struct cvmx_npei_msi_w1s_enb1_s cn56xx;
1854 };
1855 
1856 union cvmx_npei_msi_w1s_enb2 {
1857 	uint64_t u64;
1858 	struct cvmx_npei_msi_w1s_enb2_s {
1859 		uint64_t set:64;
1860 	} s;
1861 	struct cvmx_npei_msi_w1s_enb2_s cn52xx;
1862 	struct cvmx_npei_msi_w1s_enb2_s cn56xx;
1863 };
1864 
1865 union cvmx_npei_msi_w1s_enb3 {
1866 	uint64_t u64;
1867 	struct cvmx_npei_msi_w1s_enb3_s {
1868 		uint64_t set:64;
1869 	} s;
1870 	struct cvmx_npei_msi_w1s_enb3_s cn52xx;
1871 	struct cvmx_npei_msi_w1s_enb3_s cn56xx;
1872 };
1873 
1874 union cvmx_npei_msi_wr_map {
1875 	uint64_t u64;
1876 	struct cvmx_npei_msi_wr_map_s {
1877 		uint64_t reserved_16_63:48;
1878 		uint64_t ciu_int:8;
1879 		uint64_t msi_int:8;
1880 	} s;
1881 	struct cvmx_npei_msi_wr_map_s cn52xx;
1882 	struct cvmx_npei_msi_wr_map_s cn52xxp1;
1883 	struct cvmx_npei_msi_wr_map_s cn56xx;
1884 	struct cvmx_npei_msi_wr_map_s cn56xxp1;
1885 };
1886 
1887 union cvmx_npei_pcie_credit_cnt {
1888 	uint64_t u64;
1889 	struct cvmx_npei_pcie_credit_cnt_s {
1890 		uint64_t reserved_48_63:16;
1891 		uint64_t p1_ccnt:8;
1892 		uint64_t p1_ncnt:8;
1893 		uint64_t p1_pcnt:8;
1894 		uint64_t p0_ccnt:8;
1895 		uint64_t p0_ncnt:8;
1896 		uint64_t p0_pcnt:8;
1897 	} s;
1898 	struct cvmx_npei_pcie_credit_cnt_s cn52xx;
1899 	struct cvmx_npei_pcie_credit_cnt_s cn56xx;
1900 };
1901 
1902 union cvmx_npei_pcie_msi_rcv {
1903 	uint64_t u64;
1904 	struct cvmx_npei_pcie_msi_rcv_s {
1905 		uint64_t reserved_8_63:56;
1906 		uint64_t intr:8;
1907 	} s;
1908 	struct cvmx_npei_pcie_msi_rcv_s cn52xx;
1909 	struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
1910 	struct cvmx_npei_pcie_msi_rcv_s cn56xx;
1911 	struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
1912 };
1913 
1914 union cvmx_npei_pcie_msi_rcv_b1 {
1915 	uint64_t u64;
1916 	struct cvmx_npei_pcie_msi_rcv_b1_s {
1917 		uint64_t reserved_16_63:48;
1918 		uint64_t intr:8;
1919 		uint64_t reserved_0_7:8;
1920 	} s;
1921 	struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
1922 	struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
1923 	struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
1924 	struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
1925 };
1926 
1927 union cvmx_npei_pcie_msi_rcv_b2 {
1928 	uint64_t u64;
1929 	struct cvmx_npei_pcie_msi_rcv_b2_s {
1930 		uint64_t reserved_24_63:40;
1931 		uint64_t intr:8;
1932 		uint64_t reserved_0_15:16;
1933 	} s;
1934 	struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
1935 	struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
1936 	struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
1937 	struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
1938 };
1939 
1940 union cvmx_npei_pcie_msi_rcv_b3 {
1941 	uint64_t u64;
1942 	struct cvmx_npei_pcie_msi_rcv_b3_s {
1943 		uint64_t reserved_32_63:32;
1944 		uint64_t intr:8;
1945 		uint64_t reserved_0_23:24;
1946 	} s;
1947 	struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
1948 	struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
1949 	struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
1950 	struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
1951 };
1952 
1953 union cvmx_npei_pktx_cnts {
1954 	uint64_t u64;
1955 	struct cvmx_npei_pktx_cnts_s {
1956 		uint64_t reserved_54_63:10;
1957 		uint64_t timer:22;
1958 		uint64_t cnt:32;
1959 	} s;
1960 	struct cvmx_npei_pktx_cnts_s cn52xx;
1961 	struct cvmx_npei_pktx_cnts_s cn56xx;
1962 	struct cvmx_npei_pktx_cnts_s cn56xxp1;
1963 };
1964 
1965 union cvmx_npei_pktx_in_bp {
1966 	uint64_t u64;
1967 	struct cvmx_npei_pktx_in_bp_s {
1968 		uint64_t wmark:32;
1969 		uint64_t cnt:32;
1970 	} s;
1971 	struct cvmx_npei_pktx_in_bp_s cn52xx;
1972 	struct cvmx_npei_pktx_in_bp_s cn56xx;
1973 	struct cvmx_npei_pktx_in_bp_s cn56xxp1;
1974 };
1975 
1976 union cvmx_npei_pktx_instr_baddr {
1977 	uint64_t u64;
1978 	struct cvmx_npei_pktx_instr_baddr_s {
1979 		uint64_t addr:61;
1980 		uint64_t reserved_0_2:3;
1981 	} s;
1982 	struct cvmx_npei_pktx_instr_baddr_s cn52xx;
1983 	struct cvmx_npei_pktx_instr_baddr_s cn56xx;
1984 	struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
1985 };
1986 
1987 union cvmx_npei_pktx_instr_baoff_dbell {
1988 	uint64_t u64;
1989 	struct cvmx_npei_pktx_instr_baoff_dbell_s {
1990 		uint64_t aoff:32;
1991 		uint64_t dbell:32;
1992 	} s;
1993 	struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
1994 	struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
1995 	struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
1996 };
1997 
1998 union cvmx_npei_pktx_instr_fifo_rsize {
1999 	uint64_t u64;
2000 	struct cvmx_npei_pktx_instr_fifo_rsize_s {
2001 		uint64_t max:9;
2002 		uint64_t rrp:9;
2003 		uint64_t wrp:9;
2004 		uint64_t fcnt:5;
2005 		uint64_t rsize:32;
2006 	} s;
2007 	struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
2008 	struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
2009 	struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
2010 };
2011 
2012 union cvmx_npei_pktx_instr_header {
2013 	uint64_t u64;
2014 	struct cvmx_npei_pktx_instr_header_s {
2015 		uint64_t reserved_44_63:20;
2016 		uint64_t pbp:1;
2017 		uint64_t rsv_f:5;
2018 		uint64_t rparmode:2;
2019 		uint64_t rsv_e:1;
2020 		uint64_t rskp_len:7;
2021 		uint64_t rsv_d:6;
2022 		uint64_t use_ihdr:1;
2023 		uint64_t rsv_c:5;
2024 		uint64_t par_mode:2;
2025 		uint64_t rsv_b:1;
2026 		uint64_t skp_len:7;
2027 		uint64_t rsv_a:6;
2028 	} s;
2029 	struct cvmx_npei_pktx_instr_header_s cn52xx;
2030 	struct cvmx_npei_pktx_instr_header_s cn56xx;
2031 	struct cvmx_npei_pktx_instr_header_s cn56xxp1;
2032 };
2033 
2034 union cvmx_npei_pktx_slist_baddr {
2035 	uint64_t u64;
2036 	struct cvmx_npei_pktx_slist_baddr_s {
2037 		uint64_t addr:60;
2038 		uint64_t reserved_0_3:4;
2039 	} s;
2040 	struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2041 	struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2042 	struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
2043 };
2044 
2045 union cvmx_npei_pktx_slist_baoff_dbell {
2046 	uint64_t u64;
2047 	struct cvmx_npei_pktx_slist_baoff_dbell_s {
2048 		uint64_t aoff:32;
2049 		uint64_t dbell:32;
2050 	} s;
2051 	struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2052 	struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2053 	struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
2054 };
2055 
2056 union cvmx_npei_pktx_slist_fifo_rsize {
2057 	uint64_t u64;
2058 	struct cvmx_npei_pktx_slist_fifo_rsize_s {
2059 		uint64_t reserved_32_63:32;
2060 		uint64_t rsize:32;
2061 	} s;
2062 	struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2063 	struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2064 	struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
2065 };
2066 
2067 union cvmx_npei_pkt_cnt_int {
2068 	uint64_t u64;
2069 	struct cvmx_npei_pkt_cnt_int_s {
2070 		uint64_t reserved_32_63:32;
2071 		uint64_t port:32;
2072 	} s;
2073 	struct cvmx_npei_pkt_cnt_int_s cn52xx;
2074 	struct cvmx_npei_pkt_cnt_int_s cn56xx;
2075 	struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
2076 };
2077 
2078 union cvmx_npei_pkt_cnt_int_enb {
2079 	uint64_t u64;
2080 	struct cvmx_npei_pkt_cnt_int_enb_s {
2081 		uint64_t reserved_32_63:32;
2082 		uint64_t port:32;
2083 	} s;
2084 	struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2085 	struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2086 	struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
2087 };
2088 
2089 union cvmx_npei_pkt_data_out_es {
2090 	uint64_t u64;
2091 	struct cvmx_npei_pkt_data_out_es_s {
2092 		uint64_t es:64;
2093 	} s;
2094 	struct cvmx_npei_pkt_data_out_es_s cn52xx;
2095 	struct cvmx_npei_pkt_data_out_es_s cn56xx;
2096 	struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
2097 };
2098 
2099 union cvmx_npei_pkt_data_out_ns {
2100 	uint64_t u64;
2101 	struct cvmx_npei_pkt_data_out_ns_s {
2102 		uint64_t reserved_32_63:32;
2103 		uint64_t nsr:32;
2104 	} s;
2105 	struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2106 	struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2107 	struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
2108 };
2109 
2110 union cvmx_npei_pkt_data_out_ror {
2111 	uint64_t u64;
2112 	struct cvmx_npei_pkt_data_out_ror_s {
2113 		uint64_t reserved_32_63:32;
2114 		uint64_t ror:32;
2115 	} s;
2116 	struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2117 	struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2118 	struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
2119 };
2120 
2121 union cvmx_npei_pkt_dpaddr {
2122 	uint64_t u64;
2123 	struct cvmx_npei_pkt_dpaddr_s {
2124 		uint64_t reserved_32_63:32;
2125 		uint64_t dptr:32;
2126 	} s;
2127 	struct cvmx_npei_pkt_dpaddr_s cn52xx;
2128 	struct cvmx_npei_pkt_dpaddr_s cn56xx;
2129 	struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
2130 };
2131 
2132 union cvmx_npei_pkt_in_bp {
2133 	uint64_t u64;
2134 	struct cvmx_npei_pkt_in_bp_s {
2135 		uint64_t reserved_32_63:32;
2136 		uint64_t bp:32;
2137 	} s;
2138 	struct cvmx_npei_pkt_in_bp_s cn56xx;
2139 };
2140 
2141 union cvmx_npei_pkt_in_donex_cnts {
2142 	uint64_t u64;
2143 	struct cvmx_npei_pkt_in_donex_cnts_s {
2144 		uint64_t reserved_32_63:32;
2145 		uint64_t cnt:32;
2146 	} s;
2147 	struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2148 	struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2149 	struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
2150 };
2151 
2152 union cvmx_npei_pkt_in_instr_counts {
2153 	uint64_t u64;
2154 	struct cvmx_npei_pkt_in_instr_counts_s {
2155 		uint64_t wr_cnt:32;
2156 		uint64_t rd_cnt:32;
2157 	} s;
2158 	struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
2159 	struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
2160 };
2161 
2162 union cvmx_npei_pkt_in_pcie_port {
2163 	uint64_t u64;
2164 	struct cvmx_npei_pkt_in_pcie_port_s {
2165 		uint64_t pp:64;
2166 	} s;
2167 	struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
2168 	struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
2169 };
2170 
2171 union cvmx_npei_pkt_input_control {
2172 	uint64_t u64;
2173 	struct cvmx_npei_pkt_input_control_s {
2174 		uint64_t reserved_23_63:41;
2175 		uint64_t pkt_rr:1;
2176 		uint64_t pbp_dhi:13;
2177 		uint64_t d_nsr:1;
2178 		uint64_t d_esr:2;
2179 		uint64_t d_ror:1;
2180 		uint64_t use_csr:1;
2181 		uint64_t nsr:1;
2182 		uint64_t esr:2;
2183 		uint64_t ror:1;
2184 	} s;
2185 	struct cvmx_npei_pkt_input_control_s cn52xx;
2186 	struct cvmx_npei_pkt_input_control_s cn56xx;
2187 	struct cvmx_npei_pkt_input_control_s cn56xxp1;
2188 };
2189 
2190 union cvmx_npei_pkt_instr_enb {
2191 	uint64_t u64;
2192 	struct cvmx_npei_pkt_instr_enb_s {
2193 		uint64_t reserved_32_63:32;
2194 		uint64_t enb:32;
2195 	} s;
2196 	struct cvmx_npei_pkt_instr_enb_s cn52xx;
2197 	struct cvmx_npei_pkt_instr_enb_s cn56xx;
2198 	struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
2199 };
2200 
2201 union cvmx_npei_pkt_instr_rd_size {
2202 	uint64_t u64;
2203 	struct cvmx_npei_pkt_instr_rd_size_s {
2204 		uint64_t rdsize:64;
2205 	} s;
2206 	struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
2207 	struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
2208 };
2209 
2210 union cvmx_npei_pkt_instr_size {
2211 	uint64_t u64;
2212 	struct cvmx_npei_pkt_instr_size_s {
2213 		uint64_t reserved_32_63:32;
2214 		uint64_t is_64b:32;
2215 	} s;
2216 	struct cvmx_npei_pkt_instr_size_s cn52xx;
2217 	struct cvmx_npei_pkt_instr_size_s cn56xx;
2218 	struct cvmx_npei_pkt_instr_size_s cn56xxp1;
2219 };
2220 
2221 union cvmx_npei_pkt_int_levels {
2222 	uint64_t u64;
2223 	struct cvmx_npei_pkt_int_levels_s {
2224 		uint64_t reserved_54_63:10;
2225 		uint64_t time:22;
2226 		uint64_t cnt:32;
2227 	} s;
2228 	struct cvmx_npei_pkt_int_levels_s cn52xx;
2229 	struct cvmx_npei_pkt_int_levels_s cn56xx;
2230 	struct cvmx_npei_pkt_int_levels_s cn56xxp1;
2231 };
2232 
2233 union cvmx_npei_pkt_iptr {
2234 	uint64_t u64;
2235 	struct cvmx_npei_pkt_iptr_s {
2236 		uint64_t reserved_32_63:32;
2237 		uint64_t iptr:32;
2238 	} s;
2239 	struct cvmx_npei_pkt_iptr_s cn52xx;
2240 	struct cvmx_npei_pkt_iptr_s cn56xx;
2241 	struct cvmx_npei_pkt_iptr_s cn56xxp1;
2242 };
2243 
2244 union cvmx_npei_pkt_out_bmode {
2245 	uint64_t u64;
2246 	struct cvmx_npei_pkt_out_bmode_s {
2247 		uint64_t reserved_32_63:32;
2248 		uint64_t bmode:32;
2249 	} s;
2250 	struct cvmx_npei_pkt_out_bmode_s cn52xx;
2251 	struct cvmx_npei_pkt_out_bmode_s cn56xx;
2252 	struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
2253 };
2254 
2255 union cvmx_npei_pkt_out_enb {
2256 	uint64_t u64;
2257 	struct cvmx_npei_pkt_out_enb_s {
2258 		uint64_t reserved_32_63:32;
2259 		uint64_t enb:32;
2260 	} s;
2261 	struct cvmx_npei_pkt_out_enb_s cn52xx;
2262 	struct cvmx_npei_pkt_out_enb_s cn56xx;
2263 	struct cvmx_npei_pkt_out_enb_s cn56xxp1;
2264 };
2265 
2266 union cvmx_npei_pkt_output_wmark {
2267 	uint64_t u64;
2268 	struct cvmx_npei_pkt_output_wmark_s {
2269 		uint64_t reserved_32_63:32;
2270 		uint64_t wmark:32;
2271 	} s;
2272 	struct cvmx_npei_pkt_output_wmark_s cn52xx;
2273 	struct cvmx_npei_pkt_output_wmark_s cn56xx;
2274 };
2275 
2276 union cvmx_npei_pkt_pcie_port {
2277 	uint64_t u64;
2278 	struct cvmx_npei_pkt_pcie_port_s {
2279 		uint64_t pp:64;
2280 	} s;
2281 	struct cvmx_npei_pkt_pcie_port_s cn52xx;
2282 	struct cvmx_npei_pkt_pcie_port_s cn56xx;
2283 	struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
2284 };
2285 
2286 union cvmx_npei_pkt_port_in_rst {
2287 	uint64_t u64;
2288 	struct cvmx_npei_pkt_port_in_rst_s {
2289 		uint64_t in_rst:32;
2290 		uint64_t out_rst:32;
2291 	} s;
2292 	struct cvmx_npei_pkt_port_in_rst_s cn52xx;
2293 	struct cvmx_npei_pkt_port_in_rst_s cn56xx;
2294 };
2295 
2296 union cvmx_npei_pkt_slist_es {
2297 	uint64_t u64;
2298 	struct cvmx_npei_pkt_slist_es_s {
2299 		uint64_t es:64;
2300 	} s;
2301 	struct cvmx_npei_pkt_slist_es_s cn52xx;
2302 	struct cvmx_npei_pkt_slist_es_s cn56xx;
2303 	struct cvmx_npei_pkt_slist_es_s cn56xxp1;
2304 };
2305 
2306 union cvmx_npei_pkt_slist_id_size {
2307 	uint64_t u64;
2308 	struct cvmx_npei_pkt_slist_id_size_s {
2309 		uint64_t reserved_23_63:41;
2310 		uint64_t isize:7;
2311 		uint64_t bsize:16;
2312 	} s;
2313 	struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2314 	struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2315 	struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
2316 };
2317 
2318 union cvmx_npei_pkt_slist_ns {
2319 	uint64_t u64;
2320 	struct cvmx_npei_pkt_slist_ns_s {
2321 		uint64_t reserved_32_63:32;
2322 		uint64_t nsr:32;
2323 	} s;
2324 	struct cvmx_npei_pkt_slist_ns_s cn52xx;
2325 	struct cvmx_npei_pkt_slist_ns_s cn56xx;
2326 	struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
2327 };
2328 
2329 union cvmx_npei_pkt_slist_ror {
2330 	uint64_t u64;
2331 	struct cvmx_npei_pkt_slist_ror_s {
2332 		uint64_t reserved_32_63:32;
2333 		uint64_t ror:32;
2334 	} s;
2335 	struct cvmx_npei_pkt_slist_ror_s cn52xx;
2336 	struct cvmx_npei_pkt_slist_ror_s cn56xx;
2337 	struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
2338 };
2339 
2340 union cvmx_npei_pkt_time_int {
2341 	uint64_t u64;
2342 	struct cvmx_npei_pkt_time_int_s {
2343 		uint64_t reserved_32_63:32;
2344 		uint64_t port:32;
2345 	} s;
2346 	struct cvmx_npei_pkt_time_int_s cn52xx;
2347 	struct cvmx_npei_pkt_time_int_s cn56xx;
2348 	struct cvmx_npei_pkt_time_int_s cn56xxp1;
2349 };
2350 
2351 union cvmx_npei_pkt_time_int_enb {
2352 	uint64_t u64;
2353 	struct cvmx_npei_pkt_time_int_enb_s {
2354 		uint64_t reserved_32_63:32;
2355 		uint64_t port:32;
2356 	} s;
2357 	struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2358 	struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2359 	struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
2360 };
2361 
2362 union cvmx_npei_rsl_int_blocks {
2363 	uint64_t u64;
2364 	struct cvmx_npei_rsl_int_blocks_s {
2365 		uint64_t reserved_31_63:33;
2366 		uint64_t iob:1;
2367 		uint64_t lmc1:1;
2368 		uint64_t agl:1;
2369 		uint64_t reserved_24_27:4;
2370 		uint64_t asxpcs1:1;
2371 		uint64_t asxpcs0:1;
2372 		uint64_t reserved_21_21:1;
2373 		uint64_t pip:1;
2374 		uint64_t reserved_18_19:2;
2375 		uint64_t lmc0:1;
2376 		uint64_t l2c:1;
2377 		uint64_t usb1:1;
2378 		uint64_t rad:1;
2379 		uint64_t usb:1;
2380 		uint64_t pow:1;
2381 		uint64_t tim:1;
2382 		uint64_t pko:1;
2383 		uint64_t ipd:1;
2384 		uint64_t reserved_8_8:1;
2385 		uint64_t zip:1;
2386 		uint64_t reserved_6_6:1;
2387 		uint64_t fpa:1;
2388 		uint64_t key:1;
2389 		uint64_t npei:1;
2390 		uint64_t gmx1:1;
2391 		uint64_t gmx0:1;
2392 		uint64_t mio:1;
2393 	} s;
2394 	struct cvmx_npei_rsl_int_blocks_s cn52xx;
2395 	struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2396 	struct cvmx_npei_rsl_int_blocks_cn56xx {
2397 		uint64_t reserved_31_63:33;
2398 		uint64_t iob:1;
2399 		uint64_t lmc1:1;
2400 		uint64_t agl:1;
2401 		uint64_t reserved_24_27:4;
2402 		uint64_t asxpcs1:1;
2403 		uint64_t asxpcs0:1;
2404 		uint64_t reserved_21_21:1;
2405 		uint64_t pip:1;
2406 		uint64_t reserved_18_19:2;
2407 		uint64_t lmc0:1;
2408 		uint64_t l2c:1;
2409 		uint64_t reserved_15_15:1;
2410 		uint64_t rad:1;
2411 		uint64_t usb:1;
2412 		uint64_t pow:1;
2413 		uint64_t tim:1;
2414 		uint64_t pko:1;
2415 		uint64_t ipd:1;
2416 		uint64_t reserved_8_8:1;
2417 		uint64_t zip:1;
2418 		uint64_t reserved_6_6:1;
2419 		uint64_t fpa:1;
2420 		uint64_t key:1;
2421 		uint64_t npei:1;
2422 		uint64_t gmx1:1;
2423 		uint64_t gmx0:1;
2424 		uint64_t mio:1;
2425 	} cn56xx;
2426 	struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
2427 };
2428 
2429 union cvmx_npei_scratch_1 {
2430 	uint64_t u64;
2431 	struct cvmx_npei_scratch_1_s {
2432 		uint64_t data:64;
2433 	} s;
2434 	struct cvmx_npei_scratch_1_s cn52xx;
2435 	struct cvmx_npei_scratch_1_s cn52xxp1;
2436 	struct cvmx_npei_scratch_1_s cn56xx;
2437 	struct cvmx_npei_scratch_1_s cn56xxp1;
2438 };
2439 
2440 union cvmx_npei_state1 {
2441 	uint64_t u64;
2442 	struct cvmx_npei_state1_s {
2443 		uint64_t cpl1:12;
2444 		uint64_t cpl0:12;
2445 		uint64_t arb:1;
2446 		uint64_t csr:39;
2447 	} s;
2448 	struct cvmx_npei_state1_s cn52xx;
2449 	struct cvmx_npei_state1_s cn52xxp1;
2450 	struct cvmx_npei_state1_s cn56xx;
2451 	struct cvmx_npei_state1_s cn56xxp1;
2452 };
2453 
2454 union cvmx_npei_state2 {
2455 	uint64_t u64;
2456 	struct cvmx_npei_state2_s {
2457 		uint64_t reserved_48_63:16;
2458 		uint64_t npei:1;
2459 		uint64_t rac:1;
2460 		uint64_t csm1:15;
2461 		uint64_t csm0:15;
2462 		uint64_t nnp0:8;
2463 		uint64_t nnd:8;
2464 	} s;
2465 	struct cvmx_npei_state2_s cn52xx;
2466 	struct cvmx_npei_state2_s cn52xxp1;
2467 	struct cvmx_npei_state2_s cn56xx;
2468 	struct cvmx_npei_state2_s cn56xxp1;
2469 };
2470 
2471 union cvmx_npei_state3 {
2472 	uint64_t u64;
2473 	struct cvmx_npei_state3_s {
2474 		uint64_t reserved_56_63:8;
2475 		uint64_t psm1:15;
2476 		uint64_t psm0:15;
2477 		uint64_t nsm1:13;
2478 		uint64_t nsm0:13;
2479 	} s;
2480 	struct cvmx_npei_state3_s cn52xx;
2481 	struct cvmx_npei_state3_s cn52xxp1;
2482 	struct cvmx_npei_state3_s cn56xx;
2483 	struct cvmx_npei_state3_s cn56xxp1;
2484 };
2485 
2486 union cvmx_npei_win_rd_addr {
2487 	uint64_t u64;
2488 	struct cvmx_npei_win_rd_addr_s {
2489 		uint64_t reserved_51_63:13;
2490 		uint64_t ld_cmd:2;
2491 		uint64_t iobit:1;
2492 		uint64_t rd_addr:48;
2493 	} s;
2494 	struct cvmx_npei_win_rd_addr_s cn52xx;
2495 	struct cvmx_npei_win_rd_addr_s cn52xxp1;
2496 	struct cvmx_npei_win_rd_addr_s cn56xx;
2497 	struct cvmx_npei_win_rd_addr_s cn56xxp1;
2498 };
2499 
2500 union cvmx_npei_win_rd_data {
2501 	uint64_t u64;
2502 	struct cvmx_npei_win_rd_data_s {
2503 		uint64_t rd_data:64;
2504 	} s;
2505 	struct cvmx_npei_win_rd_data_s cn52xx;
2506 	struct cvmx_npei_win_rd_data_s cn52xxp1;
2507 	struct cvmx_npei_win_rd_data_s cn56xx;
2508 	struct cvmx_npei_win_rd_data_s cn56xxp1;
2509 };
2510 
2511 union cvmx_npei_win_wr_addr {
2512 	uint64_t u64;
2513 	struct cvmx_npei_win_wr_addr_s {
2514 		uint64_t reserved_49_63:15;
2515 		uint64_t iobit:1;
2516 		uint64_t wr_addr:46;
2517 		uint64_t reserved_0_1:2;
2518 	} s;
2519 	struct cvmx_npei_win_wr_addr_s cn52xx;
2520 	struct cvmx_npei_win_wr_addr_s cn52xxp1;
2521 	struct cvmx_npei_win_wr_addr_s cn56xx;
2522 	struct cvmx_npei_win_wr_addr_s cn56xxp1;
2523 };
2524 
2525 union cvmx_npei_win_wr_data {
2526 	uint64_t u64;
2527 	struct cvmx_npei_win_wr_data_s {
2528 		uint64_t wr_data:64;
2529 	} s;
2530 	struct cvmx_npei_win_wr_data_s cn52xx;
2531 	struct cvmx_npei_win_wr_data_s cn52xxp1;
2532 	struct cvmx_npei_win_wr_data_s cn56xx;
2533 	struct cvmx_npei_win_wr_data_s cn56xxp1;
2534 };
2535 
2536 union cvmx_npei_win_wr_mask {
2537 	uint64_t u64;
2538 	struct cvmx_npei_win_wr_mask_s {
2539 		uint64_t reserved_8_63:56;
2540 		uint64_t wr_mask:8;
2541 	} s;
2542 	struct cvmx_npei_win_wr_mask_s cn52xx;
2543 	struct cvmx_npei_win_wr_mask_s cn52xxp1;
2544 	struct cvmx_npei_win_wr_mask_s cn56xx;
2545 	struct cvmx_npei_win_wr_mask_s cn56xxp1;
2546 };
2547 
2548 union cvmx_npei_window_ctl {
2549 	uint64_t u64;
2550 	struct cvmx_npei_window_ctl_s {
2551 		uint64_t reserved_32_63:32;
2552 		uint64_t time:32;
2553 	} s;
2554 	struct cvmx_npei_window_ctl_s cn52xx;
2555 	struct cvmx_npei_window_ctl_s cn52xxp1;
2556 	struct cvmx_npei_window_ctl_s cn56xx;
2557 	struct cvmx_npei_window_ctl_s cn56xxp1;
2558 };
2559 
2560 #endif
2561