1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2011 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_NPEI_DEFS_H__ 29 #define __CVMX_NPEI_DEFS_H__ 30 31 #define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16) 32 #define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull) 33 #define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull) 34 #define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull) 35 #define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull) 36 #define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull) 37 #define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull) 38 #define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull) 39 #define CVMX_NPEI_DBG_DATA (0x0000000000000510ull) 40 #define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull) 41 #define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull) 42 #define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull) 43 #define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16) 44 #define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16) 45 #define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16) 46 #define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16) 47 #define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull) 48 #define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull) 49 #define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull) 50 #define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull) 51 #define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull) 52 #define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull) 53 #define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull) 54 #define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull) 55 #define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull) 56 #define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull) 57 #define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull) 58 #define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull) 59 #define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull) 60 #define CVMX_NPEI_INT_ENB (0x0000000000000540ull) 61 #define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull) 62 #define CVMX_NPEI_INT_INFO (0x0000000000000590ull) 63 #define CVMX_NPEI_INT_SUM (0x0000000000000530ull) 64 #define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull) 65 #define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) 66 #define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) 67 #define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) 68 #define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12) 69 #define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) 70 #define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) 71 #define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) 72 #define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull) 73 #define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull) 74 #define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull) 75 #define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull) 76 #define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull) 77 #define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull) 78 #define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull) 79 #define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull) 80 #define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull) 81 #define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull) 82 #define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull) 83 #define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull) 84 #define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull) 85 #define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull) 86 #define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull) 87 #define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull) 88 #define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull) 89 #define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) 90 #define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) 91 #define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) 92 #define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) 93 #define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16) 94 #define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16) 95 #define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16) 96 #define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16) 97 #define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16) 98 #define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16) 99 #define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16) 100 #define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16) 101 #define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull) 102 #define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull) 103 #define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull) 104 #define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull) 105 #define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull) 106 #define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull) 107 #define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull) 108 #define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull) 109 #define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull) 110 #define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull) 111 #define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull) 112 #define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull) 113 #define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16) 114 #define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull) 115 #define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull) 116 #define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull) 117 #define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull) 118 #define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull) 119 #define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull) 120 #define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull) 121 #define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull) 122 #define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull) 123 #define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull) 124 #define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull) 125 #define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull) 126 #define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull) 127 #define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull) 128 #define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull) 129 #define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull) 130 #define CVMX_NPEI_STATE1 (0x0000000000000620ull) 131 #define CVMX_NPEI_STATE2 (0x0000000000000630ull) 132 #define CVMX_NPEI_STATE3 (0x0000000000000640ull) 133 #define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull) 134 #define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull) 135 #define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull) 136 #define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull) 137 #define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull) 138 #define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull) 139 140 union cvmx_npei_bar1_indexx { 141 uint32_t u32; 142 struct cvmx_npei_bar1_indexx_s { 143 uint32_t reserved_18_31:14; 144 uint32_t addr_idx:14; 145 uint32_t ca:1; 146 uint32_t end_swp:2; 147 uint32_t addr_v:1; 148 } s; 149 struct cvmx_npei_bar1_indexx_s cn52xx; 150 struct cvmx_npei_bar1_indexx_s cn52xxp1; 151 struct cvmx_npei_bar1_indexx_s cn56xx; 152 struct cvmx_npei_bar1_indexx_s cn56xxp1; 153 }; 154 155 union cvmx_npei_bist_status { 156 uint64_t u64; 157 struct cvmx_npei_bist_status_s { 158 uint64_t pkt_rdf:1; 159 uint64_t reserved_60_62:3; 160 uint64_t pcr_gim:1; 161 uint64_t pkt_pif:1; 162 uint64_t pcsr_int:1; 163 uint64_t pcsr_im:1; 164 uint64_t pcsr_cnt:1; 165 uint64_t pcsr_id:1; 166 uint64_t pcsr_sl:1; 167 uint64_t reserved_50_52:3; 168 uint64_t pkt_ind:1; 169 uint64_t pkt_slm:1; 170 uint64_t reserved_36_47:12; 171 uint64_t d0_pst:1; 172 uint64_t d1_pst:1; 173 uint64_t d2_pst:1; 174 uint64_t d3_pst:1; 175 uint64_t reserved_31_31:1; 176 uint64_t n2p0_c:1; 177 uint64_t n2p0_o:1; 178 uint64_t n2p1_c:1; 179 uint64_t n2p1_o:1; 180 uint64_t cpl_p0:1; 181 uint64_t cpl_p1:1; 182 uint64_t p2n1_po:1; 183 uint64_t p2n1_no:1; 184 uint64_t p2n1_co:1; 185 uint64_t p2n0_po:1; 186 uint64_t p2n0_no:1; 187 uint64_t p2n0_co:1; 188 uint64_t p2n0_c0:1; 189 uint64_t p2n0_c1:1; 190 uint64_t p2n0_n:1; 191 uint64_t p2n0_p0:1; 192 uint64_t p2n0_p1:1; 193 uint64_t p2n1_c0:1; 194 uint64_t p2n1_c1:1; 195 uint64_t p2n1_n:1; 196 uint64_t p2n1_p0:1; 197 uint64_t p2n1_p1:1; 198 uint64_t csm0:1; 199 uint64_t csm1:1; 200 uint64_t dif0:1; 201 uint64_t dif1:1; 202 uint64_t dif2:1; 203 uint64_t dif3:1; 204 uint64_t reserved_2_2:1; 205 uint64_t msi:1; 206 uint64_t ncb_cmd:1; 207 } s; 208 struct cvmx_npei_bist_status_cn52xx { 209 uint64_t pkt_rdf:1; 210 uint64_t reserved_60_62:3; 211 uint64_t pcr_gim:1; 212 uint64_t pkt_pif:1; 213 uint64_t pcsr_int:1; 214 uint64_t pcsr_im:1; 215 uint64_t pcsr_cnt:1; 216 uint64_t pcsr_id:1; 217 uint64_t pcsr_sl:1; 218 uint64_t pkt_imem:1; 219 uint64_t pkt_pfm:1; 220 uint64_t pkt_pof:1; 221 uint64_t reserved_48_49:2; 222 uint64_t pkt_pop0:1; 223 uint64_t pkt_pop1:1; 224 uint64_t d0_mem:1; 225 uint64_t d1_mem:1; 226 uint64_t d2_mem:1; 227 uint64_t d3_mem:1; 228 uint64_t d4_mem:1; 229 uint64_t ds_mem:1; 230 uint64_t reserved_36_39:4; 231 uint64_t d0_pst:1; 232 uint64_t d1_pst:1; 233 uint64_t d2_pst:1; 234 uint64_t d3_pst:1; 235 uint64_t d4_pst:1; 236 uint64_t n2p0_c:1; 237 uint64_t n2p0_o:1; 238 uint64_t n2p1_c:1; 239 uint64_t n2p1_o:1; 240 uint64_t cpl_p0:1; 241 uint64_t cpl_p1:1; 242 uint64_t p2n1_po:1; 243 uint64_t p2n1_no:1; 244 uint64_t p2n1_co:1; 245 uint64_t p2n0_po:1; 246 uint64_t p2n0_no:1; 247 uint64_t p2n0_co:1; 248 uint64_t p2n0_c0:1; 249 uint64_t p2n0_c1:1; 250 uint64_t p2n0_n:1; 251 uint64_t p2n0_p0:1; 252 uint64_t p2n0_p1:1; 253 uint64_t p2n1_c0:1; 254 uint64_t p2n1_c1:1; 255 uint64_t p2n1_n:1; 256 uint64_t p2n1_p0:1; 257 uint64_t p2n1_p1:1; 258 uint64_t csm0:1; 259 uint64_t csm1:1; 260 uint64_t dif0:1; 261 uint64_t dif1:1; 262 uint64_t dif2:1; 263 uint64_t dif3:1; 264 uint64_t dif4:1; 265 uint64_t msi:1; 266 uint64_t ncb_cmd:1; 267 } cn52xx; 268 struct cvmx_npei_bist_status_cn52xxp1 { 269 uint64_t reserved_46_63:18; 270 uint64_t d0_mem0:1; 271 uint64_t d1_mem1:1; 272 uint64_t d2_mem2:1; 273 uint64_t d3_mem3:1; 274 uint64_t dr0_mem:1; 275 uint64_t d0_mem:1; 276 uint64_t d1_mem:1; 277 uint64_t d2_mem:1; 278 uint64_t d3_mem:1; 279 uint64_t dr1_mem:1; 280 uint64_t d0_pst:1; 281 uint64_t d1_pst:1; 282 uint64_t d2_pst:1; 283 uint64_t d3_pst:1; 284 uint64_t dr2_mem:1; 285 uint64_t n2p0_c:1; 286 uint64_t n2p0_o:1; 287 uint64_t n2p1_c:1; 288 uint64_t n2p1_o:1; 289 uint64_t cpl_p0:1; 290 uint64_t cpl_p1:1; 291 uint64_t p2n1_po:1; 292 uint64_t p2n1_no:1; 293 uint64_t p2n1_co:1; 294 uint64_t p2n0_po:1; 295 uint64_t p2n0_no:1; 296 uint64_t p2n0_co:1; 297 uint64_t p2n0_c0:1; 298 uint64_t p2n0_c1:1; 299 uint64_t p2n0_n:1; 300 uint64_t p2n0_p0:1; 301 uint64_t p2n0_p1:1; 302 uint64_t p2n1_c0:1; 303 uint64_t p2n1_c1:1; 304 uint64_t p2n1_n:1; 305 uint64_t p2n1_p0:1; 306 uint64_t p2n1_p1:1; 307 uint64_t csm0:1; 308 uint64_t csm1:1; 309 uint64_t dif0:1; 310 uint64_t dif1:1; 311 uint64_t dif2:1; 312 uint64_t dif3:1; 313 uint64_t dr3_mem:1; 314 uint64_t msi:1; 315 uint64_t ncb_cmd:1; 316 } cn52xxp1; 317 struct cvmx_npei_bist_status_cn52xx cn56xx; 318 struct cvmx_npei_bist_status_cn56xxp1 { 319 uint64_t reserved_58_63:6; 320 uint64_t pcsr_int:1; 321 uint64_t pcsr_im:1; 322 uint64_t pcsr_cnt:1; 323 uint64_t pcsr_id:1; 324 uint64_t pcsr_sl:1; 325 uint64_t pkt_pout:1; 326 uint64_t pkt_imem:1; 327 uint64_t pkt_cntm:1; 328 uint64_t pkt_ind:1; 329 uint64_t pkt_slm:1; 330 uint64_t pkt_odf:1; 331 uint64_t pkt_oif:1; 332 uint64_t pkt_out:1; 333 uint64_t pkt_i0:1; 334 uint64_t pkt_i1:1; 335 uint64_t pkt_s0:1; 336 uint64_t pkt_s1:1; 337 uint64_t d0_mem:1; 338 uint64_t d1_mem:1; 339 uint64_t d2_mem:1; 340 uint64_t d3_mem:1; 341 uint64_t d4_mem:1; 342 uint64_t d0_pst:1; 343 uint64_t d1_pst:1; 344 uint64_t d2_pst:1; 345 uint64_t d3_pst:1; 346 uint64_t d4_pst:1; 347 uint64_t n2p0_c:1; 348 uint64_t n2p0_o:1; 349 uint64_t n2p1_c:1; 350 uint64_t n2p1_o:1; 351 uint64_t cpl_p0:1; 352 uint64_t cpl_p1:1; 353 uint64_t p2n1_po:1; 354 uint64_t p2n1_no:1; 355 uint64_t p2n1_co:1; 356 uint64_t p2n0_po:1; 357 uint64_t p2n0_no:1; 358 uint64_t p2n0_co:1; 359 uint64_t p2n0_c0:1; 360 uint64_t p2n0_c1:1; 361 uint64_t p2n0_n:1; 362 uint64_t p2n0_p0:1; 363 uint64_t p2n0_p1:1; 364 uint64_t p2n1_c0:1; 365 uint64_t p2n1_c1:1; 366 uint64_t p2n1_n:1; 367 uint64_t p2n1_p0:1; 368 uint64_t p2n1_p1:1; 369 uint64_t csm0:1; 370 uint64_t csm1:1; 371 uint64_t dif0:1; 372 uint64_t dif1:1; 373 uint64_t dif2:1; 374 uint64_t dif3:1; 375 uint64_t dif4:1; 376 uint64_t msi:1; 377 uint64_t ncb_cmd:1; 378 } cn56xxp1; 379 }; 380 381 union cvmx_npei_bist_status2 { 382 uint64_t u64; 383 struct cvmx_npei_bist_status2_s { 384 uint64_t reserved_14_63:50; 385 uint64_t prd_tag:1; 386 uint64_t prd_st0:1; 387 uint64_t prd_st1:1; 388 uint64_t prd_err:1; 389 uint64_t nrd_st:1; 390 uint64_t nwe_st:1; 391 uint64_t nwe_wr0:1; 392 uint64_t nwe_wr1:1; 393 uint64_t pkt_rd:1; 394 uint64_t psc_p0:1; 395 uint64_t psc_p1:1; 396 uint64_t pkt_gd:1; 397 uint64_t pkt_gl:1; 398 uint64_t pkt_blk:1; 399 } s; 400 struct cvmx_npei_bist_status2_s cn52xx; 401 struct cvmx_npei_bist_status2_s cn56xx; 402 }; 403 404 union cvmx_npei_ctl_port0 { 405 uint64_t u64; 406 struct cvmx_npei_ctl_port0_s { 407 uint64_t reserved_21_63:43; 408 uint64_t waitl_com:1; 409 uint64_t intd:1; 410 uint64_t intc:1; 411 uint64_t intb:1; 412 uint64_t inta:1; 413 uint64_t intd_map:2; 414 uint64_t intc_map:2; 415 uint64_t intb_map:2; 416 uint64_t inta_map:2; 417 uint64_t ctlp_ro:1; 418 uint64_t reserved_6_6:1; 419 uint64_t ptlp_ro:1; 420 uint64_t bar2_enb:1; 421 uint64_t bar2_esx:2; 422 uint64_t bar2_cax:1; 423 uint64_t wait_com:1; 424 } s; 425 struct cvmx_npei_ctl_port0_s cn52xx; 426 struct cvmx_npei_ctl_port0_s cn52xxp1; 427 struct cvmx_npei_ctl_port0_s cn56xx; 428 struct cvmx_npei_ctl_port0_s cn56xxp1; 429 }; 430 431 union cvmx_npei_ctl_port1 { 432 uint64_t u64; 433 struct cvmx_npei_ctl_port1_s { 434 uint64_t reserved_21_63:43; 435 uint64_t waitl_com:1; 436 uint64_t intd:1; 437 uint64_t intc:1; 438 uint64_t intb:1; 439 uint64_t inta:1; 440 uint64_t intd_map:2; 441 uint64_t intc_map:2; 442 uint64_t intb_map:2; 443 uint64_t inta_map:2; 444 uint64_t ctlp_ro:1; 445 uint64_t reserved_6_6:1; 446 uint64_t ptlp_ro:1; 447 uint64_t bar2_enb:1; 448 uint64_t bar2_esx:2; 449 uint64_t bar2_cax:1; 450 uint64_t wait_com:1; 451 } s; 452 struct cvmx_npei_ctl_port1_s cn52xx; 453 struct cvmx_npei_ctl_port1_s cn52xxp1; 454 struct cvmx_npei_ctl_port1_s cn56xx; 455 struct cvmx_npei_ctl_port1_s cn56xxp1; 456 }; 457 458 union cvmx_npei_ctl_status { 459 uint64_t u64; 460 struct cvmx_npei_ctl_status_s { 461 uint64_t reserved_44_63:20; 462 uint64_t p1_ntags:6; 463 uint64_t p0_ntags:6; 464 uint64_t cfg_rtry:16; 465 uint64_t ring_en:1; 466 uint64_t lnk_rst:1; 467 uint64_t arb:1; 468 uint64_t pkt_bp:4; 469 uint64_t host_mode:1; 470 uint64_t chip_rev:8; 471 } s; 472 struct cvmx_npei_ctl_status_s cn52xx; 473 struct cvmx_npei_ctl_status_cn52xxp1 { 474 uint64_t reserved_44_63:20; 475 uint64_t p1_ntags:6; 476 uint64_t p0_ntags:6; 477 uint64_t cfg_rtry:16; 478 uint64_t reserved_15_15:1; 479 uint64_t lnk_rst:1; 480 uint64_t arb:1; 481 uint64_t reserved_9_12:4; 482 uint64_t host_mode:1; 483 uint64_t chip_rev:8; 484 } cn52xxp1; 485 struct cvmx_npei_ctl_status_s cn56xx; 486 struct cvmx_npei_ctl_status_cn56xxp1 { 487 uint64_t reserved_15_63:49; 488 uint64_t lnk_rst:1; 489 uint64_t arb:1; 490 uint64_t pkt_bp:4; 491 uint64_t host_mode:1; 492 uint64_t chip_rev:8; 493 } cn56xxp1; 494 }; 495 496 union cvmx_npei_ctl_status2 { 497 uint64_t u64; 498 struct cvmx_npei_ctl_status2_s { 499 uint64_t reserved_16_63:48; 500 uint64_t mps:1; 501 uint64_t mrrs:3; 502 uint64_t c1_w_flt:1; 503 uint64_t c0_w_flt:1; 504 uint64_t c1_b1_s:3; 505 uint64_t c0_b1_s:3; 506 uint64_t c1_wi_d:1; 507 uint64_t c1_b0_d:1; 508 uint64_t c0_wi_d:1; 509 uint64_t c0_b0_d:1; 510 } s; 511 struct cvmx_npei_ctl_status2_s cn52xx; 512 struct cvmx_npei_ctl_status2_s cn52xxp1; 513 struct cvmx_npei_ctl_status2_s cn56xx; 514 struct cvmx_npei_ctl_status2_s cn56xxp1; 515 }; 516 517 union cvmx_npei_data_out_cnt { 518 uint64_t u64; 519 struct cvmx_npei_data_out_cnt_s { 520 uint64_t reserved_44_63:20; 521 uint64_t p1_ucnt:16; 522 uint64_t p1_fcnt:6; 523 uint64_t p0_ucnt:16; 524 uint64_t p0_fcnt:6; 525 } s; 526 struct cvmx_npei_data_out_cnt_s cn52xx; 527 struct cvmx_npei_data_out_cnt_s cn52xxp1; 528 struct cvmx_npei_data_out_cnt_s cn56xx; 529 struct cvmx_npei_data_out_cnt_s cn56xxp1; 530 }; 531 532 union cvmx_npei_dbg_data { 533 uint64_t u64; 534 struct cvmx_npei_dbg_data_s { 535 uint64_t reserved_28_63:36; 536 uint64_t qlm0_rev_lanes:1; 537 uint64_t reserved_25_26:2; 538 uint64_t qlm1_spd:2; 539 uint64_t c_mul:5; 540 uint64_t dsel_ext:1; 541 uint64_t data:17; 542 } s; 543 struct cvmx_npei_dbg_data_cn52xx { 544 uint64_t reserved_29_63:35; 545 uint64_t qlm0_link_width:1; 546 uint64_t qlm0_rev_lanes:1; 547 uint64_t qlm1_mode:2; 548 uint64_t qlm1_spd:2; 549 uint64_t c_mul:5; 550 uint64_t dsel_ext:1; 551 uint64_t data:17; 552 } cn52xx; 553 struct cvmx_npei_dbg_data_cn52xx cn52xxp1; 554 struct cvmx_npei_dbg_data_cn56xx { 555 uint64_t reserved_29_63:35; 556 uint64_t qlm2_rev_lanes:1; 557 uint64_t qlm0_rev_lanes:1; 558 uint64_t qlm3_spd:2; 559 uint64_t qlm1_spd:2; 560 uint64_t c_mul:5; 561 uint64_t dsel_ext:1; 562 uint64_t data:17; 563 } cn56xx; 564 struct cvmx_npei_dbg_data_cn56xx cn56xxp1; 565 }; 566 567 union cvmx_npei_dbg_select { 568 uint64_t u64; 569 struct cvmx_npei_dbg_select_s { 570 uint64_t reserved_16_63:48; 571 uint64_t dbg_sel:16; 572 } s; 573 struct cvmx_npei_dbg_select_s cn52xx; 574 struct cvmx_npei_dbg_select_s cn52xxp1; 575 struct cvmx_npei_dbg_select_s cn56xx; 576 struct cvmx_npei_dbg_select_s cn56xxp1; 577 }; 578 579 union cvmx_npei_dmax_counts { 580 uint64_t u64; 581 struct cvmx_npei_dmax_counts_s { 582 uint64_t reserved_39_63:25; 583 uint64_t fcnt:7; 584 uint64_t dbell:32; 585 } s; 586 struct cvmx_npei_dmax_counts_s cn52xx; 587 struct cvmx_npei_dmax_counts_s cn52xxp1; 588 struct cvmx_npei_dmax_counts_s cn56xx; 589 struct cvmx_npei_dmax_counts_s cn56xxp1; 590 }; 591 592 union cvmx_npei_dmax_dbell { 593 uint32_t u32; 594 struct cvmx_npei_dmax_dbell_s { 595 uint32_t reserved_16_31:16; 596 uint32_t dbell:16; 597 } s; 598 struct cvmx_npei_dmax_dbell_s cn52xx; 599 struct cvmx_npei_dmax_dbell_s cn52xxp1; 600 struct cvmx_npei_dmax_dbell_s cn56xx; 601 struct cvmx_npei_dmax_dbell_s cn56xxp1; 602 }; 603 604 union cvmx_npei_dmax_ibuff_saddr { 605 uint64_t u64; 606 struct cvmx_npei_dmax_ibuff_saddr_s { 607 uint64_t reserved_37_63:27; 608 uint64_t idle:1; 609 uint64_t saddr:29; 610 uint64_t reserved_0_6:7; 611 } s; 612 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx; 613 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 { 614 uint64_t reserved_36_63:28; 615 uint64_t saddr:29; 616 uint64_t reserved_0_6:7; 617 } cn52xxp1; 618 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; 619 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1; 620 }; 621 622 union cvmx_npei_dmax_naddr { 623 uint64_t u64; 624 struct cvmx_npei_dmax_naddr_s { 625 uint64_t reserved_36_63:28; 626 uint64_t addr:36; 627 } s; 628 struct cvmx_npei_dmax_naddr_s cn52xx; 629 struct cvmx_npei_dmax_naddr_s cn52xxp1; 630 struct cvmx_npei_dmax_naddr_s cn56xx; 631 struct cvmx_npei_dmax_naddr_s cn56xxp1; 632 }; 633 634 union cvmx_npei_dma0_int_level { 635 uint64_t u64; 636 struct cvmx_npei_dma0_int_level_s { 637 uint64_t time:32; 638 uint64_t cnt:32; 639 } s; 640 struct cvmx_npei_dma0_int_level_s cn52xx; 641 struct cvmx_npei_dma0_int_level_s cn52xxp1; 642 struct cvmx_npei_dma0_int_level_s cn56xx; 643 struct cvmx_npei_dma0_int_level_s cn56xxp1; 644 }; 645 646 union cvmx_npei_dma1_int_level { 647 uint64_t u64; 648 struct cvmx_npei_dma1_int_level_s { 649 uint64_t time:32; 650 uint64_t cnt:32; 651 } s; 652 struct cvmx_npei_dma1_int_level_s cn52xx; 653 struct cvmx_npei_dma1_int_level_s cn52xxp1; 654 struct cvmx_npei_dma1_int_level_s cn56xx; 655 struct cvmx_npei_dma1_int_level_s cn56xxp1; 656 }; 657 658 union cvmx_npei_dma_cnts { 659 uint64_t u64; 660 struct cvmx_npei_dma_cnts_s { 661 uint64_t dma1:32; 662 uint64_t dma0:32; 663 } s; 664 struct cvmx_npei_dma_cnts_s cn52xx; 665 struct cvmx_npei_dma_cnts_s cn52xxp1; 666 struct cvmx_npei_dma_cnts_s cn56xx; 667 struct cvmx_npei_dma_cnts_s cn56xxp1; 668 }; 669 670 union cvmx_npei_dma_control { 671 uint64_t u64; 672 struct cvmx_npei_dma_control_s { 673 uint64_t reserved_40_63:24; 674 uint64_t p_32b_m:1; 675 uint64_t dma4_enb:1; 676 uint64_t dma3_enb:1; 677 uint64_t dma2_enb:1; 678 uint64_t dma1_enb:1; 679 uint64_t dma0_enb:1; 680 uint64_t b0_lend:1; 681 uint64_t dwb_denb:1; 682 uint64_t dwb_ichk:9; 683 uint64_t fpa_que:3; 684 uint64_t o_add1:1; 685 uint64_t o_ro:1; 686 uint64_t o_ns:1; 687 uint64_t o_es:2; 688 uint64_t o_mode:1; 689 uint64_t csize:14; 690 } s; 691 struct cvmx_npei_dma_control_s cn52xx; 692 struct cvmx_npei_dma_control_cn52xxp1 { 693 uint64_t reserved_38_63:26; 694 uint64_t dma3_enb:1; 695 uint64_t dma2_enb:1; 696 uint64_t dma1_enb:1; 697 uint64_t dma0_enb:1; 698 uint64_t b0_lend:1; 699 uint64_t dwb_denb:1; 700 uint64_t dwb_ichk:9; 701 uint64_t fpa_que:3; 702 uint64_t o_add1:1; 703 uint64_t o_ro:1; 704 uint64_t o_ns:1; 705 uint64_t o_es:2; 706 uint64_t o_mode:1; 707 uint64_t csize:14; 708 } cn52xxp1; 709 struct cvmx_npei_dma_control_s cn56xx; 710 struct cvmx_npei_dma_control_cn56xxp1 { 711 uint64_t reserved_39_63:25; 712 uint64_t dma4_enb:1; 713 uint64_t dma3_enb:1; 714 uint64_t dma2_enb:1; 715 uint64_t dma1_enb:1; 716 uint64_t dma0_enb:1; 717 uint64_t b0_lend:1; 718 uint64_t dwb_denb:1; 719 uint64_t dwb_ichk:9; 720 uint64_t fpa_que:3; 721 uint64_t o_add1:1; 722 uint64_t o_ro:1; 723 uint64_t o_ns:1; 724 uint64_t o_es:2; 725 uint64_t o_mode:1; 726 uint64_t csize:14; 727 } cn56xxp1; 728 }; 729 730 union cvmx_npei_dma_pcie_req_num { 731 uint64_t u64; 732 struct cvmx_npei_dma_pcie_req_num_s { 733 uint64_t dma_arb:1; 734 uint64_t reserved_53_62:10; 735 uint64_t pkt_cnt:5; 736 uint64_t reserved_45_47:3; 737 uint64_t dma4_cnt:5; 738 uint64_t reserved_37_39:3; 739 uint64_t dma3_cnt:5; 740 uint64_t reserved_29_31:3; 741 uint64_t dma2_cnt:5; 742 uint64_t reserved_21_23:3; 743 uint64_t dma1_cnt:5; 744 uint64_t reserved_13_15:3; 745 uint64_t dma0_cnt:5; 746 uint64_t reserved_5_7:3; 747 uint64_t dma_cnt:5; 748 } s; 749 struct cvmx_npei_dma_pcie_req_num_s cn52xx; 750 struct cvmx_npei_dma_pcie_req_num_s cn56xx; 751 }; 752 753 union cvmx_npei_dma_state1 { 754 uint64_t u64; 755 struct cvmx_npei_dma_state1_s { 756 uint64_t reserved_40_63:24; 757 uint64_t d4_dwe:8; 758 uint64_t d3_dwe:8; 759 uint64_t d2_dwe:8; 760 uint64_t d1_dwe:8; 761 uint64_t d0_dwe:8; 762 } s; 763 struct cvmx_npei_dma_state1_s cn52xx; 764 }; 765 766 union cvmx_npei_dma_state1_p1 { 767 uint64_t u64; 768 struct cvmx_npei_dma_state1_p1_s { 769 uint64_t reserved_60_63:4; 770 uint64_t d0_difst:7; 771 uint64_t d1_difst:7; 772 uint64_t d2_difst:7; 773 uint64_t d3_difst:7; 774 uint64_t d4_difst:7; 775 uint64_t d0_reqst:5; 776 uint64_t d1_reqst:5; 777 uint64_t d2_reqst:5; 778 uint64_t d3_reqst:5; 779 uint64_t d4_reqst:5; 780 } s; 781 struct cvmx_npei_dma_state1_p1_cn52xxp1 { 782 uint64_t reserved_60_63:4; 783 uint64_t d0_difst:7; 784 uint64_t d1_difst:7; 785 uint64_t d2_difst:7; 786 uint64_t d3_difst:7; 787 uint64_t reserved_25_31:7; 788 uint64_t d0_reqst:5; 789 uint64_t d1_reqst:5; 790 uint64_t d2_reqst:5; 791 uint64_t d3_reqst:5; 792 uint64_t reserved_0_4:5; 793 } cn52xxp1; 794 struct cvmx_npei_dma_state1_p1_s cn56xxp1; 795 }; 796 797 union cvmx_npei_dma_state2 { 798 uint64_t u64; 799 struct cvmx_npei_dma_state2_s { 800 uint64_t reserved_28_63:36; 801 uint64_t ndwe:4; 802 uint64_t reserved_21_23:3; 803 uint64_t ndre:5; 804 uint64_t reserved_10_15:6; 805 uint64_t prd:10; 806 } s; 807 struct cvmx_npei_dma_state2_s cn52xx; 808 }; 809 810 union cvmx_npei_dma_state2_p1 { 811 uint64_t u64; 812 struct cvmx_npei_dma_state2_p1_s { 813 uint64_t reserved_45_63:19; 814 uint64_t d0_dffst:9; 815 uint64_t d1_dffst:9; 816 uint64_t d2_dffst:9; 817 uint64_t d3_dffst:9; 818 uint64_t d4_dffst:9; 819 } s; 820 struct cvmx_npei_dma_state2_p1_cn52xxp1 { 821 uint64_t reserved_45_63:19; 822 uint64_t d0_dffst:9; 823 uint64_t d1_dffst:9; 824 uint64_t d2_dffst:9; 825 uint64_t d3_dffst:9; 826 uint64_t reserved_0_8:9; 827 } cn52xxp1; 828 struct cvmx_npei_dma_state2_p1_s cn56xxp1; 829 }; 830 831 union cvmx_npei_dma_state3_p1 { 832 uint64_t u64; 833 struct cvmx_npei_dma_state3_p1_s { 834 uint64_t reserved_60_63:4; 835 uint64_t d0_drest:15; 836 uint64_t d1_drest:15; 837 uint64_t d2_drest:15; 838 uint64_t d3_drest:15; 839 } s; 840 struct cvmx_npei_dma_state3_p1_s cn52xxp1; 841 struct cvmx_npei_dma_state3_p1_s cn56xxp1; 842 }; 843 844 union cvmx_npei_dma_state4_p1 { 845 uint64_t u64; 846 struct cvmx_npei_dma_state4_p1_s { 847 uint64_t reserved_52_63:12; 848 uint64_t d0_dwest:13; 849 uint64_t d1_dwest:13; 850 uint64_t d2_dwest:13; 851 uint64_t d3_dwest:13; 852 } s; 853 struct cvmx_npei_dma_state4_p1_s cn52xxp1; 854 struct cvmx_npei_dma_state4_p1_s cn56xxp1; 855 }; 856 857 union cvmx_npei_dma_state5_p1 { 858 uint64_t u64; 859 struct cvmx_npei_dma_state5_p1_s { 860 uint64_t reserved_28_63:36; 861 uint64_t d4_drest:15; 862 uint64_t d4_dwest:13; 863 } s; 864 struct cvmx_npei_dma_state5_p1_s cn56xxp1; 865 }; 866 867 union cvmx_npei_int_a_enb { 868 uint64_t u64; 869 struct cvmx_npei_int_a_enb_s { 870 uint64_t reserved_10_63:54; 871 uint64_t pout_err:1; 872 uint64_t pin_bp:1; 873 uint64_t p1_rdlk:1; 874 uint64_t p0_rdlk:1; 875 uint64_t pgl_err:1; 876 uint64_t pdi_err:1; 877 uint64_t pop_err:1; 878 uint64_t pins_err:1; 879 uint64_t dma1_cpl:1; 880 uint64_t dma0_cpl:1; 881 } s; 882 struct cvmx_npei_int_a_enb_s cn52xx; 883 struct cvmx_npei_int_a_enb_cn52xxp1 { 884 uint64_t reserved_2_63:62; 885 uint64_t dma1_cpl:1; 886 uint64_t dma0_cpl:1; 887 } cn52xxp1; 888 struct cvmx_npei_int_a_enb_s cn56xx; 889 }; 890 891 union cvmx_npei_int_a_enb2 { 892 uint64_t u64; 893 struct cvmx_npei_int_a_enb2_s { 894 uint64_t reserved_10_63:54; 895 uint64_t pout_err:1; 896 uint64_t pin_bp:1; 897 uint64_t p1_rdlk:1; 898 uint64_t p0_rdlk:1; 899 uint64_t pgl_err:1; 900 uint64_t pdi_err:1; 901 uint64_t pop_err:1; 902 uint64_t pins_err:1; 903 uint64_t dma1_cpl:1; 904 uint64_t dma0_cpl:1; 905 } s; 906 struct cvmx_npei_int_a_enb2_s cn52xx; 907 struct cvmx_npei_int_a_enb2_cn52xxp1 { 908 uint64_t reserved_2_63:62; 909 uint64_t dma1_cpl:1; 910 uint64_t dma0_cpl:1; 911 } cn52xxp1; 912 struct cvmx_npei_int_a_enb2_s cn56xx; 913 }; 914 915 union cvmx_npei_int_a_sum { 916 uint64_t u64; 917 struct cvmx_npei_int_a_sum_s { 918 uint64_t reserved_10_63:54; 919 uint64_t pout_err:1; 920 uint64_t pin_bp:1; 921 uint64_t p1_rdlk:1; 922 uint64_t p0_rdlk:1; 923 uint64_t pgl_err:1; 924 uint64_t pdi_err:1; 925 uint64_t pop_err:1; 926 uint64_t pins_err:1; 927 uint64_t dma1_cpl:1; 928 uint64_t dma0_cpl:1; 929 } s; 930 struct cvmx_npei_int_a_sum_s cn52xx; 931 struct cvmx_npei_int_a_sum_cn52xxp1 { 932 uint64_t reserved_2_63:62; 933 uint64_t dma1_cpl:1; 934 uint64_t dma0_cpl:1; 935 } cn52xxp1; 936 struct cvmx_npei_int_a_sum_s cn56xx; 937 }; 938 939 union cvmx_npei_int_enb { 940 uint64_t u64; 941 struct cvmx_npei_int_enb_s { 942 uint64_t mio_inta:1; 943 uint64_t reserved_62_62:1; 944 uint64_t int_a:1; 945 uint64_t c1_ldwn:1; 946 uint64_t c0_ldwn:1; 947 uint64_t c1_exc:1; 948 uint64_t c0_exc:1; 949 uint64_t c1_up_wf:1; 950 uint64_t c0_up_wf:1; 951 uint64_t c1_un_wf:1; 952 uint64_t c0_un_wf:1; 953 uint64_t c1_un_bx:1; 954 uint64_t c1_un_wi:1; 955 uint64_t c1_un_b2:1; 956 uint64_t c1_un_b1:1; 957 uint64_t c1_un_b0:1; 958 uint64_t c1_up_bx:1; 959 uint64_t c1_up_wi:1; 960 uint64_t c1_up_b2:1; 961 uint64_t c1_up_b1:1; 962 uint64_t c1_up_b0:1; 963 uint64_t c0_un_bx:1; 964 uint64_t c0_un_wi:1; 965 uint64_t c0_un_b2:1; 966 uint64_t c0_un_b1:1; 967 uint64_t c0_un_b0:1; 968 uint64_t c0_up_bx:1; 969 uint64_t c0_up_wi:1; 970 uint64_t c0_up_b2:1; 971 uint64_t c0_up_b1:1; 972 uint64_t c0_up_b0:1; 973 uint64_t c1_hpint:1; 974 uint64_t c1_pmei:1; 975 uint64_t c1_wake:1; 976 uint64_t crs1_dr:1; 977 uint64_t c1_se:1; 978 uint64_t crs1_er:1; 979 uint64_t c1_aeri:1; 980 uint64_t c0_hpint:1; 981 uint64_t c0_pmei:1; 982 uint64_t c0_wake:1; 983 uint64_t crs0_dr:1; 984 uint64_t c0_se:1; 985 uint64_t crs0_er:1; 986 uint64_t c0_aeri:1; 987 uint64_t ptime:1; 988 uint64_t pcnt:1; 989 uint64_t pidbof:1; 990 uint64_t psldbof:1; 991 uint64_t dtime1:1; 992 uint64_t dtime0:1; 993 uint64_t dcnt1:1; 994 uint64_t dcnt0:1; 995 uint64_t dma1fi:1; 996 uint64_t dma0fi:1; 997 uint64_t dma4dbo:1; 998 uint64_t dma3dbo:1; 999 uint64_t dma2dbo:1; 1000 uint64_t dma1dbo:1; 1001 uint64_t dma0dbo:1; 1002 uint64_t iob2big:1; 1003 uint64_t bar0_to:1; 1004 uint64_t rml_wto:1; 1005 uint64_t rml_rto:1; 1006 } s; 1007 struct cvmx_npei_int_enb_s cn52xx; 1008 struct cvmx_npei_int_enb_cn52xxp1 { 1009 uint64_t mio_inta:1; 1010 uint64_t reserved_62_62:1; 1011 uint64_t int_a:1; 1012 uint64_t c1_ldwn:1; 1013 uint64_t c0_ldwn:1; 1014 uint64_t c1_exc:1; 1015 uint64_t c0_exc:1; 1016 uint64_t c1_up_wf:1; 1017 uint64_t c0_up_wf:1; 1018 uint64_t c1_un_wf:1; 1019 uint64_t c0_un_wf:1; 1020 uint64_t c1_un_bx:1; 1021 uint64_t c1_un_wi:1; 1022 uint64_t c1_un_b2:1; 1023 uint64_t c1_un_b1:1; 1024 uint64_t c1_un_b0:1; 1025 uint64_t c1_up_bx:1; 1026 uint64_t c1_up_wi:1; 1027 uint64_t c1_up_b2:1; 1028 uint64_t c1_up_b1:1; 1029 uint64_t c1_up_b0:1; 1030 uint64_t c0_un_bx:1; 1031 uint64_t c0_un_wi:1; 1032 uint64_t c0_un_b2:1; 1033 uint64_t c0_un_b1:1; 1034 uint64_t c0_un_b0:1; 1035 uint64_t c0_up_bx:1; 1036 uint64_t c0_up_wi:1; 1037 uint64_t c0_up_b2:1; 1038 uint64_t c0_up_b1:1; 1039 uint64_t c0_up_b0:1; 1040 uint64_t c1_hpint:1; 1041 uint64_t c1_pmei:1; 1042 uint64_t c1_wake:1; 1043 uint64_t crs1_dr:1; 1044 uint64_t c1_se:1; 1045 uint64_t crs1_er:1; 1046 uint64_t c1_aeri:1; 1047 uint64_t c0_hpint:1; 1048 uint64_t c0_pmei:1; 1049 uint64_t c0_wake:1; 1050 uint64_t crs0_dr:1; 1051 uint64_t c0_se:1; 1052 uint64_t crs0_er:1; 1053 uint64_t c0_aeri:1; 1054 uint64_t ptime:1; 1055 uint64_t pcnt:1; 1056 uint64_t pidbof:1; 1057 uint64_t psldbof:1; 1058 uint64_t dtime1:1; 1059 uint64_t dtime0:1; 1060 uint64_t dcnt1:1; 1061 uint64_t dcnt0:1; 1062 uint64_t dma1fi:1; 1063 uint64_t dma0fi:1; 1064 uint64_t reserved_8_8:1; 1065 uint64_t dma3dbo:1; 1066 uint64_t dma2dbo:1; 1067 uint64_t dma1dbo:1; 1068 uint64_t dma0dbo:1; 1069 uint64_t iob2big:1; 1070 uint64_t bar0_to:1; 1071 uint64_t rml_wto:1; 1072 uint64_t rml_rto:1; 1073 } cn52xxp1; 1074 struct cvmx_npei_int_enb_s cn56xx; 1075 struct cvmx_npei_int_enb_cn56xxp1 { 1076 uint64_t mio_inta:1; 1077 uint64_t reserved_61_62:2; 1078 uint64_t c1_ldwn:1; 1079 uint64_t c0_ldwn:1; 1080 uint64_t c1_exc:1; 1081 uint64_t c0_exc:1; 1082 uint64_t c1_up_wf:1; 1083 uint64_t c0_up_wf:1; 1084 uint64_t c1_un_wf:1; 1085 uint64_t c0_un_wf:1; 1086 uint64_t c1_un_bx:1; 1087 uint64_t c1_un_wi:1; 1088 uint64_t c1_un_b2:1; 1089 uint64_t c1_un_b1:1; 1090 uint64_t c1_un_b0:1; 1091 uint64_t c1_up_bx:1; 1092 uint64_t c1_up_wi:1; 1093 uint64_t c1_up_b2:1; 1094 uint64_t c1_up_b1:1; 1095 uint64_t c1_up_b0:1; 1096 uint64_t c0_un_bx:1; 1097 uint64_t c0_un_wi:1; 1098 uint64_t c0_un_b2:1; 1099 uint64_t c0_un_b1:1; 1100 uint64_t c0_un_b0:1; 1101 uint64_t c0_up_bx:1; 1102 uint64_t c0_up_wi:1; 1103 uint64_t c0_up_b2:1; 1104 uint64_t c0_up_b1:1; 1105 uint64_t c0_up_b0:1; 1106 uint64_t c1_hpint:1; 1107 uint64_t c1_pmei:1; 1108 uint64_t c1_wake:1; 1109 uint64_t reserved_29_29:1; 1110 uint64_t c1_se:1; 1111 uint64_t reserved_27_27:1; 1112 uint64_t c1_aeri:1; 1113 uint64_t c0_hpint:1; 1114 uint64_t c0_pmei:1; 1115 uint64_t c0_wake:1; 1116 uint64_t reserved_22_22:1; 1117 uint64_t c0_se:1; 1118 uint64_t reserved_20_20:1; 1119 uint64_t c0_aeri:1; 1120 uint64_t ptime:1; 1121 uint64_t pcnt:1; 1122 uint64_t pidbof:1; 1123 uint64_t psldbof:1; 1124 uint64_t dtime1:1; 1125 uint64_t dtime0:1; 1126 uint64_t dcnt1:1; 1127 uint64_t dcnt0:1; 1128 uint64_t dma1fi:1; 1129 uint64_t dma0fi:1; 1130 uint64_t dma4dbo:1; 1131 uint64_t dma3dbo:1; 1132 uint64_t dma2dbo:1; 1133 uint64_t dma1dbo:1; 1134 uint64_t dma0dbo:1; 1135 uint64_t iob2big:1; 1136 uint64_t bar0_to:1; 1137 uint64_t rml_wto:1; 1138 uint64_t rml_rto:1; 1139 } cn56xxp1; 1140 }; 1141 1142 union cvmx_npei_int_enb2 { 1143 uint64_t u64; 1144 struct cvmx_npei_int_enb2_s { 1145 uint64_t reserved_62_63:2; 1146 uint64_t int_a:1; 1147 uint64_t c1_ldwn:1; 1148 uint64_t c0_ldwn:1; 1149 uint64_t c1_exc:1; 1150 uint64_t c0_exc:1; 1151 uint64_t c1_up_wf:1; 1152 uint64_t c0_up_wf:1; 1153 uint64_t c1_un_wf:1; 1154 uint64_t c0_un_wf:1; 1155 uint64_t c1_un_bx:1; 1156 uint64_t c1_un_wi:1; 1157 uint64_t c1_un_b2:1; 1158 uint64_t c1_un_b1:1; 1159 uint64_t c1_un_b0:1; 1160 uint64_t c1_up_bx:1; 1161 uint64_t c1_up_wi:1; 1162 uint64_t c1_up_b2:1; 1163 uint64_t c1_up_b1:1; 1164 uint64_t c1_up_b0:1; 1165 uint64_t c0_un_bx:1; 1166 uint64_t c0_un_wi:1; 1167 uint64_t c0_un_b2:1; 1168 uint64_t c0_un_b1:1; 1169 uint64_t c0_un_b0:1; 1170 uint64_t c0_up_bx:1; 1171 uint64_t c0_up_wi:1; 1172 uint64_t c0_up_b2:1; 1173 uint64_t c0_up_b1:1; 1174 uint64_t c0_up_b0:1; 1175 uint64_t c1_hpint:1; 1176 uint64_t c1_pmei:1; 1177 uint64_t c1_wake:1; 1178 uint64_t crs1_dr:1; 1179 uint64_t c1_se:1; 1180 uint64_t crs1_er:1; 1181 uint64_t c1_aeri:1; 1182 uint64_t c0_hpint:1; 1183 uint64_t c0_pmei:1; 1184 uint64_t c0_wake:1; 1185 uint64_t crs0_dr:1; 1186 uint64_t c0_se:1; 1187 uint64_t crs0_er:1; 1188 uint64_t c0_aeri:1; 1189 uint64_t ptime:1; 1190 uint64_t pcnt:1; 1191 uint64_t pidbof:1; 1192 uint64_t psldbof:1; 1193 uint64_t dtime1:1; 1194 uint64_t dtime0:1; 1195 uint64_t dcnt1:1; 1196 uint64_t dcnt0:1; 1197 uint64_t dma1fi:1; 1198 uint64_t dma0fi:1; 1199 uint64_t dma4dbo:1; 1200 uint64_t dma3dbo:1; 1201 uint64_t dma2dbo:1; 1202 uint64_t dma1dbo:1; 1203 uint64_t dma0dbo:1; 1204 uint64_t iob2big:1; 1205 uint64_t bar0_to:1; 1206 uint64_t rml_wto:1; 1207 uint64_t rml_rto:1; 1208 } s; 1209 struct cvmx_npei_int_enb2_s cn52xx; 1210 struct cvmx_npei_int_enb2_cn52xxp1 { 1211 uint64_t reserved_62_63:2; 1212 uint64_t int_a:1; 1213 uint64_t c1_ldwn:1; 1214 uint64_t c0_ldwn:1; 1215 uint64_t c1_exc:1; 1216 uint64_t c0_exc:1; 1217 uint64_t c1_up_wf:1; 1218 uint64_t c0_up_wf:1; 1219 uint64_t c1_un_wf:1; 1220 uint64_t c0_un_wf:1; 1221 uint64_t c1_un_bx:1; 1222 uint64_t c1_un_wi:1; 1223 uint64_t c1_un_b2:1; 1224 uint64_t c1_un_b1:1; 1225 uint64_t c1_un_b0:1; 1226 uint64_t c1_up_bx:1; 1227 uint64_t c1_up_wi:1; 1228 uint64_t c1_up_b2:1; 1229 uint64_t c1_up_b1:1; 1230 uint64_t c1_up_b0:1; 1231 uint64_t c0_un_bx:1; 1232 uint64_t c0_un_wi:1; 1233 uint64_t c0_un_b2:1; 1234 uint64_t c0_un_b1:1; 1235 uint64_t c0_un_b0:1; 1236 uint64_t c0_up_bx:1; 1237 uint64_t c0_up_wi:1; 1238 uint64_t c0_up_b2:1; 1239 uint64_t c0_up_b1:1; 1240 uint64_t c0_up_b0:1; 1241 uint64_t c1_hpint:1; 1242 uint64_t c1_pmei:1; 1243 uint64_t c1_wake:1; 1244 uint64_t crs1_dr:1; 1245 uint64_t c1_se:1; 1246 uint64_t crs1_er:1; 1247 uint64_t c1_aeri:1; 1248 uint64_t c0_hpint:1; 1249 uint64_t c0_pmei:1; 1250 uint64_t c0_wake:1; 1251 uint64_t crs0_dr:1; 1252 uint64_t c0_se:1; 1253 uint64_t crs0_er:1; 1254 uint64_t c0_aeri:1; 1255 uint64_t ptime:1; 1256 uint64_t pcnt:1; 1257 uint64_t pidbof:1; 1258 uint64_t psldbof:1; 1259 uint64_t dtime1:1; 1260 uint64_t dtime0:1; 1261 uint64_t dcnt1:1; 1262 uint64_t dcnt0:1; 1263 uint64_t dma1fi:1; 1264 uint64_t dma0fi:1; 1265 uint64_t reserved_8_8:1; 1266 uint64_t dma3dbo:1; 1267 uint64_t dma2dbo:1; 1268 uint64_t dma1dbo:1; 1269 uint64_t dma0dbo:1; 1270 uint64_t iob2big:1; 1271 uint64_t bar0_to:1; 1272 uint64_t rml_wto:1; 1273 uint64_t rml_rto:1; 1274 } cn52xxp1; 1275 struct cvmx_npei_int_enb2_s cn56xx; 1276 struct cvmx_npei_int_enb2_cn56xxp1 { 1277 uint64_t reserved_61_63:3; 1278 uint64_t c1_ldwn:1; 1279 uint64_t c0_ldwn:1; 1280 uint64_t c1_exc:1; 1281 uint64_t c0_exc:1; 1282 uint64_t c1_up_wf:1; 1283 uint64_t c0_up_wf:1; 1284 uint64_t c1_un_wf:1; 1285 uint64_t c0_un_wf:1; 1286 uint64_t c1_un_bx:1; 1287 uint64_t c1_un_wi:1; 1288 uint64_t c1_un_b2:1; 1289 uint64_t c1_un_b1:1; 1290 uint64_t c1_un_b0:1; 1291 uint64_t c1_up_bx:1; 1292 uint64_t c1_up_wi:1; 1293 uint64_t c1_up_b2:1; 1294 uint64_t c1_up_b1:1; 1295 uint64_t c1_up_b0:1; 1296 uint64_t c0_un_bx:1; 1297 uint64_t c0_un_wi:1; 1298 uint64_t c0_un_b2:1; 1299 uint64_t c0_un_b1:1; 1300 uint64_t c0_un_b0:1; 1301 uint64_t c0_up_bx:1; 1302 uint64_t c0_up_wi:1; 1303 uint64_t c0_up_b2:1; 1304 uint64_t c0_up_b1:1; 1305 uint64_t c0_up_b0:1; 1306 uint64_t c1_hpint:1; 1307 uint64_t c1_pmei:1; 1308 uint64_t c1_wake:1; 1309 uint64_t reserved_29_29:1; 1310 uint64_t c1_se:1; 1311 uint64_t reserved_27_27:1; 1312 uint64_t c1_aeri:1; 1313 uint64_t c0_hpint:1; 1314 uint64_t c0_pmei:1; 1315 uint64_t c0_wake:1; 1316 uint64_t reserved_22_22:1; 1317 uint64_t c0_se:1; 1318 uint64_t reserved_20_20:1; 1319 uint64_t c0_aeri:1; 1320 uint64_t ptime:1; 1321 uint64_t pcnt:1; 1322 uint64_t pidbof:1; 1323 uint64_t psldbof:1; 1324 uint64_t dtime1:1; 1325 uint64_t dtime0:1; 1326 uint64_t dcnt1:1; 1327 uint64_t dcnt0:1; 1328 uint64_t dma1fi:1; 1329 uint64_t dma0fi:1; 1330 uint64_t dma4dbo:1; 1331 uint64_t dma3dbo:1; 1332 uint64_t dma2dbo:1; 1333 uint64_t dma1dbo:1; 1334 uint64_t dma0dbo:1; 1335 uint64_t iob2big:1; 1336 uint64_t bar0_to:1; 1337 uint64_t rml_wto:1; 1338 uint64_t rml_rto:1; 1339 } cn56xxp1; 1340 }; 1341 1342 union cvmx_npei_int_info { 1343 uint64_t u64; 1344 struct cvmx_npei_int_info_s { 1345 uint64_t reserved_12_63:52; 1346 uint64_t pidbof:6; 1347 uint64_t psldbof:6; 1348 } s; 1349 struct cvmx_npei_int_info_s cn52xx; 1350 struct cvmx_npei_int_info_s cn56xx; 1351 struct cvmx_npei_int_info_s cn56xxp1; 1352 }; 1353 1354 union cvmx_npei_int_sum { 1355 uint64_t u64; 1356 struct cvmx_npei_int_sum_s { 1357 uint64_t mio_inta:1; 1358 uint64_t reserved_62_62:1; 1359 uint64_t int_a:1; 1360 uint64_t c1_ldwn:1; 1361 uint64_t c0_ldwn:1; 1362 uint64_t c1_exc:1; 1363 uint64_t c0_exc:1; 1364 uint64_t c1_up_wf:1; 1365 uint64_t c0_up_wf:1; 1366 uint64_t c1_un_wf:1; 1367 uint64_t c0_un_wf:1; 1368 uint64_t c1_un_bx:1; 1369 uint64_t c1_un_wi:1; 1370 uint64_t c1_un_b2:1; 1371 uint64_t c1_un_b1:1; 1372 uint64_t c1_un_b0:1; 1373 uint64_t c1_up_bx:1; 1374 uint64_t c1_up_wi:1; 1375 uint64_t c1_up_b2:1; 1376 uint64_t c1_up_b1:1; 1377 uint64_t c1_up_b0:1; 1378 uint64_t c0_un_bx:1; 1379 uint64_t c0_un_wi:1; 1380 uint64_t c0_un_b2:1; 1381 uint64_t c0_un_b1:1; 1382 uint64_t c0_un_b0:1; 1383 uint64_t c0_up_bx:1; 1384 uint64_t c0_up_wi:1; 1385 uint64_t c0_up_b2:1; 1386 uint64_t c0_up_b1:1; 1387 uint64_t c0_up_b0:1; 1388 uint64_t c1_hpint:1; 1389 uint64_t c1_pmei:1; 1390 uint64_t c1_wake:1; 1391 uint64_t crs1_dr:1; 1392 uint64_t c1_se:1; 1393 uint64_t crs1_er:1; 1394 uint64_t c1_aeri:1; 1395 uint64_t c0_hpint:1; 1396 uint64_t c0_pmei:1; 1397 uint64_t c0_wake:1; 1398 uint64_t crs0_dr:1; 1399 uint64_t c0_se:1; 1400 uint64_t crs0_er:1; 1401 uint64_t c0_aeri:1; 1402 uint64_t ptime:1; 1403 uint64_t pcnt:1; 1404 uint64_t pidbof:1; 1405 uint64_t psldbof:1; 1406 uint64_t dtime1:1; 1407 uint64_t dtime0:1; 1408 uint64_t dcnt1:1; 1409 uint64_t dcnt0:1; 1410 uint64_t dma1fi:1; 1411 uint64_t dma0fi:1; 1412 uint64_t dma4dbo:1; 1413 uint64_t dma3dbo:1; 1414 uint64_t dma2dbo:1; 1415 uint64_t dma1dbo:1; 1416 uint64_t dma0dbo:1; 1417 uint64_t iob2big:1; 1418 uint64_t bar0_to:1; 1419 uint64_t rml_wto:1; 1420 uint64_t rml_rto:1; 1421 } s; 1422 struct cvmx_npei_int_sum_s cn52xx; 1423 struct cvmx_npei_int_sum_cn52xxp1 { 1424 uint64_t mio_inta:1; 1425 uint64_t reserved_62_62:1; 1426 uint64_t int_a:1; 1427 uint64_t c1_ldwn:1; 1428 uint64_t c0_ldwn:1; 1429 uint64_t c1_exc:1; 1430 uint64_t c0_exc:1; 1431 uint64_t c1_up_wf:1; 1432 uint64_t c0_up_wf:1; 1433 uint64_t c1_un_wf:1; 1434 uint64_t c0_un_wf:1; 1435 uint64_t c1_un_bx:1; 1436 uint64_t c1_un_wi:1; 1437 uint64_t c1_un_b2:1; 1438 uint64_t c1_un_b1:1; 1439 uint64_t c1_un_b0:1; 1440 uint64_t c1_up_bx:1; 1441 uint64_t c1_up_wi:1; 1442 uint64_t c1_up_b2:1; 1443 uint64_t c1_up_b1:1; 1444 uint64_t c1_up_b0:1; 1445 uint64_t c0_un_bx:1; 1446 uint64_t c0_un_wi:1; 1447 uint64_t c0_un_b2:1; 1448 uint64_t c0_un_b1:1; 1449 uint64_t c0_un_b0:1; 1450 uint64_t c0_up_bx:1; 1451 uint64_t c0_up_wi:1; 1452 uint64_t c0_up_b2:1; 1453 uint64_t c0_up_b1:1; 1454 uint64_t c0_up_b0:1; 1455 uint64_t c1_hpint:1; 1456 uint64_t c1_pmei:1; 1457 uint64_t c1_wake:1; 1458 uint64_t crs1_dr:1; 1459 uint64_t c1_se:1; 1460 uint64_t crs1_er:1; 1461 uint64_t c1_aeri:1; 1462 uint64_t c0_hpint:1; 1463 uint64_t c0_pmei:1; 1464 uint64_t c0_wake:1; 1465 uint64_t crs0_dr:1; 1466 uint64_t c0_se:1; 1467 uint64_t crs0_er:1; 1468 uint64_t c0_aeri:1; 1469 uint64_t reserved_15_18:4; 1470 uint64_t dtime1:1; 1471 uint64_t dtime0:1; 1472 uint64_t dcnt1:1; 1473 uint64_t dcnt0:1; 1474 uint64_t dma1fi:1; 1475 uint64_t dma0fi:1; 1476 uint64_t reserved_8_8:1; 1477 uint64_t dma3dbo:1; 1478 uint64_t dma2dbo:1; 1479 uint64_t dma1dbo:1; 1480 uint64_t dma0dbo:1; 1481 uint64_t iob2big:1; 1482 uint64_t bar0_to:1; 1483 uint64_t rml_wto:1; 1484 uint64_t rml_rto:1; 1485 } cn52xxp1; 1486 struct cvmx_npei_int_sum_s cn56xx; 1487 struct cvmx_npei_int_sum_cn56xxp1 { 1488 uint64_t mio_inta:1; 1489 uint64_t reserved_61_62:2; 1490 uint64_t c1_ldwn:1; 1491 uint64_t c0_ldwn:1; 1492 uint64_t c1_exc:1; 1493 uint64_t c0_exc:1; 1494 uint64_t c1_up_wf:1; 1495 uint64_t c0_up_wf:1; 1496 uint64_t c1_un_wf:1; 1497 uint64_t c0_un_wf:1; 1498 uint64_t c1_un_bx:1; 1499 uint64_t c1_un_wi:1; 1500 uint64_t c1_un_b2:1; 1501 uint64_t c1_un_b1:1; 1502 uint64_t c1_un_b0:1; 1503 uint64_t c1_up_bx:1; 1504 uint64_t c1_up_wi:1; 1505 uint64_t c1_up_b2:1; 1506 uint64_t c1_up_b1:1; 1507 uint64_t c1_up_b0:1; 1508 uint64_t c0_un_bx:1; 1509 uint64_t c0_un_wi:1; 1510 uint64_t c0_un_b2:1; 1511 uint64_t c0_un_b1:1; 1512 uint64_t c0_un_b0:1; 1513 uint64_t c0_up_bx:1; 1514 uint64_t c0_up_wi:1; 1515 uint64_t c0_up_b2:1; 1516 uint64_t c0_up_b1:1; 1517 uint64_t c0_up_b0:1; 1518 uint64_t c1_hpint:1; 1519 uint64_t c1_pmei:1; 1520 uint64_t c1_wake:1; 1521 uint64_t reserved_29_29:1; 1522 uint64_t c1_se:1; 1523 uint64_t reserved_27_27:1; 1524 uint64_t c1_aeri:1; 1525 uint64_t c0_hpint:1; 1526 uint64_t c0_pmei:1; 1527 uint64_t c0_wake:1; 1528 uint64_t reserved_22_22:1; 1529 uint64_t c0_se:1; 1530 uint64_t reserved_20_20:1; 1531 uint64_t c0_aeri:1; 1532 uint64_t reserved_15_18:4; 1533 uint64_t dtime1:1; 1534 uint64_t dtime0:1; 1535 uint64_t dcnt1:1; 1536 uint64_t dcnt0:1; 1537 uint64_t dma1fi:1; 1538 uint64_t dma0fi:1; 1539 uint64_t dma4dbo:1; 1540 uint64_t dma3dbo:1; 1541 uint64_t dma2dbo:1; 1542 uint64_t dma1dbo:1; 1543 uint64_t dma0dbo:1; 1544 uint64_t iob2big:1; 1545 uint64_t bar0_to:1; 1546 uint64_t rml_wto:1; 1547 uint64_t rml_rto:1; 1548 } cn56xxp1; 1549 }; 1550 1551 union cvmx_npei_int_sum2 { 1552 uint64_t u64; 1553 struct cvmx_npei_int_sum2_s { 1554 uint64_t mio_inta:1; 1555 uint64_t reserved_62_62:1; 1556 uint64_t int_a:1; 1557 uint64_t c1_ldwn:1; 1558 uint64_t c0_ldwn:1; 1559 uint64_t c1_exc:1; 1560 uint64_t c0_exc:1; 1561 uint64_t c1_up_wf:1; 1562 uint64_t c0_up_wf:1; 1563 uint64_t c1_un_wf:1; 1564 uint64_t c0_un_wf:1; 1565 uint64_t c1_un_bx:1; 1566 uint64_t c1_un_wi:1; 1567 uint64_t c1_un_b2:1; 1568 uint64_t c1_un_b1:1; 1569 uint64_t c1_un_b0:1; 1570 uint64_t c1_up_bx:1; 1571 uint64_t c1_up_wi:1; 1572 uint64_t c1_up_b2:1; 1573 uint64_t c1_up_b1:1; 1574 uint64_t c1_up_b0:1; 1575 uint64_t c0_un_bx:1; 1576 uint64_t c0_un_wi:1; 1577 uint64_t c0_un_b2:1; 1578 uint64_t c0_un_b1:1; 1579 uint64_t c0_un_b0:1; 1580 uint64_t c0_up_bx:1; 1581 uint64_t c0_up_wi:1; 1582 uint64_t c0_up_b2:1; 1583 uint64_t c0_up_b1:1; 1584 uint64_t c0_up_b0:1; 1585 uint64_t c1_hpint:1; 1586 uint64_t c1_pmei:1; 1587 uint64_t c1_wake:1; 1588 uint64_t crs1_dr:1; 1589 uint64_t c1_se:1; 1590 uint64_t crs1_er:1; 1591 uint64_t c1_aeri:1; 1592 uint64_t c0_hpint:1; 1593 uint64_t c0_pmei:1; 1594 uint64_t c0_wake:1; 1595 uint64_t crs0_dr:1; 1596 uint64_t c0_se:1; 1597 uint64_t crs0_er:1; 1598 uint64_t c0_aeri:1; 1599 uint64_t reserved_15_18:4; 1600 uint64_t dtime1:1; 1601 uint64_t dtime0:1; 1602 uint64_t dcnt1:1; 1603 uint64_t dcnt0:1; 1604 uint64_t dma1fi:1; 1605 uint64_t dma0fi:1; 1606 uint64_t reserved_8_8:1; 1607 uint64_t dma3dbo:1; 1608 uint64_t dma2dbo:1; 1609 uint64_t dma1dbo:1; 1610 uint64_t dma0dbo:1; 1611 uint64_t iob2big:1; 1612 uint64_t bar0_to:1; 1613 uint64_t rml_wto:1; 1614 uint64_t rml_rto:1; 1615 } s; 1616 struct cvmx_npei_int_sum2_s cn52xx; 1617 struct cvmx_npei_int_sum2_s cn52xxp1; 1618 struct cvmx_npei_int_sum2_s cn56xx; 1619 }; 1620 1621 union cvmx_npei_last_win_rdata0 { 1622 uint64_t u64; 1623 struct cvmx_npei_last_win_rdata0_s { 1624 uint64_t data:64; 1625 } s; 1626 struct cvmx_npei_last_win_rdata0_s cn52xx; 1627 struct cvmx_npei_last_win_rdata0_s cn52xxp1; 1628 struct cvmx_npei_last_win_rdata0_s cn56xx; 1629 struct cvmx_npei_last_win_rdata0_s cn56xxp1; 1630 }; 1631 1632 union cvmx_npei_last_win_rdata1 { 1633 uint64_t u64; 1634 struct cvmx_npei_last_win_rdata1_s { 1635 uint64_t data:64; 1636 } s; 1637 struct cvmx_npei_last_win_rdata1_s cn52xx; 1638 struct cvmx_npei_last_win_rdata1_s cn52xxp1; 1639 struct cvmx_npei_last_win_rdata1_s cn56xx; 1640 struct cvmx_npei_last_win_rdata1_s cn56xxp1; 1641 }; 1642 1643 union cvmx_npei_mem_access_ctl { 1644 uint64_t u64; 1645 struct cvmx_npei_mem_access_ctl_s { 1646 uint64_t reserved_14_63:50; 1647 uint64_t max_word:4; 1648 uint64_t timer:10; 1649 } s; 1650 struct cvmx_npei_mem_access_ctl_s cn52xx; 1651 struct cvmx_npei_mem_access_ctl_s cn52xxp1; 1652 struct cvmx_npei_mem_access_ctl_s cn56xx; 1653 struct cvmx_npei_mem_access_ctl_s cn56xxp1; 1654 }; 1655 1656 union cvmx_npei_mem_access_subidx { 1657 uint64_t u64; 1658 struct cvmx_npei_mem_access_subidx_s { 1659 uint64_t reserved_42_63:22; 1660 uint64_t zero:1; 1661 uint64_t port:2; 1662 uint64_t nmerge:1; 1663 uint64_t esr:2; 1664 uint64_t esw:2; 1665 uint64_t nsr:1; 1666 uint64_t nsw:1; 1667 uint64_t ror:1; 1668 uint64_t row:1; 1669 uint64_t ba:30; 1670 } s; 1671 struct cvmx_npei_mem_access_subidx_s cn52xx; 1672 struct cvmx_npei_mem_access_subidx_s cn52xxp1; 1673 struct cvmx_npei_mem_access_subidx_s cn56xx; 1674 struct cvmx_npei_mem_access_subidx_s cn56xxp1; 1675 }; 1676 1677 union cvmx_npei_msi_enb0 { 1678 uint64_t u64; 1679 struct cvmx_npei_msi_enb0_s { 1680 uint64_t enb:64; 1681 } s; 1682 struct cvmx_npei_msi_enb0_s cn52xx; 1683 struct cvmx_npei_msi_enb0_s cn52xxp1; 1684 struct cvmx_npei_msi_enb0_s cn56xx; 1685 struct cvmx_npei_msi_enb0_s cn56xxp1; 1686 }; 1687 1688 union cvmx_npei_msi_enb1 { 1689 uint64_t u64; 1690 struct cvmx_npei_msi_enb1_s { 1691 uint64_t enb:64; 1692 } s; 1693 struct cvmx_npei_msi_enb1_s cn52xx; 1694 struct cvmx_npei_msi_enb1_s cn52xxp1; 1695 struct cvmx_npei_msi_enb1_s cn56xx; 1696 struct cvmx_npei_msi_enb1_s cn56xxp1; 1697 }; 1698 1699 union cvmx_npei_msi_enb2 { 1700 uint64_t u64; 1701 struct cvmx_npei_msi_enb2_s { 1702 uint64_t enb:64; 1703 } s; 1704 struct cvmx_npei_msi_enb2_s cn52xx; 1705 struct cvmx_npei_msi_enb2_s cn52xxp1; 1706 struct cvmx_npei_msi_enb2_s cn56xx; 1707 struct cvmx_npei_msi_enb2_s cn56xxp1; 1708 }; 1709 1710 union cvmx_npei_msi_enb3 { 1711 uint64_t u64; 1712 struct cvmx_npei_msi_enb3_s { 1713 uint64_t enb:64; 1714 } s; 1715 struct cvmx_npei_msi_enb3_s cn52xx; 1716 struct cvmx_npei_msi_enb3_s cn52xxp1; 1717 struct cvmx_npei_msi_enb3_s cn56xx; 1718 struct cvmx_npei_msi_enb3_s cn56xxp1; 1719 }; 1720 1721 union cvmx_npei_msi_rcv0 { 1722 uint64_t u64; 1723 struct cvmx_npei_msi_rcv0_s { 1724 uint64_t intr:64; 1725 } s; 1726 struct cvmx_npei_msi_rcv0_s cn52xx; 1727 struct cvmx_npei_msi_rcv0_s cn52xxp1; 1728 struct cvmx_npei_msi_rcv0_s cn56xx; 1729 struct cvmx_npei_msi_rcv0_s cn56xxp1; 1730 }; 1731 1732 union cvmx_npei_msi_rcv1 { 1733 uint64_t u64; 1734 struct cvmx_npei_msi_rcv1_s { 1735 uint64_t intr:64; 1736 } s; 1737 struct cvmx_npei_msi_rcv1_s cn52xx; 1738 struct cvmx_npei_msi_rcv1_s cn52xxp1; 1739 struct cvmx_npei_msi_rcv1_s cn56xx; 1740 struct cvmx_npei_msi_rcv1_s cn56xxp1; 1741 }; 1742 1743 union cvmx_npei_msi_rcv2 { 1744 uint64_t u64; 1745 struct cvmx_npei_msi_rcv2_s { 1746 uint64_t intr:64; 1747 } s; 1748 struct cvmx_npei_msi_rcv2_s cn52xx; 1749 struct cvmx_npei_msi_rcv2_s cn52xxp1; 1750 struct cvmx_npei_msi_rcv2_s cn56xx; 1751 struct cvmx_npei_msi_rcv2_s cn56xxp1; 1752 }; 1753 1754 union cvmx_npei_msi_rcv3 { 1755 uint64_t u64; 1756 struct cvmx_npei_msi_rcv3_s { 1757 uint64_t intr:64; 1758 } s; 1759 struct cvmx_npei_msi_rcv3_s cn52xx; 1760 struct cvmx_npei_msi_rcv3_s cn52xxp1; 1761 struct cvmx_npei_msi_rcv3_s cn56xx; 1762 struct cvmx_npei_msi_rcv3_s cn56xxp1; 1763 }; 1764 1765 union cvmx_npei_msi_rd_map { 1766 uint64_t u64; 1767 struct cvmx_npei_msi_rd_map_s { 1768 uint64_t reserved_16_63:48; 1769 uint64_t rd_int:8; 1770 uint64_t msi_int:8; 1771 } s; 1772 struct cvmx_npei_msi_rd_map_s cn52xx; 1773 struct cvmx_npei_msi_rd_map_s cn52xxp1; 1774 struct cvmx_npei_msi_rd_map_s cn56xx; 1775 struct cvmx_npei_msi_rd_map_s cn56xxp1; 1776 }; 1777 1778 union cvmx_npei_msi_w1c_enb0 { 1779 uint64_t u64; 1780 struct cvmx_npei_msi_w1c_enb0_s { 1781 uint64_t clr:64; 1782 } s; 1783 struct cvmx_npei_msi_w1c_enb0_s cn52xx; 1784 struct cvmx_npei_msi_w1c_enb0_s cn56xx; 1785 }; 1786 1787 union cvmx_npei_msi_w1c_enb1 { 1788 uint64_t u64; 1789 struct cvmx_npei_msi_w1c_enb1_s { 1790 uint64_t clr:64; 1791 } s; 1792 struct cvmx_npei_msi_w1c_enb1_s cn52xx; 1793 struct cvmx_npei_msi_w1c_enb1_s cn56xx; 1794 }; 1795 1796 union cvmx_npei_msi_w1c_enb2 { 1797 uint64_t u64; 1798 struct cvmx_npei_msi_w1c_enb2_s { 1799 uint64_t clr:64; 1800 } s; 1801 struct cvmx_npei_msi_w1c_enb2_s cn52xx; 1802 struct cvmx_npei_msi_w1c_enb2_s cn56xx; 1803 }; 1804 1805 union cvmx_npei_msi_w1c_enb3 { 1806 uint64_t u64; 1807 struct cvmx_npei_msi_w1c_enb3_s { 1808 uint64_t clr:64; 1809 } s; 1810 struct cvmx_npei_msi_w1c_enb3_s cn52xx; 1811 struct cvmx_npei_msi_w1c_enb3_s cn56xx; 1812 }; 1813 1814 union cvmx_npei_msi_w1s_enb0 { 1815 uint64_t u64; 1816 struct cvmx_npei_msi_w1s_enb0_s { 1817 uint64_t set:64; 1818 } s; 1819 struct cvmx_npei_msi_w1s_enb0_s cn52xx; 1820 struct cvmx_npei_msi_w1s_enb0_s cn56xx; 1821 }; 1822 1823 union cvmx_npei_msi_w1s_enb1 { 1824 uint64_t u64; 1825 struct cvmx_npei_msi_w1s_enb1_s { 1826 uint64_t set:64; 1827 } s; 1828 struct cvmx_npei_msi_w1s_enb1_s cn52xx; 1829 struct cvmx_npei_msi_w1s_enb1_s cn56xx; 1830 }; 1831 1832 union cvmx_npei_msi_w1s_enb2 { 1833 uint64_t u64; 1834 struct cvmx_npei_msi_w1s_enb2_s { 1835 uint64_t set:64; 1836 } s; 1837 struct cvmx_npei_msi_w1s_enb2_s cn52xx; 1838 struct cvmx_npei_msi_w1s_enb2_s cn56xx; 1839 }; 1840 1841 union cvmx_npei_msi_w1s_enb3 { 1842 uint64_t u64; 1843 struct cvmx_npei_msi_w1s_enb3_s { 1844 uint64_t set:64; 1845 } s; 1846 struct cvmx_npei_msi_w1s_enb3_s cn52xx; 1847 struct cvmx_npei_msi_w1s_enb3_s cn56xx; 1848 }; 1849 1850 union cvmx_npei_msi_wr_map { 1851 uint64_t u64; 1852 struct cvmx_npei_msi_wr_map_s { 1853 uint64_t reserved_16_63:48; 1854 uint64_t ciu_int:8; 1855 uint64_t msi_int:8; 1856 } s; 1857 struct cvmx_npei_msi_wr_map_s cn52xx; 1858 struct cvmx_npei_msi_wr_map_s cn52xxp1; 1859 struct cvmx_npei_msi_wr_map_s cn56xx; 1860 struct cvmx_npei_msi_wr_map_s cn56xxp1; 1861 }; 1862 1863 union cvmx_npei_pcie_credit_cnt { 1864 uint64_t u64; 1865 struct cvmx_npei_pcie_credit_cnt_s { 1866 uint64_t reserved_48_63:16; 1867 uint64_t p1_ccnt:8; 1868 uint64_t p1_ncnt:8; 1869 uint64_t p1_pcnt:8; 1870 uint64_t p0_ccnt:8; 1871 uint64_t p0_ncnt:8; 1872 uint64_t p0_pcnt:8; 1873 } s; 1874 struct cvmx_npei_pcie_credit_cnt_s cn52xx; 1875 struct cvmx_npei_pcie_credit_cnt_s cn56xx; 1876 }; 1877 1878 union cvmx_npei_pcie_msi_rcv { 1879 uint64_t u64; 1880 struct cvmx_npei_pcie_msi_rcv_s { 1881 uint64_t reserved_8_63:56; 1882 uint64_t intr:8; 1883 } s; 1884 struct cvmx_npei_pcie_msi_rcv_s cn52xx; 1885 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1; 1886 struct cvmx_npei_pcie_msi_rcv_s cn56xx; 1887 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1; 1888 }; 1889 1890 union cvmx_npei_pcie_msi_rcv_b1 { 1891 uint64_t u64; 1892 struct cvmx_npei_pcie_msi_rcv_b1_s { 1893 uint64_t reserved_16_63:48; 1894 uint64_t intr:8; 1895 uint64_t reserved_0_7:8; 1896 } s; 1897 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx; 1898 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1; 1899 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx; 1900 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1; 1901 }; 1902 1903 union cvmx_npei_pcie_msi_rcv_b2 { 1904 uint64_t u64; 1905 struct cvmx_npei_pcie_msi_rcv_b2_s { 1906 uint64_t reserved_24_63:40; 1907 uint64_t intr:8; 1908 uint64_t reserved_0_15:16; 1909 } s; 1910 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx; 1911 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1; 1912 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx; 1913 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1; 1914 }; 1915 1916 union cvmx_npei_pcie_msi_rcv_b3 { 1917 uint64_t u64; 1918 struct cvmx_npei_pcie_msi_rcv_b3_s { 1919 uint64_t reserved_32_63:32; 1920 uint64_t intr:8; 1921 uint64_t reserved_0_23:24; 1922 } s; 1923 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx; 1924 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1; 1925 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx; 1926 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1; 1927 }; 1928 1929 union cvmx_npei_pktx_cnts { 1930 uint64_t u64; 1931 struct cvmx_npei_pktx_cnts_s { 1932 uint64_t reserved_54_63:10; 1933 uint64_t timer:22; 1934 uint64_t cnt:32; 1935 } s; 1936 struct cvmx_npei_pktx_cnts_s cn52xx; 1937 struct cvmx_npei_pktx_cnts_s cn56xx; 1938 }; 1939 1940 union cvmx_npei_pktx_in_bp { 1941 uint64_t u64; 1942 struct cvmx_npei_pktx_in_bp_s { 1943 uint64_t wmark:32; 1944 uint64_t cnt:32; 1945 } s; 1946 struct cvmx_npei_pktx_in_bp_s cn52xx; 1947 struct cvmx_npei_pktx_in_bp_s cn56xx; 1948 }; 1949 1950 union cvmx_npei_pktx_instr_baddr { 1951 uint64_t u64; 1952 struct cvmx_npei_pktx_instr_baddr_s { 1953 uint64_t addr:61; 1954 uint64_t reserved_0_2:3; 1955 } s; 1956 struct cvmx_npei_pktx_instr_baddr_s cn52xx; 1957 struct cvmx_npei_pktx_instr_baddr_s cn56xx; 1958 }; 1959 1960 union cvmx_npei_pktx_instr_baoff_dbell { 1961 uint64_t u64; 1962 struct cvmx_npei_pktx_instr_baoff_dbell_s { 1963 uint64_t aoff:32; 1964 uint64_t dbell:32; 1965 } s; 1966 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; 1967 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; 1968 }; 1969 1970 union cvmx_npei_pktx_instr_fifo_rsize { 1971 uint64_t u64; 1972 struct cvmx_npei_pktx_instr_fifo_rsize_s { 1973 uint64_t max:9; 1974 uint64_t rrp:9; 1975 uint64_t wrp:9; 1976 uint64_t fcnt:5; 1977 uint64_t rsize:32; 1978 } s; 1979 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; 1980 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; 1981 }; 1982 1983 union cvmx_npei_pktx_instr_header { 1984 uint64_t u64; 1985 struct cvmx_npei_pktx_instr_header_s { 1986 uint64_t reserved_44_63:20; 1987 uint64_t pbp:1; 1988 uint64_t reserved_38_42:5; 1989 uint64_t rparmode:2; 1990 uint64_t reserved_35_35:1; 1991 uint64_t rskp_len:7; 1992 uint64_t reserved_22_27:6; 1993 uint64_t use_ihdr:1; 1994 uint64_t reserved_16_20:5; 1995 uint64_t par_mode:2; 1996 uint64_t reserved_13_13:1; 1997 uint64_t skp_len:7; 1998 uint64_t reserved_0_5:6; 1999 } s; 2000 struct cvmx_npei_pktx_instr_header_s cn52xx; 2001 struct cvmx_npei_pktx_instr_header_s cn56xx; 2002 }; 2003 2004 union cvmx_npei_pktx_slist_baddr { 2005 uint64_t u64; 2006 struct cvmx_npei_pktx_slist_baddr_s { 2007 uint64_t addr:60; 2008 uint64_t reserved_0_3:4; 2009 } s; 2010 struct cvmx_npei_pktx_slist_baddr_s cn52xx; 2011 struct cvmx_npei_pktx_slist_baddr_s cn56xx; 2012 }; 2013 2014 union cvmx_npei_pktx_slist_baoff_dbell { 2015 uint64_t u64; 2016 struct cvmx_npei_pktx_slist_baoff_dbell_s { 2017 uint64_t aoff:32; 2018 uint64_t dbell:32; 2019 } s; 2020 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; 2021 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; 2022 }; 2023 2024 union cvmx_npei_pktx_slist_fifo_rsize { 2025 uint64_t u64; 2026 struct cvmx_npei_pktx_slist_fifo_rsize_s { 2027 uint64_t reserved_32_63:32; 2028 uint64_t rsize:32; 2029 } s; 2030 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; 2031 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; 2032 }; 2033 2034 union cvmx_npei_pkt_cnt_int { 2035 uint64_t u64; 2036 struct cvmx_npei_pkt_cnt_int_s { 2037 uint64_t reserved_32_63:32; 2038 uint64_t port:32; 2039 } s; 2040 struct cvmx_npei_pkt_cnt_int_s cn52xx; 2041 struct cvmx_npei_pkt_cnt_int_s cn56xx; 2042 }; 2043 2044 union cvmx_npei_pkt_cnt_int_enb { 2045 uint64_t u64; 2046 struct cvmx_npei_pkt_cnt_int_enb_s { 2047 uint64_t reserved_32_63:32; 2048 uint64_t port:32; 2049 } s; 2050 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; 2051 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; 2052 }; 2053 2054 union cvmx_npei_pkt_data_out_es { 2055 uint64_t u64; 2056 struct cvmx_npei_pkt_data_out_es_s { 2057 uint64_t es:64; 2058 } s; 2059 struct cvmx_npei_pkt_data_out_es_s cn52xx; 2060 struct cvmx_npei_pkt_data_out_es_s cn56xx; 2061 }; 2062 2063 union cvmx_npei_pkt_data_out_ns { 2064 uint64_t u64; 2065 struct cvmx_npei_pkt_data_out_ns_s { 2066 uint64_t reserved_32_63:32; 2067 uint64_t nsr:32; 2068 } s; 2069 struct cvmx_npei_pkt_data_out_ns_s cn52xx; 2070 struct cvmx_npei_pkt_data_out_ns_s cn56xx; 2071 }; 2072 2073 union cvmx_npei_pkt_data_out_ror { 2074 uint64_t u64; 2075 struct cvmx_npei_pkt_data_out_ror_s { 2076 uint64_t reserved_32_63:32; 2077 uint64_t ror:32; 2078 } s; 2079 struct cvmx_npei_pkt_data_out_ror_s cn52xx; 2080 struct cvmx_npei_pkt_data_out_ror_s cn56xx; 2081 }; 2082 2083 union cvmx_npei_pkt_dpaddr { 2084 uint64_t u64; 2085 struct cvmx_npei_pkt_dpaddr_s { 2086 uint64_t reserved_32_63:32; 2087 uint64_t dptr:32; 2088 } s; 2089 struct cvmx_npei_pkt_dpaddr_s cn52xx; 2090 struct cvmx_npei_pkt_dpaddr_s cn56xx; 2091 }; 2092 2093 union cvmx_npei_pkt_in_bp { 2094 uint64_t u64; 2095 struct cvmx_npei_pkt_in_bp_s { 2096 uint64_t reserved_32_63:32; 2097 uint64_t bp:32; 2098 } s; 2099 struct cvmx_npei_pkt_in_bp_s cn52xx; 2100 struct cvmx_npei_pkt_in_bp_s cn56xx; 2101 }; 2102 2103 union cvmx_npei_pkt_in_donex_cnts { 2104 uint64_t u64; 2105 struct cvmx_npei_pkt_in_donex_cnts_s { 2106 uint64_t reserved_32_63:32; 2107 uint64_t cnt:32; 2108 } s; 2109 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; 2110 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; 2111 }; 2112 2113 union cvmx_npei_pkt_in_instr_counts { 2114 uint64_t u64; 2115 struct cvmx_npei_pkt_in_instr_counts_s { 2116 uint64_t wr_cnt:32; 2117 uint64_t rd_cnt:32; 2118 } s; 2119 struct cvmx_npei_pkt_in_instr_counts_s cn52xx; 2120 struct cvmx_npei_pkt_in_instr_counts_s cn56xx; 2121 }; 2122 2123 union cvmx_npei_pkt_in_pcie_port { 2124 uint64_t u64; 2125 struct cvmx_npei_pkt_in_pcie_port_s { 2126 uint64_t pp:64; 2127 } s; 2128 struct cvmx_npei_pkt_in_pcie_port_s cn52xx; 2129 struct cvmx_npei_pkt_in_pcie_port_s cn56xx; 2130 }; 2131 2132 union cvmx_npei_pkt_input_control { 2133 uint64_t u64; 2134 struct cvmx_npei_pkt_input_control_s { 2135 uint64_t reserved_23_63:41; 2136 uint64_t pkt_rr:1; 2137 uint64_t pbp_dhi:13; 2138 uint64_t d_nsr:1; 2139 uint64_t d_esr:2; 2140 uint64_t d_ror:1; 2141 uint64_t use_csr:1; 2142 uint64_t nsr:1; 2143 uint64_t esr:2; 2144 uint64_t ror:1; 2145 } s; 2146 struct cvmx_npei_pkt_input_control_s cn52xx; 2147 struct cvmx_npei_pkt_input_control_s cn56xx; 2148 }; 2149 2150 union cvmx_npei_pkt_instr_enb { 2151 uint64_t u64; 2152 struct cvmx_npei_pkt_instr_enb_s { 2153 uint64_t reserved_32_63:32; 2154 uint64_t enb:32; 2155 } s; 2156 struct cvmx_npei_pkt_instr_enb_s cn52xx; 2157 struct cvmx_npei_pkt_instr_enb_s cn56xx; 2158 }; 2159 2160 union cvmx_npei_pkt_instr_rd_size { 2161 uint64_t u64; 2162 struct cvmx_npei_pkt_instr_rd_size_s { 2163 uint64_t rdsize:64; 2164 } s; 2165 struct cvmx_npei_pkt_instr_rd_size_s cn52xx; 2166 struct cvmx_npei_pkt_instr_rd_size_s cn56xx; 2167 }; 2168 2169 union cvmx_npei_pkt_instr_size { 2170 uint64_t u64; 2171 struct cvmx_npei_pkt_instr_size_s { 2172 uint64_t reserved_32_63:32; 2173 uint64_t is_64b:32; 2174 } s; 2175 struct cvmx_npei_pkt_instr_size_s cn52xx; 2176 struct cvmx_npei_pkt_instr_size_s cn56xx; 2177 }; 2178 2179 union cvmx_npei_pkt_int_levels { 2180 uint64_t u64; 2181 struct cvmx_npei_pkt_int_levels_s { 2182 uint64_t reserved_54_63:10; 2183 uint64_t time:22; 2184 uint64_t cnt:32; 2185 } s; 2186 struct cvmx_npei_pkt_int_levels_s cn52xx; 2187 struct cvmx_npei_pkt_int_levels_s cn56xx; 2188 }; 2189 2190 union cvmx_npei_pkt_iptr { 2191 uint64_t u64; 2192 struct cvmx_npei_pkt_iptr_s { 2193 uint64_t reserved_32_63:32; 2194 uint64_t iptr:32; 2195 } s; 2196 struct cvmx_npei_pkt_iptr_s cn52xx; 2197 struct cvmx_npei_pkt_iptr_s cn56xx; 2198 }; 2199 2200 union cvmx_npei_pkt_out_bmode { 2201 uint64_t u64; 2202 struct cvmx_npei_pkt_out_bmode_s { 2203 uint64_t reserved_32_63:32; 2204 uint64_t bmode:32; 2205 } s; 2206 struct cvmx_npei_pkt_out_bmode_s cn52xx; 2207 struct cvmx_npei_pkt_out_bmode_s cn56xx; 2208 }; 2209 2210 union cvmx_npei_pkt_out_enb { 2211 uint64_t u64; 2212 struct cvmx_npei_pkt_out_enb_s { 2213 uint64_t reserved_32_63:32; 2214 uint64_t enb:32; 2215 } s; 2216 struct cvmx_npei_pkt_out_enb_s cn52xx; 2217 struct cvmx_npei_pkt_out_enb_s cn56xx; 2218 }; 2219 2220 union cvmx_npei_pkt_output_wmark { 2221 uint64_t u64; 2222 struct cvmx_npei_pkt_output_wmark_s { 2223 uint64_t reserved_32_63:32; 2224 uint64_t wmark:32; 2225 } s; 2226 struct cvmx_npei_pkt_output_wmark_s cn52xx; 2227 struct cvmx_npei_pkt_output_wmark_s cn56xx; 2228 }; 2229 2230 union cvmx_npei_pkt_pcie_port { 2231 uint64_t u64; 2232 struct cvmx_npei_pkt_pcie_port_s { 2233 uint64_t pp:64; 2234 } s; 2235 struct cvmx_npei_pkt_pcie_port_s cn52xx; 2236 struct cvmx_npei_pkt_pcie_port_s cn56xx; 2237 }; 2238 2239 union cvmx_npei_pkt_port_in_rst { 2240 uint64_t u64; 2241 struct cvmx_npei_pkt_port_in_rst_s { 2242 uint64_t in_rst:32; 2243 uint64_t out_rst:32; 2244 } s; 2245 struct cvmx_npei_pkt_port_in_rst_s cn52xx; 2246 struct cvmx_npei_pkt_port_in_rst_s cn56xx; 2247 }; 2248 2249 union cvmx_npei_pkt_slist_es { 2250 uint64_t u64; 2251 struct cvmx_npei_pkt_slist_es_s { 2252 uint64_t es:64; 2253 } s; 2254 struct cvmx_npei_pkt_slist_es_s cn52xx; 2255 struct cvmx_npei_pkt_slist_es_s cn56xx; 2256 }; 2257 2258 union cvmx_npei_pkt_slist_id_size { 2259 uint64_t u64; 2260 struct cvmx_npei_pkt_slist_id_size_s { 2261 uint64_t reserved_23_63:41; 2262 uint64_t isize:7; 2263 uint64_t bsize:16; 2264 } s; 2265 struct cvmx_npei_pkt_slist_id_size_s cn52xx; 2266 struct cvmx_npei_pkt_slist_id_size_s cn56xx; 2267 }; 2268 2269 union cvmx_npei_pkt_slist_ns { 2270 uint64_t u64; 2271 struct cvmx_npei_pkt_slist_ns_s { 2272 uint64_t reserved_32_63:32; 2273 uint64_t nsr:32; 2274 } s; 2275 struct cvmx_npei_pkt_slist_ns_s cn52xx; 2276 struct cvmx_npei_pkt_slist_ns_s cn56xx; 2277 }; 2278 2279 union cvmx_npei_pkt_slist_ror { 2280 uint64_t u64; 2281 struct cvmx_npei_pkt_slist_ror_s { 2282 uint64_t reserved_32_63:32; 2283 uint64_t ror:32; 2284 } s; 2285 struct cvmx_npei_pkt_slist_ror_s cn52xx; 2286 struct cvmx_npei_pkt_slist_ror_s cn56xx; 2287 }; 2288 2289 union cvmx_npei_pkt_time_int { 2290 uint64_t u64; 2291 struct cvmx_npei_pkt_time_int_s { 2292 uint64_t reserved_32_63:32; 2293 uint64_t port:32; 2294 } s; 2295 struct cvmx_npei_pkt_time_int_s cn52xx; 2296 struct cvmx_npei_pkt_time_int_s cn56xx; 2297 }; 2298 2299 union cvmx_npei_pkt_time_int_enb { 2300 uint64_t u64; 2301 struct cvmx_npei_pkt_time_int_enb_s { 2302 uint64_t reserved_32_63:32; 2303 uint64_t port:32; 2304 } s; 2305 struct cvmx_npei_pkt_time_int_enb_s cn52xx; 2306 struct cvmx_npei_pkt_time_int_enb_s cn56xx; 2307 }; 2308 2309 union cvmx_npei_rsl_int_blocks { 2310 uint64_t u64; 2311 struct cvmx_npei_rsl_int_blocks_s { 2312 uint64_t reserved_31_63:33; 2313 uint64_t iob:1; 2314 uint64_t lmc1:1; 2315 uint64_t agl:1; 2316 uint64_t reserved_24_27:4; 2317 uint64_t asxpcs1:1; 2318 uint64_t asxpcs0:1; 2319 uint64_t reserved_21_21:1; 2320 uint64_t pip:1; 2321 uint64_t spx1:1; 2322 uint64_t spx0:1; 2323 uint64_t lmc0:1; 2324 uint64_t l2c:1; 2325 uint64_t usb1:1; 2326 uint64_t rad:1; 2327 uint64_t usb:1; 2328 uint64_t pow:1; 2329 uint64_t tim:1; 2330 uint64_t pko:1; 2331 uint64_t ipd:1; 2332 uint64_t reserved_8_8:1; 2333 uint64_t zip:1; 2334 uint64_t dfa:1; 2335 uint64_t fpa:1; 2336 uint64_t key:1; 2337 uint64_t npei:1; 2338 uint64_t gmx1:1; 2339 uint64_t gmx0:1; 2340 uint64_t mio:1; 2341 } s; 2342 struct cvmx_npei_rsl_int_blocks_s cn52xx; 2343 struct cvmx_npei_rsl_int_blocks_s cn52xxp1; 2344 struct cvmx_npei_rsl_int_blocks_s cn56xx; 2345 struct cvmx_npei_rsl_int_blocks_s cn56xxp1; 2346 }; 2347 2348 union cvmx_npei_scratch_1 { 2349 uint64_t u64; 2350 struct cvmx_npei_scratch_1_s { 2351 uint64_t data:64; 2352 } s; 2353 struct cvmx_npei_scratch_1_s cn52xx; 2354 struct cvmx_npei_scratch_1_s cn52xxp1; 2355 struct cvmx_npei_scratch_1_s cn56xx; 2356 struct cvmx_npei_scratch_1_s cn56xxp1; 2357 }; 2358 2359 union cvmx_npei_state1 { 2360 uint64_t u64; 2361 struct cvmx_npei_state1_s { 2362 uint64_t cpl1:12; 2363 uint64_t cpl0:12; 2364 uint64_t arb:1; 2365 uint64_t csr:39; 2366 } s; 2367 struct cvmx_npei_state1_s cn52xx; 2368 struct cvmx_npei_state1_s cn52xxp1; 2369 struct cvmx_npei_state1_s cn56xx; 2370 struct cvmx_npei_state1_s cn56xxp1; 2371 }; 2372 2373 union cvmx_npei_state2 { 2374 uint64_t u64; 2375 struct cvmx_npei_state2_s { 2376 uint64_t reserved_48_63:16; 2377 uint64_t npei:1; 2378 uint64_t rac:1; 2379 uint64_t csm1:15; 2380 uint64_t csm0:15; 2381 uint64_t nnp0:8; 2382 uint64_t nnd:8; 2383 } s; 2384 struct cvmx_npei_state2_s cn52xx; 2385 struct cvmx_npei_state2_s cn52xxp1; 2386 struct cvmx_npei_state2_s cn56xx; 2387 struct cvmx_npei_state2_s cn56xxp1; 2388 }; 2389 2390 union cvmx_npei_state3 { 2391 uint64_t u64; 2392 struct cvmx_npei_state3_s { 2393 uint64_t reserved_56_63:8; 2394 uint64_t psm1:15; 2395 uint64_t psm0:15; 2396 uint64_t nsm1:13; 2397 uint64_t nsm0:13; 2398 } s; 2399 struct cvmx_npei_state3_s cn52xx; 2400 struct cvmx_npei_state3_s cn52xxp1; 2401 struct cvmx_npei_state3_s cn56xx; 2402 struct cvmx_npei_state3_s cn56xxp1; 2403 }; 2404 2405 union cvmx_npei_win_rd_addr { 2406 uint64_t u64; 2407 struct cvmx_npei_win_rd_addr_s { 2408 uint64_t reserved_51_63:13; 2409 uint64_t ld_cmd:2; 2410 uint64_t iobit:1; 2411 uint64_t rd_addr:48; 2412 } s; 2413 struct cvmx_npei_win_rd_addr_s cn52xx; 2414 struct cvmx_npei_win_rd_addr_s cn52xxp1; 2415 struct cvmx_npei_win_rd_addr_s cn56xx; 2416 struct cvmx_npei_win_rd_addr_s cn56xxp1; 2417 }; 2418 2419 union cvmx_npei_win_rd_data { 2420 uint64_t u64; 2421 struct cvmx_npei_win_rd_data_s { 2422 uint64_t rd_data:64; 2423 } s; 2424 struct cvmx_npei_win_rd_data_s cn52xx; 2425 struct cvmx_npei_win_rd_data_s cn52xxp1; 2426 struct cvmx_npei_win_rd_data_s cn56xx; 2427 struct cvmx_npei_win_rd_data_s cn56xxp1; 2428 }; 2429 2430 union cvmx_npei_win_wr_addr { 2431 uint64_t u64; 2432 struct cvmx_npei_win_wr_addr_s { 2433 uint64_t reserved_49_63:15; 2434 uint64_t iobit:1; 2435 uint64_t wr_addr:46; 2436 uint64_t reserved_0_1:2; 2437 } s; 2438 struct cvmx_npei_win_wr_addr_s cn52xx; 2439 struct cvmx_npei_win_wr_addr_s cn52xxp1; 2440 struct cvmx_npei_win_wr_addr_s cn56xx; 2441 struct cvmx_npei_win_wr_addr_s cn56xxp1; 2442 }; 2443 2444 union cvmx_npei_win_wr_data { 2445 uint64_t u64; 2446 struct cvmx_npei_win_wr_data_s { 2447 uint64_t wr_data:64; 2448 } s; 2449 struct cvmx_npei_win_wr_data_s cn52xx; 2450 struct cvmx_npei_win_wr_data_s cn52xxp1; 2451 struct cvmx_npei_win_wr_data_s cn56xx; 2452 struct cvmx_npei_win_wr_data_s cn56xxp1; 2453 }; 2454 2455 union cvmx_npei_win_wr_mask { 2456 uint64_t u64; 2457 struct cvmx_npei_win_wr_mask_s { 2458 uint64_t reserved_8_63:56; 2459 uint64_t wr_mask:8; 2460 } s; 2461 struct cvmx_npei_win_wr_mask_s cn52xx; 2462 struct cvmx_npei_win_wr_mask_s cn52xxp1; 2463 struct cvmx_npei_win_wr_mask_s cn56xx; 2464 struct cvmx_npei_win_wr_mask_s cn56xxp1; 2465 }; 2466 2467 union cvmx_npei_window_ctl { 2468 uint64_t u64; 2469 struct cvmx_npei_window_ctl_s { 2470 uint64_t reserved_32_63:32; 2471 uint64_t time:32; 2472 } s; 2473 struct cvmx_npei_window_ctl_s cn52xx; 2474 struct cvmx_npei_window_ctl_s cn52xxp1; 2475 struct cvmx_npei_window_ctl_s cn56xx; 2476 struct cvmx_npei_window_ctl_s cn56xxp1; 2477 }; 2478 2479 #endif 2480