1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Octeon CIU definitions 3 * 4 * Copyright (C) 2003-2018 Cavium, Inc. 5 */ 6 7 #ifndef __CVMX_CIU_DEFS_H__ 8 #define __CVMX_CIU_DEFS_H__ 9 10 #include <asm/bitfield.h> 11 12 #define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8) 13 #define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8) 14 #define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8) 15 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) 16 #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) 17 #define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16) 18 #define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16) 19 #define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16) 20 #define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16) 21 #define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16) 22 #define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16) 23 #define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8) 24 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) 25 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) 26 #define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 27 #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) 28 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) 29 #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) 30 #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) 31 #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) 32 #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) 33 #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) 34 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) 35 #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) 36 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) 37 #define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8) 38 #define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull)) 39 #define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8) 40 41 static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) 42 { 43 switch (cvmx_get_octeon_family()) { 44 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 45 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 46 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 47 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 48 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 49 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 50 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 51 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 52 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 53 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 54 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 55 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 56 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 57 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 58 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 59 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 60 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 61 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 62 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 63 return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8; 64 } 65 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 66 } 67 68 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) 69 { 70 switch (cvmx_get_octeon_family()) { 71 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 72 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 73 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 74 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 75 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 76 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 77 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 78 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 79 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 80 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 81 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 82 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 83 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 84 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 85 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 86 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 87 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 88 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 89 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 90 return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8; 91 } 92 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 93 } 94 95 static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) 96 { 97 switch (cvmx_get_octeon_family()) { 98 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 99 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 100 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 101 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 102 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 103 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 104 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 105 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 106 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 107 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 108 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 109 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 110 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 111 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 112 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 113 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 114 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 115 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 116 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 117 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 118 return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8; 119 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 120 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 121 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 122 return CVMX_ADD_IO_SEG(0x0001010000030000ull) + (offset) * 8; 123 } 124 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 125 } 126 127 static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) 128 { 129 switch (cvmx_get_octeon_family()) { 130 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 131 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 132 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 133 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 134 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 135 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 136 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 137 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 138 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 139 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 140 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 141 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 142 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 143 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 144 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 145 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 146 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 147 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 148 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 149 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 150 return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8; 151 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 152 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 153 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 154 return CVMX_ADD_IO_SEG(0x0001010000020000ull) + (offset) * 8; 155 } 156 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 157 } 158 159 160 union cvmx_ciu_qlm { 161 uint64_t u64; 162 struct cvmx_ciu_qlm_s { 163 __BITFIELD_FIELD(uint64_t g2bypass:1, 164 __BITFIELD_FIELD(uint64_t reserved_53_62:10, 165 __BITFIELD_FIELD(uint64_t g2deemph:5, 166 __BITFIELD_FIELD(uint64_t reserved_45_47:3, 167 __BITFIELD_FIELD(uint64_t g2margin:5, 168 __BITFIELD_FIELD(uint64_t reserved_32_39:8, 169 __BITFIELD_FIELD(uint64_t txbypass:1, 170 __BITFIELD_FIELD(uint64_t reserved_21_30:10, 171 __BITFIELD_FIELD(uint64_t txdeemph:5, 172 __BITFIELD_FIELD(uint64_t reserved_13_15:3, 173 __BITFIELD_FIELD(uint64_t txmargin:5, 174 __BITFIELD_FIELD(uint64_t reserved_4_7:4, 175 __BITFIELD_FIELD(uint64_t lane_en:4, 176 ;))))))))))))) 177 } s; 178 }; 179 180 union cvmx_ciu_qlm_jtgc { 181 uint64_t u64; 182 struct cvmx_ciu_qlm_jtgc_s { 183 __BITFIELD_FIELD(uint64_t reserved_17_63:47, 184 __BITFIELD_FIELD(uint64_t bypass_ext:1, 185 __BITFIELD_FIELD(uint64_t reserved_11_15:5, 186 __BITFIELD_FIELD(uint64_t clk_div:3, 187 __BITFIELD_FIELD(uint64_t reserved_7_7:1, 188 __BITFIELD_FIELD(uint64_t mux_sel:3, 189 __BITFIELD_FIELD(uint64_t bypass:4, 190 ;))))))) 191 } s; 192 }; 193 194 union cvmx_ciu_qlm_jtgd { 195 uint64_t u64; 196 struct cvmx_ciu_qlm_jtgd_s { 197 __BITFIELD_FIELD(uint64_t capture:1, 198 __BITFIELD_FIELD(uint64_t shift:1, 199 __BITFIELD_FIELD(uint64_t update:1, 200 __BITFIELD_FIELD(uint64_t reserved_45_60:16, 201 __BITFIELD_FIELD(uint64_t select:5, 202 __BITFIELD_FIELD(uint64_t reserved_37_39:3, 203 __BITFIELD_FIELD(uint64_t shft_cnt:5, 204 __BITFIELD_FIELD(uint64_t shft_reg:32, 205 ;)))))))) 206 } s; 207 }; 208 209 union cvmx_ciu_soft_prst { 210 uint64_t u64; 211 struct cvmx_ciu_soft_prst_s { 212 __BITFIELD_FIELD(uint64_t reserved_3_63:61, 213 __BITFIELD_FIELD(uint64_t host64:1, 214 __BITFIELD_FIELD(uint64_t npi:1, 215 __BITFIELD_FIELD(uint64_t soft_prst:1, 216 ;)))) 217 } s; 218 }; 219 220 union cvmx_ciu_timx { 221 uint64_t u64; 222 struct cvmx_ciu_timx_s { 223 __BITFIELD_FIELD(uint64_t reserved_37_63:27, 224 __BITFIELD_FIELD(uint64_t one_shot:1, 225 __BITFIELD_FIELD(uint64_t len:36, 226 ;))) 227 } s; 228 }; 229 230 union cvmx_ciu_wdogx { 231 uint64_t u64; 232 struct cvmx_ciu_wdogx_s { 233 __BITFIELD_FIELD(uint64_t reserved_46_63:18, 234 __BITFIELD_FIELD(uint64_t gstopen:1, 235 __BITFIELD_FIELD(uint64_t dstop:1, 236 __BITFIELD_FIELD(uint64_t cnt:24, 237 __BITFIELD_FIELD(uint64_t len:16, 238 __BITFIELD_FIELD(uint64_t state:2, 239 __BITFIELD_FIELD(uint64_t mode:2, 240 ;))))))) 241 } s; 242 }; 243 244 #endif /* __CVMX_CIU_DEFS_H__ */ 245