1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Octeon CIU definitions 3 * 4 * Copyright (C) 2003-2018 Cavium, Inc. 5 */ 6 7 #ifndef __CVMX_CIU_DEFS_H__ 8 #define __CVMX_CIU_DEFS_H__ 9 10 #include <asm/bitfield.h> 11 12 #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull)) 13 #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull)) 14 #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull)) 15 #define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8) 16 #define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8) 17 #define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8) 18 #define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8) 19 #define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8) 20 #define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8) 21 #define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8) 22 #define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8) 23 #define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8) 24 #define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8) 25 #define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8) 26 #define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8) 27 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) 28 #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull)) 29 #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull)) 30 #define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16) 31 #define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16) 32 #define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16) 33 #define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16) 34 #define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16) 35 #define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16) 36 #define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16) 37 #define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16) 38 #define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16) 39 #define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16) 40 #define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16) 41 #define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16) 42 #define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8) 43 #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8) 44 #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull)) 45 #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) 46 static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) 47 { 48 switch (cvmx_get_octeon_family()) { 49 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 50 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 51 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 52 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 53 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 54 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 55 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 56 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 57 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 58 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 59 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 60 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 61 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 62 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 63 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 64 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 65 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 66 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 67 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 68 return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8; 69 } 70 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 71 } 72 73 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) 74 { 75 switch (cvmx_get_octeon_family()) { 76 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 77 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 78 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 79 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 80 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 81 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 82 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 83 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 84 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 85 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 86 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 87 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 88 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 89 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 90 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 91 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 92 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 93 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 94 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 95 return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8; 96 } 97 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 98 } 99 100 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) 101 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) 102 #define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 103 #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) 104 static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) 105 { 106 switch (cvmx_get_octeon_family()) { 107 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 108 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 109 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 110 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 111 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 112 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 113 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 114 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 115 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 116 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 117 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 118 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 119 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 120 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 121 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 122 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 123 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 124 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 125 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 126 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 127 return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8; 128 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 129 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 130 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 131 return CVMX_ADD_IO_SEG(0x0001010000030000ull) + (offset) * 8; 132 } 133 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 134 } 135 136 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) 137 #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) 138 #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) 139 #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull)) 140 #define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull)) 141 #define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull)) 142 #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull)) 143 #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) 144 #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) 145 #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) 146 #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) 147 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) 148 #define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull)) 149 #define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 150 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) 151 #define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8) 152 #define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8) 153 #define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8) 154 #define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8) 155 #define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8) 156 #define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8) 157 #define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8) 158 #define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8) 159 #define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8) 160 #define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull)) 161 static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) 162 { 163 switch (cvmx_get_octeon_family()) { 164 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 165 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 166 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 167 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 168 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 169 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 170 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 171 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 172 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 173 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 174 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 175 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 176 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 177 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 178 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 179 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 180 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 181 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 182 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 183 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 184 return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8; 185 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 186 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 187 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 188 return CVMX_ADD_IO_SEG(0x0001010000020000ull) + (offset) * 8; 189 } 190 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 191 } 192 193 194 union cvmx_ciu_qlm { 195 uint64_t u64; 196 struct cvmx_ciu_qlm_s { 197 __BITFIELD_FIELD(uint64_t g2bypass:1, 198 __BITFIELD_FIELD(uint64_t reserved_53_62:10, 199 __BITFIELD_FIELD(uint64_t g2deemph:5, 200 __BITFIELD_FIELD(uint64_t reserved_45_47:3, 201 __BITFIELD_FIELD(uint64_t g2margin:5, 202 __BITFIELD_FIELD(uint64_t reserved_32_39:8, 203 __BITFIELD_FIELD(uint64_t txbypass:1, 204 __BITFIELD_FIELD(uint64_t reserved_21_30:10, 205 __BITFIELD_FIELD(uint64_t txdeemph:5, 206 __BITFIELD_FIELD(uint64_t reserved_13_15:3, 207 __BITFIELD_FIELD(uint64_t txmargin:5, 208 __BITFIELD_FIELD(uint64_t reserved_4_7:4, 209 __BITFIELD_FIELD(uint64_t lane_en:4, 210 ;))))))))))))) 211 } s; 212 }; 213 214 union cvmx_ciu_qlm_jtgc { 215 uint64_t u64; 216 struct cvmx_ciu_qlm_jtgc_s { 217 __BITFIELD_FIELD(uint64_t reserved_17_63:47, 218 __BITFIELD_FIELD(uint64_t bypass_ext:1, 219 __BITFIELD_FIELD(uint64_t reserved_11_15:5, 220 __BITFIELD_FIELD(uint64_t clk_div:3, 221 __BITFIELD_FIELD(uint64_t reserved_7_7:1, 222 __BITFIELD_FIELD(uint64_t mux_sel:3, 223 __BITFIELD_FIELD(uint64_t bypass:4, 224 ;))))))) 225 } s; 226 }; 227 228 union cvmx_ciu_qlm_jtgd { 229 uint64_t u64; 230 struct cvmx_ciu_qlm_jtgd_s { 231 __BITFIELD_FIELD(uint64_t capture:1, 232 __BITFIELD_FIELD(uint64_t shift:1, 233 __BITFIELD_FIELD(uint64_t update:1, 234 __BITFIELD_FIELD(uint64_t reserved_45_60:16, 235 __BITFIELD_FIELD(uint64_t select:5, 236 __BITFIELD_FIELD(uint64_t reserved_37_39:3, 237 __BITFIELD_FIELD(uint64_t shft_cnt:5, 238 __BITFIELD_FIELD(uint64_t shft_reg:32, 239 ;)))))))) 240 } s; 241 }; 242 243 union cvmx_ciu_soft_prst { 244 uint64_t u64; 245 struct cvmx_ciu_soft_prst_s { 246 __BITFIELD_FIELD(uint64_t reserved_3_63:61, 247 __BITFIELD_FIELD(uint64_t host64:1, 248 __BITFIELD_FIELD(uint64_t npi:1, 249 __BITFIELD_FIELD(uint64_t soft_prst:1, 250 ;)))) 251 } s; 252 }; 253 254 union cvmx_ciu_timx { 255 uint64_t u64; 256 struct cvmx_ciu_timx_s { 257 __BITFIELD_FIELD(uint64_t reserved_37_63:27, 258 __BITFIELD_FIELD(uint64_t one_shot:1, 259 __BITFIELD_FIELD(uint64_t len:36, 260 ;))) 261 } s; 262 }; 263 264 union cvmx_ciu_wdogx { 265 uint64_t u64; 266 struct cvmx_ciu_wdogx_s { 267 __BITFIELD_FIELD(uint64_t reserved_46_63:18, 268 __BITFIELD_FIELD(uint64_t gstopen:1, 269 __BITFIELD_FIELD(uint64_t dstop:1, 270 __BITFIELD_FIELD(uint64_t cnt:24, 271 __BITFIELD_FIELD(uint64_t len:16, 272 __BITFIELD_FIELD(uint64_t state:2, 273 __BITFIELD_FIELD(uint64_t mode:2, 274 ;))))))) 275 } s; 276 }; 277 278 #endif /* __CVMX_CIU_DEFS_H__ */ 279