1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_CIU_DEFS_H__ 29 #define __CVMX_CIU_DEFS_H__ 30 31 #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull)) 32 #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull)) 33 #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull)) 34 #define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8) 35 #define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8) 36 #define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8) 37 #define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8) 38 #define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8) 39 #define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8) 40 #define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8) 41 #define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8) 42 #define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8) 43 #define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8) 44 #define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8) 45 #define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8) 46 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) 47 #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull)) 48 #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull)) 49 #define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16) 50 #define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16) 51 #define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16) 52 #define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16) 53 #define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16) 54 #define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16) 55 #define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16) 56 #define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16) 57 #define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16) 58 #define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16) 59 #define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16) 60 #define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16) 61 #define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8) 62 #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8) 63 #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull)) 64 #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) 65 static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) 66 { 67 switch (cvmx_get_octeon_family()) { 68 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 69 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 70 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 71 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 72 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 73 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 74 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 75 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 76 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 77 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 78 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 79 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 80 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 81 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 82 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 83 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 84 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 85 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 86 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 87 return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8; 88 } 89 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 90 } 91 92 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) 93 { 94 switch (cvmx_get_octeon_family()) { 95 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 96 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 97 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 98 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 99 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 100 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 101 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 102 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 103 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 104 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 105 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 106 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 107 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 108 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 109 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 110 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 111 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 112 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 113 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 114 return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8; 115 } 116 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 117 } 118 119 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) 120 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) 121 #define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 122 #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) 123 static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) 124 { 125 switch (cvmx_get_octeon_family()) { 126 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 127 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 128 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 129 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 130 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 131 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 132 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 133 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 134 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 135 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 136 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 137 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 138 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 139 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 140 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 141 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 142 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 143 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 144 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 145 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 146 return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8; 147 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 148 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 149 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 150 return CVMX_ADD_IO_SEG(0x0001010000030000ull) + (offset) * 8; 151 } 152 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 153 } 154 155 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) 156 #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) 157 #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) 158 #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull)) 159 #define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull)) 160 #define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull)) 161 #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull)) 162 #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) 163 #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) 164 #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) 165 #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) 166 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) 167 #define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull)) 168 #define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 169 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) 170 #define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8) 171 #define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8) 172 #define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8) 173 #define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8) 174 #define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8) 175 #define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8) 176 #define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8) 177 #define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8) 178 #define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8) 179 #define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull)) 180 static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) 181 { 182 switch (cvmx_get_octeon_family()) { 183 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 184 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 185 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 186 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 187 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 188 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 189 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 190 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 191 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 192 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 193 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 194 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 195 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 196 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 197 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 198 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 199 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 200 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 201 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 202 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 203 return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8; 204 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 205 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 206 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 207 return CVMX_ADD_IO_SEG(0x0001010000020000ull) + (offset) * 8; 208 } 209 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 210 } 211 212 union cvmx_ciu_qlm0 { 213 uint64_t u64; 214 struct cvmx_ciu_qlm0_s { 215 #ifdef __BIG_ENDIAN_BITFIELD 216 uint64_t g2bypass:1; 217 uint64_t reserved_53_62:10; 218 uint64_t g2deemph:5; 219 uint64_t reserved_45_47:3; 220 uint64_t g2margin:5; 221 uint64_t reserved_32_39:8; 222 uint64_t txbypass:1; 223 uint64_t reserved_21_30:10; 224 uint64_t txdeemph:5; 225 uint64_t reserved_13_15:3; 226 uint64_t txmargin:5; 227 uint64_t reserved_4_7:4; 228 uint64_t lane_en:4; 229 #else 230 uint64_t lane_en:4; 231 uint64_t reserved_4_7:4; 232 uint64_t txmargin:5; 233 uint64_t reserved_13_15:3; 234 uint64_t txdeemph:5; 235 uint64_t reserved_21_30:10; 236 uint64_t txbypass:1; 237 uint64_t reserved_32_39:8; 238 uint64_t g2margin:5; 239 uint64_t reserved_45_47:3; 240 uint64_t g2deemph:5; 241 uint64_t reserved_53_62:10; 242 uint64_t g2bypass:1; 243 #endif 244 } s; 245 }; 246 247 union cvmx_ciu_qlm1 { 248 uint64_t u64; 249 struct cvmx_ciu_qlm1_s { 250 #ifdef __BIG_ENDIAN_BITFIELD 251 uint64_t g2bypass:1; 252 uint64_t reserved_53_62:10; 253 uint64_t g2deemph:5; 254 uint64_t reserved_45_47:3; 255 uint64_t g2margin:5; 256 uint64_t reserved_32_39:8; 257 uint64_t txbypass:1; 258 uint64_t reserved_21_30:10; 259 uint64_t txdeemph:5; 260 uint64_t reserved_13_15:3; 261 uint64_t txmargin:5; 262 uint64_t reserved_4_7:4; 263 uint64_t lane_en:4; 264 #else 265 uint64_t lane_en:4; 266 uint64_t reserved_4_7:4; 267 uint64_t txmargin:5; 268 uint64_t reserved_13_15:3; 269 uint64_t txdeemph:5; 270 uint64_t reserved_21_30:10; 271 uint64_t txbypass:1; 272 uint64_t reserved_32_39:8; 273 uint64_t g2margin:5; 274 uint64_t reserved_45_47:3; 275 uint64_t g2deemph:5; 276 uint64_t reserved_53_62:10; 277 uint64_t g2bypass:1; 278 #endif 279 } s; 280 }; 281 282 union cvmx_ciu_qlm_jtgc { 283 uint64_t u64; 284 struct cvmx_ciu_qlm_jtgc_s { 285 #ifdef __BIG_ENDIAN_BITFIELD 286 uint64_t reserved_17_63:47; 287 uint64_t bypass_ext:1; 288 uint64_t reserved_11_15:5; 289 uint64_t clk_div:3; 290 uint64_t reserved_7_7:1; 291 uint64_t mux_sel:3; 292 uint64_t bypass:4; 293 #else 294 uint64_t bypass:4; 295 uint64_t mux_sel:3; 296 uint64_t reserved_7_7:1; 297 uint64_t clk_div:3; 298 uint64_t reserved_11_15:5; 299 uint64_t bypass_ext:1; 300 uint64_t reserved_17_63:47; 301 #endif 302 } s; 303 }; 304 305 union cvmx_ciu_qlm_jtgd { 306 uint64_t u64; 307 struct cvmx_ciu_qlm_jtgd_s { 308 #ifdef __BIG_ENDIAN_BITFIELD 309 uint64_t capture:1; 310 uint64_t shift:1; 311 uint64_t update:1; 312 uint64_t reserved_45_60:16; 313 uint64_t select:5; 314 uint64_t reserved_37_39:3; 315 uint64_t shft_cnt:5; 316 uint64_t shft_reg:32; 317 #else 318 uint64_t shft_reg:32; 319 uint64_t shft_cnt:5; 320 uint64_t reserved_37_39:3; 321 uint64_t select:5; 322 uint64_t reserved_45_60:16; 323 uint64_t update:1; 324 uint64_t shift:1; 325 uint64_t capture:1; 326 #endif 327 } s; 328 }; 329 330 union cvmx_ciu_soft_prst { 331 uint64_t u64; 332 struct cvmx_ciu_soft_prst_s { 333 #ifdef __BIG_ENDIAN_BITFIELD 334 uint64_t reserved_3_63:61; 335 uint64_t host64:1; 336 uint64_t npi:1; 337 uint64_t soft_prst:1; 338 #else 339 uint64_t soft_prst:1; 340 uint64_t npi:1; 341 uint64_t host64:1; 342 uint64_t reserved_3_63:61; 343 #endif 344 } s; 345 }; 346 347 union cvmx_ciu_timx { 348 uint64_t u64; 349 struct cvmx_ciu_timx_s { 350 #ifdef __BIG_ENDIAN_BITFIELD 351 uint64_t reserved_37_63:27; 352 uint64_t one_shot:1; 353 uint64_t len:36; 354 #else 355 uint64_t len:36; 356 uint64_t one_shot:1; 357 uint64_t reserved_37_63:27; 358 #endif 359 } s; 360 }; 361 362 union cvmx_ciu_wdogx { 363 uint64_t u64; 364 struct cvmx_ciu_wdogx_s { 365 #ifdef __BIG_ENDIAN_BITFIELD 366 uint64_t reserved_46_63:18; 367 uint64_t gstopen:1; 368 uint64_t dstop:1; 369 uint64_t cnt:24; 370 uint64_t len:16; 371 uint64_t state:2; 372 uint64_t mode:2; 373 #else 374 uint64_t mode:2; 375 uint64_t state:2; 376 uint64_t len:16; 377 uint64_t cnt:24; 378 uint64_t dstop:1; 379 uint64_t gstopen:1; 380 uint64_t reserved_46_63:18; 381 #endif 382 } s; 383 }; 384 385 #endif 386