1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_CIU_DEFS_H__ 29 #define __CVMX_CIU_DEFS_H__ 30 31 #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull)) 32 #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull)) 33 #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull)) 34 #define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8) 35 #define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8) 36 #define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8) 37 #define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8) 38 #define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8) 39 #define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8) 40 #define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8) 41 #define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8) 42 #define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8) 43 #define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8) 44 #define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8) 45 #define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8) 46 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) 47 #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull)) 48 #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull)) 49 #define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16) 50 #define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16) 51 #define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16) 52 #define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16) 53 #define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16) 54 #define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16) 55 #define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16) 56 #define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16) 57 #define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16) 58 #define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16) 59 #define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16) 60 #define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16) 61 #define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8) 62 #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8) 63 #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull)) 64 #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) 65 static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) 66 { 67 switch (cvmx_get_octeon_family()) { 68 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 69 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 70 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 71 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 72 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 73 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 74 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 75 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 76 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 77 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 78 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 79 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 80 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 81 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 82 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 83 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 84 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 85 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 86 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 87 return CVMX_ADD_IO_SEG(0x0001070100100600ull) + (offset) * 8; 88 } 89 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + (offset) * 8; 90 } 91 92 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) 93 { 94 switch (cvmx_get_octeon_family()) { 95 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 96 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 97 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 98 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 99 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 100 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 101 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 102 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 103 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 104 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 105 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 106 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 107 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 108 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 109 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 110 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 111 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 112 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 113 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 114 return CVMX_ADD_IO_SEG(0x0001070100100400ull) + (offset) * 8; 115 } 116 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + (offset) * 8; 117 } 118 119 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) 120 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) 121 #define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 122 #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) 123 static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) 124 { 125 switch (cvmx_get_octeon_family()) { 126 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 127 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 128 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 129 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 130 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 131 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 132 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 133 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 134 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 135 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 136 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 137 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 138 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 139 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 140 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 141 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 142 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 143 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 144 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 145 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 146 return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8; 147 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 148 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 149 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 150 return CVMX_ADD_IO_SEG(0x0001010000030000ull) + (offset) * 8; 151 } 152 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8; 153 } 154 155 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) 156 #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) 157 #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) 158 #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull)) 159 #define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull)) 160 #define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull)) 161 #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull)) 162 #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) 163 #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) 164 #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) 165 #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) 166 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) 167 #define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull)) 168 #define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull)) 169 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) 170 #define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8) 171 #define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8) 172 #define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8) 173 #define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8) 174 #define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8) 175 #define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8) 176 #define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8) 177 #define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8) 178 #define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8) 179 #define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull)) 180 static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) 181 { 182 switch (cvmx_get_octeon_family()) { 183 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 184 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 185 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 186 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 187 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 188 case OCTEON_CN70XX & OCTEON_FAMILY_MASK: 189 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 190 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 191 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 192 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 193 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 194 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 195 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 196 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 197 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 198 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 199 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 200 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 201 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 202 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 203 return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8; 204 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK: 205 case OCTEON_CN73XX & OCTEON_FAMILY_MASK: 206 case OCTEON_CN78XX & OCTEON_FAMILY_MASK: 207 return CVMX_ADD_IO_SEG(0x0001010000020000ull) + (offset) * 8; 208 } 209 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8; 210 } 211 212 union cvmx_ciu_bist { 213 uint64_t u64; 214 struct cvmx_ciu_bist_s { 215 #ifdef __BIG_ENDIAN_BITFIELD 216 uint64_t reserved_7_63:57; 217 uint64_t bist:7; 218 #else 219 uint64_t bist:7; 220 uint64_t reserved_7_63:57; 221 #endif 222 } s; 223 struct cvmx_ciu_bist_cn30xx { 224 #ifdef __BIG_ENDIAN_BITFIELD 225 uint64_t reserved_4_63:60; 226 uint64_t bist:4; 227 #else 228 uint64_t bist:4; 229 uint64_t reserved_4_63:60; 230 #endif 231 } cn30xx; 232 struct cvmx_ciu_bist_cn30xx cn31xx; 233 struct cvmx_ciu_bist_cn30xx cn38xx; 234 struct cvmx_ciu_bist_cn30xx cn38xxp2; 235 struct cvmx_ciu_bist_cn50xx { 236 #ifdef __BIG_ENDIAN_BITFIELD 237 uint64_t reserved_2_63:62; 238 uint64_t bist:2; 239 #else 240 uint64_t bist:2; 241 uint64_t reserved_2_63:62; 242 #endif 243 } cn50xx; 244 struct cvmx_ciu_bist_cn52xx { 245 #ifdef __BIG_ENDIAN_BITFIELD 246 uint64_t reserved_3_63:61; 247 uint64_t bist:3; 248 #else 249 uint64_t bist:3; 250 uint64_t reserved_3_63:61; 251 #endif 252 } cn52xx; 253 struct cvmx_ciu_bist_cn52xx cn52xxp1; 254 struct cvmx_ciu_bist_cn30xx cn56xx; 255 struct cvmx_ciu_bist_cn30xx cn56xxp1; 256 struct cvmx_ciu_bist_cn30xx cn58xx; 257 struct cvmx_ciu_bist_cn30xx cn58xxp1; 258 struct cvmx_ciu_bist_cn61xx { 259 #ifdef __BIG_ENDIAN_BITFIELD 260 uint64_t reserved_6_63:58; 261 uint64_t bist:6; 262 #else 263 uint64_t bist:6; 264 uint64_t reserved_6_63:58; 265 #endif 266 } cn61xx; 267 struct cvmx_ciu_bist_cn63xx { 268 #ifdef __BIG_ENDIAN_BITFIELD 269 uint64_t reserved_5_63:59; 270 uint64_t bist:5; 271 #else 272 uint64_t bist:5; 273 uint64_t reserved_5_63:59; 274 #endif 275 } cn63xx; 276 struct cvmx_ciu_bist_cn63xx cn63xxp1; 277 struct cvmx_ciu_bist_cn61xx cn66xx; 278 struct cvmx_ciu_bist_s cn68xx; 279 struct cvmx_ciu_bist_s cn68xxp1; 280 struct cvmx_ciu_bist_cn61xx cnf71xx; 281 }; 282 283 union cvmx_ciu_block_int { 284 uint64_t u64; 285 struct cvmx_ciu_block_int_s { 286 #ifdef __BIG_ENDIAN_BITFIELD 287 uint64_t reserved_62_63:2; 288 uint64_t srio3:1; 289 uint64_t srio2:1; 290 uint64_t reserved_43_59:17; 291 uint64_t ptp:1; 292 uint64_t dpi:1; 293 uint64_t dfm:1; 294 uint64_t reserved_34_39:6; 295 uint64_t srio1:1; 296 uint64_t srio0:1; 297 uint64_t reserved_31_31:1; 298 uint64_t iob:1; 299 uint64_t reserved_29_29:1; 300 uint64_t agl:1; 301 uint64_t reserved_27_27:1; 302 uint64_t pem1:1; 303 uint64_t pem0:1; 304 uint64_t reserved_24_24:1; 305 uint64_t asxpcs1:1; 306 uint64_t asxpcs0:1; 307 uint64_t reserved_21_21:1; 308 uint64_t pip:1; 309 uint64_t reserved_18_19:2; 310 uint64_t lmc0:1; 311 uint64_t l2c:1; 312 uint64_t reserved_15_15:1; 313 uint64_t rad:1; 314 uint64_t usb:1; 315 uint64_t pow:1; 316 uint64_t tim:1; 317 uint64_t pko:1; 318 uint64_t ipd:1; 319 uint64_t reserved_8_8:1; 320 uint64_t zip:1; 321 uint64_t dfa:1; 322 uint64_t fpa:1; 323 uint64_t key:1; 324 uint64_t sli:1; 325 uint64_t gmx1:1; 326 uint64_t gmx0:1; 327 uint64_t mio:1; 328 #else 329 uint64_t mio:1; 330 uint64_t gmx0:1; 331 uint64_t gmx1:1; 332 uint64_t sli:1; 333 uint64_t key:1; 334 uint64_t fpa:1; 335 uint64_t dfa:1; 336 uint64_t zip:1; 337 uint64_t reserved_8_8:1; 338 uint64_t ipd:1; 339 uint64_t pko:1; 340 uint64_t tim:1; 341 uint64_t pow:1; 342 uint64_t usb:1; 343 uint64_t rad:1; 344 uint64_t reserved_15_15:1; 345 uint64_t l2c:1; 346 uint64_t lmc0:1; 347 uint64_t reserved_18_19:2; 348 uint64_t pip:1; 349 uint64_t reserved_21_21:1; 350 uint64_t asxpcs0:1; 351 uint64_t asxpcs1:1; 352 uint64_t reserved_24_24:1; 353 uint64_t pem0:1; 354 uint64_t pem1:1; 355 uint64_t reserved_27_27:1; 356 uint64_t agl:1; 357 uint64_t reserved_29_29:1; 358 uint64_t iob:1; 359 uint64_t reserved_31_31:1; 360 uint64_t srio0:1; 361 uint64_t srio1:1; 362 uint64_t reserved_34_39:6; 363 uint64_t dfm:1; 364 uint64_t dpi:1; 365 uint64_t ptp:1; 366 uint64_t reserved_43_59:17; 367 uint64_t srio2:1; 368 uint64_t srio3:1; 369 uint64_t reserved_62_63:2; 370 #endif 371 } s; 372 struct cvmx_ciu_block_int_cn61xx { 373 #ifdef __BIG_ENDIAN_BITFIELD 374 uint64_t reserved_43_63:21; 375 uint64_t ptp:1; 376 uint64_t dpi:1; 377 uint64_t reserved_31_40:10; 378 uint64_t iob:1; 379 uint64_t reserved_29_29:1; 380 uint64_t agl:1; 381 uint64_t reserved_27_27:1; 382 uint64_t pem1:1; 383 uint64_t pem0:1; 384 uint64_t reserved_24_24:1; 385 uint64_t asxpcs1:1; 386 uint64_t asxpcs0:1; 387 uint64_t reserved_21_21:1; 388 uint64_t pip:1; 389 uint64_t reserved_18_19:2; 390 uint64_t lmc0:1; 391 uint64_t l2c:1; 392 uint64_t reserved_15_15:1; 393 uint64_t rad:1; 394 uint64_t usb:1; 395 uint64_t pow:1; 396 uint64_t tim:1; 397 uint64_t pko:1; 398 uint64_t ipd:1; 399 uint64_t reserved_8_8:1; 400 uint64_t zip:1; 401 uint64_t dfa:1; 402 uint64_t fpa:1; 403 uint64_t key:1; 404 uint64_t sli:1; 405 uint64_t gmx1:1; 406 uint64_t gmx0:1; 407 uint64_t mio:1; 408 #else 409 uint64_t mio:1; 410 uint64_t gmx0:1; 411 uint64_t gmx1:1; 412 uint64_t sli:1; 413 uint64_t key:1; 414 uint64_t fpa:1; 415 uint64_t dfa:1; 416 uint64_t zip:1; 417 uint64_t reserved_8_8:1; 418 uint64_t ipd:1; 419 uint64_t pko:1; 420 uint64_t tim:1; 421 uint64_t pow:1; 422 uint64_t usb:1; 423 uint64_t rad:1; 424 uint64_t reserved_15_15:1; 425 uint64_t l2c:1; 426 uint64_t lmc0:1; 427 uint64_t reserved_18_19:2; 428 uint64_t pip:1; 429 uint64_t reserved_21_21:1; 430 uint64_t asxpcs0:1; 431 uint64_t asxpcs1:1; 432 uint64_t reserved_24_24:1; 433 uint64_t pem0:1; 434 uint64_t pem1:1; 435 uint64_t reserved_27_27:1; 436 uint64_t agl:1; 437 uint64_t reserved_29_29:1; 438 uint64_t iob:1; 439 uint64_t reserved_31_40:10; 440 uint64_t dpi:1; 441 uint64_t ptp:1; 442 uint64_t reserved_43_63:21; 443 #endif 444 } cn61xx; 445 struct cvmx_ciu_block_int_cn63xx { 446 #ifdef __BIG_ENDIAN_BITFIELD 447 uint64_t reserved_43_63:21; 448 uint64_t ptp:1; 449 uint64_t dpi:1; 450 uint64_t dfm:1; 451 uint64_t reserved_34_39:6; 452 uint64_t srio1:1; 453 uint64_t srio0:1; 454 uint64_t reserved_31_31:1; 455 uint64_t iob:1; 456 uint64_t reserved_29_29:1; 457 uint64_t agl:1; 458 uint64_t reserved_27_27:1; 459 uint64_t pem1:1; 460 uint64_t pem0:1; 461 uint64_t reserved_23_24:2; 462 uint64_t asxpcs0:1; 463 uint64_t reserved_21_21:1; 464 uint64_t pip:1; 465 uint64_t reserved_18_19:2; 466 uint64_t lmc0:1; 467 uint64_t l2c:1; 468 uint64_t reserved_15_15:1; 469 uint64_t rad:1; 470 uint64_t usb:1; 471 uint64_t pow:1; 472 uint64_t tim:1; 473 uint64_t pko:1; 474 uint64_t ipd:1; 475 uint64_t reserved_8_8:1; 476 uint64_t zip:1; 477 uint64_t dfa:1; 478 uint64_t fpa:1; 479 uint64_t key:1; 480 uint64_t sli:1; 481 uint64_t reserved_2_2:1; 482 uint64_t gmx0:1; 483 uint64_t mio:1; 484 #else 485 uint64_t mio:1; 486 uint64_t gmx0:1; 487 uint64_t reserved_2_2:1; 488 uint64_t sli:1; 489 uint64_t key:1; 490 uint64_t fpa:1; 491 uint64_t dfa:1; 492 uint64_t zip:1; 493 uint64_t reserved_8_8:1; 494 uint64_t ipd:1; 495 uint64_t pko:1; 496 uint64_t tim:1; 497 uint64_t pow:1; 498 uint64_t usb:1; 499 uint64_t rad:1; 500 uint64_t reserved_15_15:1; 501 uint64_t l2c:1; 502 uint64_t lmc0:1; 503 uint64_t reserved_18_19:2; 504 uint64_t pip:1; 505 uint64_t reserved_21_21:1; 506 uint64_t asxpcs0:1; 507 uint64_t reserved_23_24:2; 508 uint64_t pem0:1; 509 uint64_t pem1:1; 510 uint64_t reserved_27_27:1; 511 uint64_t agl:1; 512 uint64_t reserved_29_29:1; 513 uint64_t iob:1; 514 uint64_t reserved_31_31:1; 515 uint64_t srio0:1; 516 uint64_t srio1:1; 517 uint64_t reserved_34_39:6; 518 uint64_t dfm:1; 519 uint64_t dpi:1; 520 uint64_t ptp:1; 521 uint64_t reserved_43_63:21; 522 #endif 523 } cn63xx; 524 struct cvmx_ciu_block_int_cn63xx cn63xxp1; 525 struct cvmx_ciu_block_int_cn66xx { 526 #ifdef __BIG_ENDIAN_BITFIELD 527 uint64_t reserved_62_63:2; 528 uint64_t srio3:1; 529 uint64_t srio2:1; 530 uint64_t reserved_43_59:17; 531 uint64_t ptp:1; 532 uint64_t dpi:1; 533 uint64_t dfm:1; 534 uint64_t reserved_33_39:7; 535 uint64_t srio0:1; 536 uint64_t reserved_31_31:1; 537 uint64_t iob:1; 538 uint64_t reserved_29_29:1; 539 uint64_t agl:1; 540 uint64_t reserved_27_27:1; 541 uint64_t pem1:1; 542 uint64_t pem0:1; 543 uint64_t reserved_24_24:1; 544 uint64_t asxpcs1:1; 545 uint64_t asxpcs0:1; 546 uint64_t reserved_21_21:1; 547 uint64_t pip:1; 548 uint64_t reserved_18_19:2; 549 uint64_t lmc0:1; 550 uint64_t l2c:1; 551 uint64_t reserved_15_15:1; 552 uint64_t rad:1; 553 uint64_t usb:1; 554 uint64_t pow:1; 555 uint64_t tim:1; 556 uint64_t pko:1; 557 uint64_t ipd:1; 558 uint64_t reserved_8_8:1; 559 uint64_t zip:1; 560 uint64_t dfa:1; 561 uint64_t fpa:1; 562 uint64_t key:1; 563 uint64_t sli:1; 564 uint64_t gmx1:1; 565 uint64_t gmx0:1; 566 uint64_t mio:1; 567 #else 568 uint64_t mio:1; 569 uint64_t gmx0:1; 570 uint64_t gmx1:1; 571 uint64_t sli:1; 572 uint64_t key:1; 573 uint64_t fpa:1; 574 uint64_t dfa:1; 575 uint64_t zip:1; 576 uint64_t reserved_8_8:1; 577 uint64_t ipd:1; 578 uint64_t pko:1; 579 uint64_t tim:1; 580 uint64_t pow:1; 581 uint64_t usb:1; 582 uint64_t rad:1; 583 uint64_t reserved_15_15:1; 584 uint64_t l2c:1; 585 uint64_t lmc0:1; 586 uint64_t reserved_18_19:2; 587 uint64_t pip:1; 588 uint64_t reserved_21_21:1; 589 uint64_t asxpcs0:1; 590 uint64_t asxpcs1:1; 591 uint64_t reserved_24_24:1; 592 uint64_t pem0:1; 593 uint64_t pem1:1; 594 uint64_t reserved_27_27:1; 595 uint64_t agl:1; 596 uint64_t reserved_29_29:1; 597 uint64_t iob:1; 598 uint64_t reserved_31_31:1; 599 uint64_t srio0:1; 600 uint64_t reserved_33_39:7; 601 uint64_t dfm:1; 602 uint64_t dpi:1; 603 uint64_t ptp:1; 604 uint64_t reserved_43_59:17; 605 uint64_t srio2:1; 606 uint64_t srio3:1; 607 uint64_t reserved_62_63:2; 608 #endif 609 } cn66xx; 610 struct cvmx_ciu_block_int_cnf71xx { 611 #ifdef __BIG_ENDIAN_BITFIELD 612 uint64_t reserved_43_63:21; 613 uint64_t ptp:1; 614 uint64_t dpi:1; 615 uint64_t reserved_31_40:10; 616 uint64_t iob:1; 617 uint64_t reserved_27_29:3; 618 uint64_t pem1:1; 619 uint64_t pem0:1; 620 uint64_t reserved_23_24:2; 621 uint64_t asxpcs0:1; 622 uint64_t reserved_21_21:1; 623 uint64_t pip:1; 624 uint64_t reserved_18_19:2; 625 uint64_t lmc0:1; 626 uint64_t l2c:1; 627 uint64_t reserved_15_15:1; 628 uint64_t rad:1; 629 uint64_t usb:1; 630 uint64_t pow:1; 631 uint64_t tim:1; 632 uint64_t pko:1; 633 uint64_t ipd:1; 634 uint64_t reserved_6_8:3; 635 uint64_t fpa:1; 636 uint64_t key:1; 637 uint64_t sli:1; 638 uint64_t reserved_2_2:1; 639 uint64_t gmx0:1; 640 uint64_t mio:1; 641 #else 642 uint64_t mio:1; 643 uint64_t gmx0:1; 644 uint64_t reserved_2_2:1; 645 uint64_t sli:1; 646 uint64_t key:1; 647 uint64_t fpa:1; 648 uint64_t reserved_6_8:3; 649 uint64_t ipd:1; 650 uint64_t pko:1; 651 uint64_t tim:1; 652 uint64_t pow:1; 653 uint64_t usb:1; 654 uint64_t rad:1; 655 uint64_t reserved_15_15:1; 656 uint64_t l2c:1; 657 uint64_t lmc0:1; 658 uint64_t reserved_18_19:2; 659 uint64_t pip:1; 660 uint64_t reserved_21_21:1; 661 uint64_t asxpcs0:1; 662 uint64_t reserved_23_24:2; 663 uint64_t pem0:1; 664 uint64_t pem1:1; 665 uint64_t reserved_27_29:3; 666 uint64_t iob:1; 667 uint64_t reserved_31_40:10; 668 uint64_t dpi:1; 669 uint64_t ptp:1; 670 uint64_t reserved_43_63:21; 671 #endif 672 } cnf71xx; 673 }; 674 675 union cvmx_ciu_dint { 676 uint64_t u64; 677 struct cvmx_ciu_dint_s { 678 #ifdef __BIG_ENDIAN_BITFIELD 679 uint64_t reserved_32_63:32; 680 uint64_t dint:32; 681 #else 682 uint64_t dint:32; 683 uint64_t reserved_32_63:32; 684 #endif 685 } s; 686 struct cvmx_ciu_dint_cn30xx { 687 #ifdef __BIG_ENDIAN_BITFIELD 688 uint64_t reserved_1_63:63; 689 uint64_t dint:1; 690 #else 691 uint64_t dint:1; 692 uint64_t reserved_1_63:63; 693 #endif 694 } cn30xx; 695 struct cvmx_ciu_dint_cn31xx { 696 #ifdef __BIG_ENDIAN_BITFIELD 697 uint64_t reserved_2_63:62; 698 uint64_t dint:2; 699 #else 700 uint64_t dint:2; 701 uint64_t reserved_2_63:62; 702 #endif 703 } cn31xx; 704 struct cvmx_ciu_dint_cn38xx { 705 #ifdef __BIG_ENDIAN_BITFIELD 706 uint64_t reserved_16_63:48; 707 uint64_t dint:16; 708 #else 709 uint64_t dint:16; 710 uint64_t reserved_16_63:48; 711 #endif 712 } cn38xx; 713 struct cvmx_ciu_dint_cn38xx cn38xxp2; 714 struct cvmx_ciu_dint_cn31xx cn50xx; 715 struct cvmx_ciu_dint_cn52xx { 716 #ifdef __BIG_ENDIAN_BITFIELD 717 uint64_t reserved_4_63:60; 718 uint64_t dint:4; 719 #else 720 uint64_t dint:4; 721 uint64_t reserved_4_63:60; 722 #endif 723 } cn52xx; 724 struct cvmx_ciu_dint_cn52xx cn52xxp1; 725 struct cvmx_ciu_dint_cn56xx { 726 #ifdef __BIG_ENDIAN_BITFIELD 727 uint64_t reserved_12_63:52; 728 uint64_t dint:12; 729 #else 730 uint64_t dint:12; 731 uint64_t reserved_12_63:52; 732 #endif 733 } cn56xx; 734 struct cvmx_ciu_dint_cn56xx cn56xxp1; 735 struct cvmx_ciu_dint_cn38xx cn58xx; 736 struct cvmx_ciu_dint_cn38xx cn58xxp1; 737 struct cvmx_ciu_dint_cn52xx cn61xx; 738 struct cvmx_ciu_dint_cn63xx { 739 #ifdef __BIG_ENDIAN_BITFIELD 740 uint64_t reserved_6_63:58; 741 uint64_t dint:6; 742 #else 743 uint64_t dint:6; 744 uint64_t reserved_6_63:58; 745 #endif 746 } cn63xx; 747 struct cvmx_ciu_dint_cn63xx cn63xxp1; 748 struct cvmx_ciu_dint_cn66xx { 749 #ifdef __BIG_ENDIAN_BITFIELD 750 uint64_t reserved_10_63:54; 751 uint64_t dint:10; 752 #else 753 uint64_t dint:10; 754 uint64_t reserved_10_63:54; 755 #endif 756 } cn66xx; 757 struct cvmx_ciu_dint_s cn68xx; 758 struct cvmx_ciu_dint_s cn68xxp1; 759 struct cvmx_ciu_dint_cn52xx cnf71xx; 760 }; 761 762 union cvmx_ciu_en2_iox_int { 763 uint64_t u64; 764 struct cvmx_ciu_en2_iox_int_s { 765 #ifdef __BIG_ENDIAN_BITFIELD 766 uint64_t reserved_15_63:49; 767 uint64_t endor:2; 768 uint64_t eoi:1; 769 uint64_t reserved_10_11:2; 770 uint64_t timer:6; 771 uint64_t reserved_0_3:4; 772 #else 773 uint64_t reserved_0_3:4; 774 uint64_t timer:6; 775 uint64_t reserved_10_11:2; 776 uint64_t eoi:1; 777 uint64_t endor:2; 778 uint64_t reserved_15_63:49; 779 #endif 780 } s; 781 struct cvmx_ciu_en2_iox_int_cn61xx { 782 #ifdef __BIG_ENDIAN_BITFIELD 783 uint64_t reserved_10_63:54; 784 uint64_t timer:6; 785 uint64_t reserved_0_3:4; 786 #else 787 uint64_t reserved_0_3:4; 788 uint64_t timer:6; 789 uint64_t reserved_10_63:54; 790 #endif 791 } cn61xx; 792 struct cvmx_ciu_en2_iox_int_cn61xx cn66xx; 793 struct cvmx_ciu_en2_iox_int_s cnf71xx; 794 }; 795 796 union cvmx_ciu_en2_iox_int_w1c { 797 uint64_t u64; 798 struct cvmx_ciu_en2_iox_int_w1c_s { 799 #ifdef __BIG_ENDIAN_BITFIELD 800 uint64_t reserved_15_63:49; 801 uint64_t endor:2; 802 uint64_t eoi:1; 803 uint64_t reserved_10_11:2; 804 uint64_t timer:6; 805 uint64_t reserved_0_3:4; 806 #else 807 uint64_t reserved_0_3:4; 808 uint64_t timer:6; 809 uint64_t reserved_10_11:2; 810 uint64_t eoi:1; 811 uint64_t endor:2; 812 uint64_t reserved_15_63:49; 813 #endif 814 } s; 815 struct cvmx_ciu_en2_iox_int_w1c_cn61xx { 816 #ifdef __BIG_ENDIAN_BITFIELD 817 uint64_t reserved_10_63:54; 818 uint64_t timer:6; 819 uint64_t reserved_0_3:4; 820 #else 821 uint64_t reserved_0_3:4; 822 uint64_t timer:6; 823 uint64_t reserved_10_63:54; 824 #endif 825 } cn61xx; 826 struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx; 827 struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx; 828 }; 829 830 union cvmx_ciu_en2_iox_int_w1s { 831 uint64_t u64; 832 struct cvmx_ciu_en2_iox_int_w1s_s { 833 #ifdef __BIG_ENDIAN_BITFIELD 834 uint64_t reserved_15_63:49; 835 uint64_t endor:2; 836 uint64_t eoi:1; 837 uint64_t reserved_10_11:2; 838 uint64_t timer:6; 839 uint64_t reserved_0_3:4; 840 #else 841 uint64_t reserved_0_3:4; 842 uint64_t timer:6; 843 uint64_t reserved_10_11:2; 844 uint64_t eoi:1; 845 uint64_t endor:2; 846 uint64_t reserved_15_63:49; 847 #endif 848 } s; 849 struct cvmx_ciu_en2_iox_int_w1s_cn61xx { 850 #ifdef __BIG_ENDIAN_BITFIELD 851 uint64_t reserved_10_63:54; 852 uint64_t timer:6; 853 uint64_t reserved_0_3:4; 854 #else 855 uint64_t reserved_0_3:4; 856 uint64_t timer:6; 857 uint64_t reserved_10_63:54; 858 #endif 859 } cn61xx; 860 struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx; 861 struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx; 862 }; 863 864 union cvmx_ciu_en2_ppx_ip2 { 865 uint64_t u64; 866 struct cvmx_ciu_en2_ppx_ip2_s { 867 #ifdef __BIG_ENDIAN_BITFIELD 868 uint64_t reserved_15_63:49; 869 uint64_t endor:2; 870 uint64_t eoi:1; 871 uint64_t reserved_10_11:2; 872 uint64_t timer:6; 873 uint64_t reserved_0_3:4; 874 #else 875 uint64_t reserved_0_3:4; 876 uint64_t timer:6; 877 uint64_t reserved_10_11:2; 878 uint64_t eoi:1; 879 uint64_t endor:2; 880 uint64_t reserved_15_63:49; 881 #endif 882 } s; 883 struct cvmx_ciu_en2_ppx_ip2_cn61xx { 884 #ifdef __BIG_ENDIAN_BITFIELD 885 uint64_t reserved_10_63:54; 886 uint64_t timer:6; 887 uint64_t reserved_0_3:4; 888 #else 889 uint64_t reserved_0_3:4; 890 uint64_t timer:6; 891 uint64_t reserved_10_63:54; 892 #endif 893 } cn61xx; 894 struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx; 895 struct cvmx_ciu_en2_ppx_ip2_s cnf71xx; 896 }; 897 898 union cvmx_ciu_en2_ppx_ip2_w1c { 899 uint64_t u64; 900 struct cvmx_ciu_en2_ppx_ip2_w1c_s { 901 #ifdef __BIG_ENDIAN_BITFIELD 902 uint64_t reserved_15_63:49; 903 uint64_t endor:2; 904 uint64_t eoi:1; 905 uint64_t reserved_10_11:2; 906 uint64_t timer:6; 907 uint64_t reserved_0_3:4; 908 #else 909 uint64_t reserved_0_3:4; 910 uint64_t timer:6; 911 uint64_t reserved_10_11:2; 912 uint64_t eoi:1; 913 uint64_t endor:2; 914 uint64_t reserved_15_63:49; 915 #endif 916 } s; 917 struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx { 918 #ifdef __BIG_ENDIAN_BITFIELD 919 uint64_t reserved_10_63:54; 920 uint64_t timer:6; 921 uint64_t reserved_0_3:4; 922 #else 923 uint64_t reserved_0_3:4; 924 uint64_t timer:6; 925 uint64_t reserved_10_63:54; 926 #endif 927 } cn61xx; 928 struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx; 929 struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx; 930 }; 931 932 union cvmx_ciu_en2_ppx_ip2_w1s { 933 uint64_t u64; 934 struct cvmx_ciu_en2_ppx_ip2_w1s_s { 935 #ifdef __BIG_ENDIAN_BITFIELD 936 uint64_t reserved_15_63:49; 937 uint64_t endor:2; 938 uint64_t eoi:1; 939 uint64_t reserved_10_11:2; 940 uint64_t timer:6; 941 uint64_t reserved_0_3:4; 942 #else 943 uint64_t reserved_0_3:4; 944 uint64_t timer:6; 945 uint64_t reserved_10_11:2; 946 uint64_t eoi:1; 947 uint64_t endor:2; 948 uint64_t reserved_15_63:49; 949 #endif 950 } s; 951 struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx { 952 #ifdef __BIG_ENDIAN_BITFIELD 953 uint64_t reserved_10_63:54; 954 uint64_t timer:6; 955 uint64_t reserved_0_3:4; 956 #else 957 uint64_t reserved_0_3:4; 958 uint64_t timer:6; 959 uint64_t reserved_10_63:54; 960 #endif 961 } cn61xx; 962 struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx; 963 struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx; 964 }; 965 966 union cvmx_ciu_en2_ppx_ip3 { 967 uint64_t u64; 968 struct cvmx_ciu_en2_ppx_ip3_s { 969 #ifdef __BIG_ENDIAN_BITFIELD 970 uint64_t reserved_15_63:49; 971 uint64_t endor:2; 972 uint64_t eoi:1; 973 uint64_t reserved_10_11:2; 974 uint64_t timer:6; 975 uint64_t reserved_0_3:4; 976 #else 977 uint64_t reserved_0_3:4; 978 uint64_t timer:6; 979 uint64_t reserved_10_11:2; 980 uint64_t eoi:1; 981 uint64_t endor:2; 982 uint64_t reserved_15_63:49; 983 #endif 984 } s; 985 struct cvmx_ciu_en2_ppx_ip3_cn61xx { 986 #ifdef __BIG_ENDIAN_BITFIELD 987 uint64_t reserved_10_63:54; 988 uint64_t timer:6; 989 uint64_t reserved_0_3:4; 990 #else 991 uint64_t reserved_0_3:4; 992 uint64_t timer:6; 993 uint64_t reserved_10_63:54; 994 #endif 995 } cn61xx; 996 struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx; 997 struct cvmx_ciu_en2_ppx_ip3_s cnf71xx; 998 }; 999 1000 union cvmx_ciu_en2_ppx_ip3_w1c { 1001 uint64_t u64; 1002 struct cvmx_ciu_en2_ppx_ip3_w1c_s { 1003 #ifdef __BIG_ENDIAN_BITFIELD 1004 uint64_t reserved_15_63:49; 1005 uint64_t endor:2; 1006 uint64_t eoi:1; 1007 uint64_t reserved_10_11:2; 1008 uint64_t timer:6; 1009 uint64_t reserved_0_3:4; 1010 #else 1011 uint64_t reserved_0_3:4; 1012 uint64_t timer:6; 1013 uint64_t reserved_10_11:2; 1014 uint64_t eoi:1; 1015 uint64_t endor:2; 1016 uint64_t reserved_15_63:49; 1017 #endif 1018 } s; 1019 struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx { 1020 #ifdef __BIG_ENDIAN_BITFIELD 1021 uint64_t reserved_10_63:54; 1022 uint64_t timer:6; 1023 uint64_t reserved_0_3:4; 1024 #else 1025 uint64_t reserved_0_3:4; 1026 uint64_t timer:6; 1027 uint64_t reserved_10_63:54; 1028 #endif 1029 } cn61xx; 1030 struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx; 1031 struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx; 1032 }; 1033 1034 union cvmx_ciu_en2_ppx_ip3_w1s { 1035 uint64_t u64; 1036 struct cvmx_ciu_en2_ppx_ip3_w1s_s { 1037 #ifdef __BIG_ENDIAN_BITFIELD 1038 uint64_t reserved_15_63:49; 1039 uint64_t endor:2; 1040 uint64_t eoi:1; 1041 uint64_t reserved_10_11:2; 1042 uint64_t timer:6; 1043 uint64_t reserved_0_3:4; 1044 #else 1045 uint64_t reserved_0_3:4; 1046 uint64_t timer:6; 1047 uint64_t reserved_10_11:2; 1048 uint64_t eoi:1; 1049 uint64_t endor:2; 1050 uint64_t reserved_15_63:49; 1051 #endif 1052 } s; 1053 struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx { 1054 #ifdef __BIG_ENDIAN_BITFIELD 1055 uint64_t reserved_10_63:54; 1056 uint64_t timer:6; 1057 uint64_t reserved_0_3:4; 1058 #else 1059 uint64_t reserved_0_3:4; 1060 uint64_t timer:6; 1061 uint64_t reserved_10_63:54; 1062 #endif 1063 } cn61xx; 1064 struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx; 1065 struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx; 1066 }; 1067 1068 union cvmx_ciu_en2_ppx_ip4 { 1069 uint64_t u64; 1070 struct cvmx_ciu_en2_ppx_ip4_s { 1071 #ifdef __BIG_ENDIAN_BITFIELD 1072 uint64_t reserved_15_63:49; 1073 uint64_t endor:2; 1074 uint64_t eoi:1; 1075 uint64_t reserved_10_11:2; 1076 uint64_t timer:6; 1077 uint64_t reserved_0_3:4; 1078 #else 1079 uint64_t reserved_0_3:4; 1080 uint64_t timer:6; 1081 uint64_t reserved_10_11:2; 1082 uint64_t eoi:1; 1083 uint64_t endor:2; 1084 uint64_t reserved_15_63:49; 1085 #endif 1086 } s; 1087 struct cvmx_ciu_en2_ppx_ip4_cn61xx { 1088 #ifdef __BIG_ENDIAN_BITFIELD 1089 uint64_t reserved_10_63:54; 1090 uint64_t timer:6; 1091 uint64_t reserved_0_3:4; 1092 #else 1093 uint64_t reserved_0_3:4; 1094 uint64_t timer:6; 1095 uint64_t reserved_10_63:54; 1096 #endif 1097 } cn61xx; 1098 struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx; 1099 struct cvmx_ciu_en2_ppx_ip4_s cnf71xx; 1100 }; 1101 1102 union cvmx_ciu_en2_ppx_ip4_w1c { 1103 uint64_t u64; 1104 struct cvmx_ciu_en2_ppx_ip4_w1c_s { 1105 #ifdef __BIG_ENDIAN_BITFIELD 1106 uint64_t reserved_15_63:49; 1107 uint64_t endor:2; 1108 uint64_t eoi:1; 1109 uint64_t reserved_10_11:2; 1110 uint64_t timer:6; 1111 uint64_t reserved_0_3:4; 1112 #else 1113 uint64_t reserved_0_3:4; 1114 uint64_t timer:6; 1115 uint64_t reserved_10_11:2; 1116 uint64_t eoi:1; 1117 uint64_t endor:2; 1118 uint64_t reserved_15_63:49; 1119 #endif 1120 } s; 1121 struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx { 1122 #ifdef __BIG_ENDIAN_BITFIELD 1123 uint64_t reserved_10_63:54; 1124 uint64_t timer:6; 1125 uint64_t reserved_0_3:4; 1126 #else 1127 uint64_t reserved_0_3:4; 1128 uint64_t timer:6; 1129 uint64_t reserved_10_63:54; 1130 #endif 1131 } cn61xx; 1132 struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx; 1133 struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx; 1134 }; 1135 1136 union cvmx_ciu_en2_ppx_ip4_w1s { 1137 uint64_t u64; 1138 struct cvmx_ciu_en2_ppx_ip4_w1s_s { 1139 #ifdef __BIG_ENDIAN_BITFIELD 1140 uint64_t reserved_15_63:49; 1141 uint64_t endor:2; 1142 uint64_t eoi:1; 1143 uint64_t reserved_10_11:2; 1144 uint64_t timer:6; 1145 uint64_t reserved_0_3:4; 1146 #else 1147 uint64_t reserved_0_3:4; 1148 uint64_t timer:6; 1149 uint64_t reserved_10_11:2; 1150 uint64_t eoi:1; 1151 uint64_t endor:2; 1152 uint64_t reserved_15_63:49; 1153 #endif 1154 } s; 1155 struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx { 1156 #ifdef __BIG_ENDIAN_BITFIELD 1157 uint64_t reserved_10_63:54; 1158 uint64_t timer:6; 1159 uint64_t reserved_0_3:4; 1160 #else 1161 uint64_t reserved_0_3:4; 1162 uint64_t timer:6; 1163 uint64_t reserved_10_63:54; 1164 #endif 1165 } cn61xx; 1166 struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx; 1167 struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx; 1168 }; 1169 1170 union cvmx_ciu_fuse { 1171 uint64_t u64; 1172 struct cvmx_ciu_fuse_s { 1173 #ifdef __BIG_ENDIAN_BITFIELD 1174 uint64_t reserved_32_63:32; 1175 uint64_t fuse:32; 1176 #else 1177 uint64_t fuse:32; 1178 uint64_t reserved_32_63:32; 1179 #endif 1180 } s; 1181 struct cvmx_ciu_fuse_cn30xx { 1182 #ifdef __BIG_ENDIAN_BITFIELD 1183 uint64_t reserved_1_63:63; 1184 uint64_t fuse:1; 1185 #else 1186 uint64_t fuse:1; 1187 uint64_t reserved_1_63:63; 1188 #endif 1189 } cn30xx; 1190 struct cvmx_ciu_fuse_cn31xx { 1191 #ifdef __BIG_ENDIAN_BITFIELD 1192 uint64_t reserved_2_63:62; 1193 uint64_t fuse:2; 1194 #else 1195 uint64_t fuse:2; 1196 uint64_t reserved_2_63:62; 1197 #endif 1198 } cn31xx; 1199 struct cvmx_ciu_fuse_cn38xx { 1200 #ifdef __BIG_ENDIAN_BITFIELD 1201 uint64_t reserved_16_63:48; 1202 uint64_t fuse:16; 1203 #else 1204 uint64_t fuse:16; 1205 uint64_t reserved_16_63:48; 1206 #endif 1207 } cn38xx; 1208 struct cvmx_ciu_fuse_cn38xx cn38xxp2; 1209 struct cvmx_ciu_fuse_cn31xx cn50xx; 1210 struct cvmx_ciu_fuse_cn52xx { 1211 #ifdef __BIG_ENDIAN_BITFIELD 1212 uint64_t reserved_4_63:60; 1213 uint64_t fuse:4; 1214 #else 1215 uint64_t fuse:4; 1216 uint64_t reserved_4_63:60; 1217 #endif 1218 } cn52xx; 1219 struct cvmx_ciu_fuse_cn52xx cn52xxp1; 1220 struct cvmx_ciu_fuse_cn56xx { 1221 #ifdef __BIG_ENDIAN_BITFIELD 1222 uint64_t reserved_12_63:52; 1223 uint64_t fuse:12; 1224 #else 1225 uint64_t fuse:12; 1226 uint64_t reserved_12_63:52; 1227 #endif 1228 } cn56xx; 1229 struct cvmx_ciu_fuse_cn56xx cn56xxp1; 1230 struct cvmx_ciu_fuse_cn38xx cn58xx; 1231 struct cvmx_ciu_fuse_cn38xx cn58xxp1; 1232 struct cvmx_ciu_fuse_cn52xx cn61xx; 1233 struct cvmx_ciu_fuse_cn63xx { 1234 #ifdef __BIG_ENDIAN_BITFIELD 1235 uint64_t reserved_6_63:58; 1236 uint64_t fuse:6; 1237 #else 1238 uint64_t fuse:6; 1239 uint64_t reserved_6_63:58; 1240 #endif 1241 } cn63xx; 1242 struct cvmx_ciu_fuse_cn63xx cn63xxp1; 1243 struct cvmx_ciu_fuse_cn66xx { 1244 #ifdef __BIG_ENDIAN_BITFIELD 1245 uint64_t reserved_10_63:54; 1246 uint64_t fuse:10; 1247 #else 1248 uint64_t fuse:10; 1249 uint64_t reserved_10_63:54; 1250 #endif 1251 } cn66xx; 1252 struct cvmx_ciu_fuse_s cn68xx; 1253 struct cvmx_ciu_fuse_s cn68xxp1; 1254 struct cvmx_ciu_fuse_cn52xx cnf71xx; 1255 }; 1256 1257 union cvmx_ciu_gstop { 1258 uint64_t u64; 1259 struct cvmx_ciu_gstop_s { 1260 #ifdef __BIG_ENDIAN_BITFIELD 1261 uint64_t reserved_1_63:63; 1262 uint64_t gstop:1; 1263 #else 1264 uint64_t gstop:1; 1265 uint64_t reserved_1_63:63; 1266 #endif 1267 } s; 1268 struct cvmx_ciu_gstop_s cn30xx; 1269 struct cvmx_ciu_gstop_s cn31xx; 1270 struct cvmx_ciu_gstop_s cn38xx; 1271 struct cvmx_ciu_gstop_s cn38xxp2; 1272 struct cvmx_ciu_gstop_s cn50xx; 1273 struct cvmx_ciu_gstop_s cn52xx; 1274 struct cvmx_ciu_gstop_s cn52xxp1; 1275 struct cvmx_ciu_gstop_s cn56xx; 1276 struct cvmx_ciu_gstop_s cn56xxp1; 1277 struct cvmx_ciu_gstop_s cn58xx; 1278 struct cvmx_ciu_gstop_s cn58xxp1; 1279 struct cvmx_ciu_gstop_s cn61xx; 1280 struct cvmx_ciu_gstop_s cn63xx; 1281 struct cvmx_ciu_gstop_s cn63xxp1; 1282 struct cvmx_ciu_gstop_s cn66xx; 1283 struct cvmx_ciu_gstop_s cn68xx; 1284 struct cvmx_ciu_gstop_s cn68xxp1; 1285 struct cvmx_ciu_gstop_s cnf71xx; 1286 }; 1287 1288 union cvmx_ciu_intx_en0 { 1289 uint64_t u64; 1290 struct cvmx_ciu_intx_en0_s { 1291 #ifdef __BIG_ENDIAN_BITFIELD 1292 uint64_t bootdma:1; 1293 uint64_t mii:1; 1294 uint64_t ipdppthr:1; 1295 uint64_t powiq:1; 1296 uint64_t twsi2:1; 1297 uint64_t mpi:1; 1298 uint64_t pcm:1; 1299 uint64_t usb:1; 1300 uint64_t timer:4; 1301 uint64_t key_zero:1; 1302 uint64_t ipd_drp:1; 1303 uint64_t gmx_drp:2; 1304 uint64_t trace:1; 1305 uint64_t rml:1; 1306 uint64_t twsi:1; 1307 uint64_t reserved_44_44:1; 1308 uint64_t pci_msi:4; 1309 uint64_t pci_int:4; 1310 uint64_t uart:2; 1311 uint64_t mbox:2; 1312 uint64_t gpio:16; 1313 uint64_t workq:16; 1314 #else 1315 uint64_t workq:16; 1316 uint64_t gpio:16; 1317 uint64_t mbox:2; 1318 uint64_t uart:2; 1319 uint64_t pci_int:4; 1320 uint64_t pci_msi:4; 1321 uint64_t reserved_44_44:1; 1322 uint64_t twsi:1; 1323 uint64_t rml:1; 1324 uint64_t trace:1; 1325 uint64_t gmx_drp:2; 1326 uint64_t ipd_drp:1; 1327 uint64_t key_zero:1; 1328 uint64_t timer:4; 1329 uint64_t usb:1; 1330 uint64_t pcm:1; 1331 uint64_t mpi:1; 1332 uint64_t twsi2:1; 1333 uint64_t powiq:1; 1334 uint64_t ipdppthr:1; 1335 uint64_t mii:1; 1336 uint64_t bootdma:1; 1337 #endif 1338 } s; 1339 struct cvmx_ciu_intx_en0_cn30xx { 1340 #ifdef __BIG_ENDIAN_BITFIELD 1341 uint64_t reserved_59_63:5; 1342 uint64_t mpi:1; 1343 uint64_t pcm:1; 1344 uint64_t usb:1; 1345 uint64_t timer:4; 1346 uint64_t reserved_51_51:1; 1347 uint64_t ipd_drp:1; 1348 uint64_t reserved_49_49:1; 1349 uint64_t gmx_drp:1; 1350 uint64_t reserved_47_47:1; 1351 uint64_t rml:1; 1352 uint64_t twsi:1; 1353 uint64_t reserved_44_44:1; 1354 uint64_t pci_msi:4; 1355 uint64_t pci_int:4; 1356 uint64_t uart:2; 1357 uint64_t mbox:2; 1358 uint64_t gpio:16; 1359 uint64_t workq:16; 1360 #else 1361 uint64_t workq:16; 1362 uint64_t gpio:16; 1363 uint64_t mbox:2; 1364 uint64_t uart:2; 1365 uint64_t pci_int:4; 1366 uint64_t pci_msi:4; 1367 uint64_t reserved_44_44:1; 1368 uint64_t twsi:1; 1369 uint64_t rml:1; 1370 uint64_t reserved_47_47:1; 1371 uint64_t gmx_drp:1; 1372 uint64_t reserved_49_49:1; 1373 uint64_t ipd_drp:1; 1374 uint64_t reserved_51_51:1; 1375 uint64_t timer:4; 1376 uint64_t usb:1; 1377 uint64_t pcm:1; 1378 uint64_t mpi:1; 1379 uint64_t reserved_59_63:5; 1380 #endif 1381 } cn30xx; 1382 struct cvmx_ciu_intx_en0_cn31xx { 1383 #ifdef __BIG_ENDIAN_BITFIELD 1384 uint64_t reserved_59_63:5; 1385 uint64_t mpi:1; 1386 uint64_t pcm:1; 1387 uint64_t usb:1; 1388 uint64_t timer:4; 1389 uint64_t reserved_51_51:1; 1390 uint64_t ipd_drp:1; 1391 uint64_t reserved_49_49:1; 1392 uint64_t gmx_drp:1; 1393 uint64_t trace:1; 1394 uint64_t rml:1; 1395 uint64_t twsi:1; 1396 uint64_t reserved_44_44:1; 1397 uint64_t pci_msi:4; 1398 uint64_t pci_int:4; 1399 uint64_t uart:2; 1400 uint64_t mbox:2; 1401 uint64_t gpio:16; 1402 uint64_t workq:16; 1403 #else 1404 uint64_t workq:16; 1405 uint64_t gpio:16; 1406 uint64_t mbox:2; 1407 uint64_t uart:2; 1408 uint64_t pci_int:4; 1409 uint64_t pci_msi:4; 1410 uint64_t reserved_44_44:1; 1411 uint64_t twsi:1; 1412 uint64_t rml:1; 1413 uint64_t trace:1; 1414 uint64_t gmx_drp:1; 1415 uint64_t reserved_49_49:1; 1416 uint64_t ipd_drp:1; 1417 uint64_t reserved_51_51:1; 1418 uint64_t timer:4; 1419 uint64_t usb:1; 1420 uint64_t pcm:1; 1421 uint64_t mpi:1; 1422 uint64_t reserved_59_63:5; 1423 #endif 1424 } cn31xx; 1425 struct cvmx_ciu_intx_en0_cn38xx { 1426 #ifdef __BIG_ENDIAN_BITFIELD 1427 uint64_t reserved_56_63:8; 1428 uint64_t timer:4; 1429 uint64_t key_zero:1; 1430 uint64_t ipd_drp:1; 1431 uint64_t gmx_drp:2; 1432 uint64_t trace:1; 1433 uint64_t rml:1; 1434 uint64_t twsi:1; 1435 uint64_t reserved_44_44:1; 1436 uint64_t pci_msi:4; 1437 uint64_t pci_int:4; 1438 uint64_t uart:2; 1439 uint64_t mbox:2; 1440 uint64_t gpio:16; 1441 uint64_t workq:16; 1442 #else 1443 uint64_t workq:16; 1444 uint64_t gpio:16; 1445 uint64_t mbox:2; 1446 uint64_t uart:2; 1447 uint64_t pci_int:4; 1448 uint64_t pci_msi:4; 1449 uint64_t reserved_44_44:1; 1450 uint64_t twsi:1; 1451 uint64_t rml:1; 1452 uint64_t trace:1; 1453 uint64_t gmx_drp:2; 1454 uint64_t ipd_drp:1; 1455 uint64_t key_zero:1; 1456 uint64_t timer:4; 1457 uint64_t reserved_56_63:8; 1458 #endif 1459 } cn38xx; 1460 struct cvmx_ciu_intx_en0_cn38xx cn38xxp2; 1461 struct cvmx_ciu_intx_en0_cn30xx cn50xx; 1462 struct cvmx_ciu_intx_en0_cn52xx { 1463 #ifdef __BIG_ENDIAN_BITFIELD 1464 uint64_t bootdma:1; 1465 uint64_t mii:1; 1466 uint64_t ipdppthr:1; 1467 uint64_t powiq:1; 1468 uint64_t twsi2:1; 1469 uint64_t reserved_57_58:2; 1470 uint64_t usb:1; 1471 uint64_t timer:4; 1472 uint64_t reserved_51_51:1; 1473 uint64_t ipd_drp:1; 1474 uint64_t reserved_49_49:1; 1475 uint64_t gmx_drp:1; 1476 uint64_t trace:1; 1477 uint64_t rml:1; 1478 uint64_t twsi:1; 1479 uint64_t reserved_44_44:1; 1480 uint64_t pci_msi:4; 1481 uint64_t pci_int:4; 1482 uint64_t uart:2; 1483 uint64_t mbox:2; 1484 uint64_t gpio:16; 1485 uint64_t workq:16; 1486 #else 1487 uint64_t workq:16; 1488 uint64_t gpio:16; 1489 uint64_t mbox:2; 1490 uint64_t uart:2; 1491 uint64_t pci_int:4; 1492 uint64_t pci_msi:4; 1493 uint64_t reserved_44_44:1; 1494 uint64_t twsi:1; 1495 uint64_t rml:1; 1496 uint64_t trace:1; 1497 uint64_t gmx_drp:1; 1498 uint64_t reserved_49_49:1; 1499 uint64_t ipd_drp:1; 1500 uint64_t reserved_51_51:1; 1501 uint64_t timer:4; 1502 uint64_t usb:1; 1503 uint64_t reserved_57_58:2; 1504 uint64_t twsi2:1; 1505 uint64_t powiq:1; 1506 uint64_t ipdppthr:1; 1507 uint64_t mii:1; 1508 uint64_t bootdma:1; 1509 #endif 1510 } cn52xx; 1511 struct cvmx_ciu_intx_en0_cn52xx cn52xxp1; 1512 struct cvmx_ciu_intx_en0_cn56xx { 1513 #ifdef __BIG_ENDIAN_BITFIELD 1514 uint64_t bootdma:1; 1515 uint64_t mii:1; 1516 uint64_t ipdppthr:1; 1517 uint64_t powiq:1; 1518 uint64_t twsi2:1; 1519 uint64_t reserved_57_58:2; 1520 uint64_t usb:1; 1521 uint64_t timer:4; 1522 uint64_t key_zero:1; 1523 uint64_t ipd_drp:1; 1524 uint64_t gmx_drp:2; 1525 uint64_t trace:1; 1526 uint64_t rml:1; 1527 uint64_t twsi:1; 1528 uint64_t reserved_44_44:1; 1529 uint64_t pci_msi:4; 1530 uint64_t pci_int:4; 1531 uint64_t uart:2; 1532 uint64_t mbox:2; 1533 uint64_t gpio:16; 1534 uint64_t workq:16; 1535 #else 1536 uint64_t workq:16; 1537 uint64_t gpio:16; 1538 uint64_t mbox:2; 1539 uint64_t uart:2; 1540 uint64_t pci_int:4; 1541 uint64_t pci_msi:4; 1542 uint64_t reserved_44_44:1; 1543 uint64_t twsi:1; 1544 uint64_t rml:1; 1545 uint64_t trace:1; 1546 uint64_t gmx_drp:2; 1547 uint64_t ipd_drp:1; 1548 uint64_t key_zero:1; 1549 uint64_t timer:4; 1550 uint64_t usb:1; 1551 uint64_t reserved_57_58:2; 1552 uint64_t twsi2:1; 1553 uint64_t powiq:1; 1554 uint64_t ipdppthr:1; 1555 uint64_t mii:1; 1556 uint64_t bootdma:1; 1557 #endif 1558 } cn56xx; 1559 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; 1560 struct cvmx_ciu_intx_en0_cn38xx cn58xx; 1561 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; 1562 struct cvmx_ciu_intx_en0_cn61xx { 1563 #ifdef __BIG_ENDIAN_BITFIELD 1564 uint64_t bootdma:1; 1565 uint64_t mii:1; 1566 uint64_t ipdppthr:1; 1567 uint64_t powiq:1; 1568 uint64_t twsi2:1; 1569 uint64_t mpi:1; 1570 uint64_t pcm:1; 1571 uint64_t usb:1; 1572 uint64_t timer:4; 1573 uint64_t reserved_51_51:1; 1574 uint64_t ipd_drp:1; 1575 uint64_t gmx_drp:2; 1576 uint64_t trace:1; 1577 uint64_t rml:1; 1578 uint64_t twsi:1; 1579 uint64_t reserved_44_44:1; 1580 uint64_t pci_msi:4; 1581 uint64_t pci_int:4; 1582 uint64_t uart:2; 1583 uint64_t mbox:2; 1584 uint64_t gpio:16; 1585 uint64_t workq:16; 1586 #else 1587 uint64_t workq:16; 1588 uint64_t gpio:16; 1589 uint64_t mbox:2; 1590 uint64_t uart:2; 1591 uint64_t pci_int:4; 1592 uint64_t pci_msi:4; 1593 uint64_t reserved_44_44:1; 1594 uint64_t twsi:1; 1595 uint64_t rml:1; 1596 uint64_t trace:1; 1597 uint64_t gmx_drp:2; 1598 uint64_t ipd_drp:1; 1599 uint64_t reserved_51_51:1; 1600 uint64_t timer:4; 1601 uint64_t usb:1; 1602 uint64_t pcm:1; 1603 uint64_t mpi:1; 1604 uint64_t twsi2:1; 1605 uint64_t powiq:1; 1606 uint64_t ipdppthr:1; 1607 uint64_t mii:1; 1608 uint64_t bootdma:1; 1609 #endif 1610 } cn61xx; 1611 struct cvmx_ciu_intx_en0_cn52xx cn63xx; 1612 struct cvmx_ciu_intx_en0_cn52xx cn63xxp1; 1613 struct cvmx_ciu_intx_en0_cn66xx { 1614 #ifdef __BIG_ENDIAN_BITFIELD 1615 uint64_t bootdma:1; 1616 uint64_t mii:1; 1617 uint64_t ipdppthr:1; 1618 uint64_t powiq:1; 1619 uint64_t twsi2:1; 1620 uint64_t mpi:1; 1621 uint64_t reserved_57_57:1; 1622 uint64_t usb:1; 1623 uint64_t timer:4; 1624 uint64_t reserved_51_51:1; 1625 uint64_t ipd_drp:1; 1626 uint64_t gmx_drp:2; 1627 uint64_t trace:1; 1628 uint64_t rml:1; 1629 uint64_t twsi:1; 1630 uint64_t reserved_44_44:1; 1631 uint64_t pci_msi:4; 1632 uint64_t pci_int:4; 1633 uint64_t uart:2; 1634 uint64_t mbox:2; 1635 uint64_t gpio:16; 1636 uint64_t workq:16; 1637 #else 1638 uint64_t workq:16; 1639 uint64_t gpio:16; 1640 uint64_t mbox:2; 1641 uint64_t uart:2; 1642 uint64_t pci_int:4; 1643 uint64_t pci_msi:4; 1644 uint64_t reserved_44_44:1; 1645 uint64_t twsi:1; 1646 uint64_t rml:1; 1647 uint64_t trace:1; 1648 uint64_t gmx_drp:2; 1649 uint64_t ipd_drp:1; 1650 uint64_t reserved_51_51:1; 1651 uint64_t timer:4; 1652 uint64_t usb:1; 1653 uint64_t reserved_57_57:1; 1654 uint64_t mpi:1; 1655 uint64_t twsi2:1; 1656 uint64_t powiq:1; 1657 uint64_t ipdppthr:1; 1658 uint64_t mii:1; 1659 uint64_t bootdma:1; 1660 #endif 1661 } cn66xx; 1662 struct cvmx_ciu_intx_en0_cnf71xx { 1663 #ifdef __BIG_ENDIAN_BITFIELD 1664 uint64_t bootdma:1; 1665 uint64_t reserved_62_62:1; 1666 uint64_t ipdppthr:1; 1667 uint64_t powiq:1; 1668 uint64_t twsi2:1; 1669 uint64_t mpi:1; 1670 uint64_t pcm:1; 1671 uint64_t usb:1; 1672 uint64_t timer:4; 1673 uint64_t reserved_51_51:1; 1674 uint64_t ipd_drp:1; 1675 uint64_t reserved_49_49:1; 1676 uint64_t gmx_drp:1; 1677 uint64_t trace:1; 1678 uint64_t rml:1; 1679 uint64_t twsi:1; 1680 uint64_t reserved_44_44:1; 1681 uint64_t pci_msi:4; 1682 uint64_t pci_int:4; 1683 uint64_t uart:2; 1684 uint64_t mbox:2; 1685 uint64_t gpio:16; 1686 uint64_t workq:16; 1687 #else 1688 uint64_t workq:16; 1689 uint64_t gpio:16; 1690 uint64_t mbox:2; 1691 uint64_t uart:2; 1692 uint64_t pci_int:4; 1693 uint64_t pci_msi:4; 1694 uint64_t reserved_44_44:1; 1695 uint64_t twsi:1; 1696 uint64_t rml:1; 1697 uint64_t trace:1; 1698 uint64_t gmx_drp:1; 1699 uint64_t reserved_49_49:1; 1700 uint64_t ipd_drp:1; 1701 uint64_t reserved_51_51:1; 1702 uint64_t timer:4; 1703 uint64_t usb:1; 1704 uint64_t pcm:1; 1705 uint64_t mpi:1; 1706 uint64_t twsi2:1; 1707 uint64_t powiq:1; 1708 uint64_t ipdppthr:1; 1709 uint64_t reserved_62_62:1; 1710 uint64_t bootdma:1; 1711 #endif 1712 } cnf71xx; 1713 }; 1714 1715 union cvmx_ciu_intx_en0_w1c { 1716 uint64_t u64; 1717 struct cvmx_ciu_intx_en0_w1c_s { 1718 #ifdef __BIG_ENDIAN_BITFIELD 1719 uint64_t bootdma:1; 1720 uint64_t mii:1; 1721 uint64_t ipdppthr:1; 1722 uint64_t powiq:1; 1723 uint64_t twsi2:1; 1724 uint64_t mpi:1; 1725 uint64_t pcm:1; 1726 uint64_t usb:1; 1727 uint64_t timer:4; 1728 uint64_t key_zero:1; 1729 uint64_t ipd_drp:1; 1730 uint64_t gmx_drp:2; 1731 uint64_t trace:1; 1732 uint64_t rml:1; 1733 uint64_t twsi:1; 1734 uint64_t reserved_44_44:1; 1735 uint64_t pci_msi:4; 1736 uint64_t pci_int:4; 1737 uint64_t uart:2; 1738 uint64_t mbox:2; 1739 uint64_t gpio:16; 1740 uint64_t workq:16; 1741 #else 1742 uint64_t workq:16; 1743 uint64_t gpio:16; 1744 uint64_t mbox:2; 1745 uint64_t uart:2; 1746 uint64_t pci_int:4; 1747 uint64_t pci_msi:4; 1748 uint64_t reserved_44_44:1; 1749 uint64_t twsi:1; 1750 uint64_t rml:1; 1751 uint64_t trace:1; 1752 uint64_t gmx_drp:2; 1753 uint64_t ipd_drp:1; 1754 uint64_t key_zero:1; 1755 uint64_t timer:4; 1756 uint64_t usb:1; 1757 uint64_t pcm:1; 1758 uint64_t mpi:1; 1759 uint64_t twsi2:1; 1760 uint64_t powiq:1; 1761 uint64_t ipdppthr:1; 1762 uint64_t mii:1; 1763 uint64_t bootdma:1; 1764 #endif 1765 } s; 1766 struct cvmx_ciu_intx_en0_w1c_cn52xx { 1767 #ifdef __BIG_ENDIAN_BITFIELD 1768 uint64_t bootdma:1; 1769 uint64_t mii:1; 1770 uint64_t ipdppthr:1; 1771 uint64_t powiq:1; 1772 uint64_t twsi2:1; 1773 uint64_t reserved_57_58:2; 1774 uint64_t usb:1; 1775 uint64_t timer:4; 1776 uint64_t reserved_51_51:1; 1777 uint64_t ipd_drp:1; 1778 uint64_t reserved_49_49:1; 1779 uint64_t gmx_drp:1; 1780 uint64_t trace:1; 1781 uint64_t rml:1; 1782 uint64_t twsi:1; 1783 uint64_t reserved_44_44:1; 1784 uint64_t pci_msi:4; 1785 uint64_t pci_int:4; 1786 uint64_t uart:2; 1787 uint64_t mbox:2; 1788 uint64_t gpio:16; 1789 uint64_t workq:16; 1790 #else 1791 uint64_t workq:16; 1792 uint64_t gpio:16; 1793 uint64_t mbox:2; 1794 uint64_t uart:2; 1795 uint64_t pci_int:4; 1796 uint64_t pci_msi:4; 1797 uint64_t reserved_44_44:1; 1798 uint64_t twsi:1; 1799 uint64_t rml:1; 1800 uint64_t trace:1; 1801 uint64_t gmx_drp:1; 1802 uint64_t reserved_49_49:1; 1803 uint64_t ipd_drp:1; 1804 uint64_t reserved_51_51:1; 1805 uint64_t timer:4; 1806 uint64_t usb:1; 1807 uint64_t reserved_57_58:2; 1808 uint64_t twsi2:1; 1809 uint64_t powiq:1; 1810 uint64_t ipdppthr:1; 1811 uint64_t mii:1; 1812 uint64_t bootdma:1; 1813 #endif 1814 } cn52xx; 1815 struct cvmx_ciu_intx_en0_w1c_cn56xx { 1816 #ifdef __BIG_ENDIAN_BITFIELD 1817 uint64_t bootdma:1; 1818 uint64_t mii:1; 1819 uint64_t ipdppthr:1; 1820 uint64_t powiq:1; 1821 uint64_t twsi2:1; 1822 uint64_t reserved_57_58:2; 1823 uint64_t usb:1; 1824 uint64_t timer:4; 1825 uint64_t key_zero:1; 1826 uint64_t ipd_drp:1; 1827 uint64_t gmx_drp:2; 1828 uint64_t trace:1; 1829 uint64_t rml:1; 1830 uint64_t twsi:1; 1831 uint64_t reserved_44_44:1; 1832 uint64_t pci_msi:4; 1833 uint64_t pci_int:4; 1834 uint64_t uart:2; 1835 uint64_t mbox:2; 1836 uint64_t gpio:16; 1837 uint64_t workq:16; 1838 #else 1839 uint64_t workq:16; 1840 uint64_t gpio:16; 1841 uint64_t mbox:2; 1842 uint64_t uart:2; 1843 uint64_t pci_int:4; 1844 uint64_t pci_msi:4; 1845 uint64_t reserved_44_44:1; 1846 uint64_t twsi:1; 1847 uint64_t rml:1; 1848 uint64_t trace:1; 1849 uint64_t gmx_drp:2; 1850 uint64_t ipd_drp:1; 1851 uint64_t key_zero:1; 1852 uint64_t timer:4; 1853 uint64_t usb:1; 1854 uint64_t reserved_57_58:2; 1855 uint64_t twsi2:1; 1856 uint64_t powiq:1; 1857 uint64_t ipdppthr:1; 1858 uint64_t mii:1; 1859 uint64_t bootdma:1; 1860 #endif 1861 } cn56xx; 1862 struct cvmx_ciu_intx_en0_w1c_cn58xx { 1863 #ifdef __BIG_ENDIAN_BITFIELD 1864 uint64_t reserved_56_63:8; 1865 uint64_t timer:4; 1866 uint64_t key_zero:1; 1867 uint64_t ipd_drp:1; 1868 uint64_t gmx_drp:2; 1869 uint64_t trace:1; 1870 uint64_t rml:1; 1871 uint64_t twsi:1; 1872 uint64_t reserved_44_44:1; 1873 uint64_t pci_msi:4; 1874 uint64_t pci_int:4; 1875 uint64_t uart:2; 1876 uint64_t mbox:2; 1877 uint64_t gpio:16; 1878 uint64_t workq:16; 1879 #else 1880 uint64_t workq:16; 1881 uint64_t gpio:16; 1882 uint64_t mbox:2; 1883 uint64_t uart:2; 1884 uint64_t pci_int:4; 1885 uint64_t pci_msi:4; 1886 uint64_t reserved_44_44:1; 1887 uint64_t twsi:1; 1888 uint64_t rml:1; 1889 uint64_t trace:1; 1890 uint64_t gmx_drp:2; 1891 uint64_t ipd_drp:1; 1892 uint64_t key_zero:1; 1893 uint64_t timer:4; 1894 uint64_t reserved_56_63:8; 1895 #endif 1896 } cn58xx; 1897 struct cvmx_ciu_intx_en0_w1c_cn61xx { 1898 #ifdef __BIG_ENDIAN_BITFIELD 1899 uint64_t bootdma:1; 1900 uint64_t mii:1; 1901 uint64_t ipdppthr:1; 1902 uint64_t powiq:1; 1903 uint64_t twsi2:1; 1904 uint64_t mpi:1; 1905 uint64_t pcm:1; 1906 uint64_t usb:1; 1907 uint64_t timer:4; 1908 uint64_t reserved_51_51:1; 1909 uint64_t ipd_drp:1; 1910 uint64_t gmx_drp:2; 1911 uint64_t trace:1; 1912 uint64_t rml:1; 1913 uint64_t twsi:1; 1914 uint64_t reserved_44_44:1; 1915 uint64_t pci_msi:4; 1916 uint64_t pci_int:4; 1917 uint64_t uart:2; 1918 uint64_t mbox:2; 1919 uint64_t gpio:16; 1920 uint64_t workq:16; 1921 #else 1922 uint64_t workq:16; 1923 uint64_t gpio:16; 1924 uint64_t mbox:2; 1925 uint64_t uart:2; 1926 uint64_t pci_int:4; 1927 uint64_t pci_msi:4; 1928 uint64_t reserved_44_44:1; 1929 uint64_t twsi:1; 1930 uint64_t rml:1; 1931 uint64_t trace:1; 1932 uint64_t gmx_drp:2; 1933 uint64_t ipd_drp:1; 1934 uint64_t reserved_51_51:1; 1935 uint64_t timer:4; 1936 uint64_t usb:1; 1937 uint64_t pcm:1; 1938 uint64_t mpi:1; 1939 uint64_t twsi2:1; 1940 uint64_t powiq:1; 1941 uint64_t ipdppthr:1; 1942 uint64_t mii:1; 1943 uint64_t bootdma:1; 1944 #endif 1945 } cn61xx; 1946 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx; 1947 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1; 1948 struct cvmx_ciu_intx_en0_w1c_cn66xx { 1949 #ifdef __BIG_ENDIAN_BITFIELD 1950 uint64_t bootdma:1; 1951 uint64_t mii:1; 1952 uint64_t ipdppthr:1; 1953 uint64_t powiq:1; 1954 uint64_t twsi2:1; 1955 uint64_t mpi:1; 1956 uint64_t reserved_57_57:1; 1957 uint64_t usb:1; 1958 uint64_t timer:4; 1959 uint64_t reserved_51_51:1; 1960 uint64_t ipd_drp:1; 1961 uint64_t gmx_drp:2; 1962 uint64_t trace:1; 1963 uint64_t rml:1; 1964 uint64_t twsi:1; 1965 uint64_t reserved_44_44:1; 1966 uint64_t pci_msi:4; 1967 uint64_t pci_int:4; 1968 uint64_t uart:2; 1969 uint64_t mbox:2; 1970 uint64_t gpio:16; 1971 uint64_t workq:16; 1972 #else 1973 uint64_t workq:16; 1974 uint64_t gpio:16; 1975 uint64_t mbox:2; 1976 uint64_t uart:2; 1977 uint64_t pci_int:4; 1978 uint64_t pci_msi:4; 1979 uint64_t reserved_44_44:1; 1980 uint64_t twsi:1; 1981 uint64_t rml:1; 1982 uint64_t trace:1; 1983 uint64_t gmx_drp:2; 1984 uint64_t ipd_drp:1; 1985 uint64_t reserved_51_51:1; 1986 uint64_t timer:4; 1987 uint64_t usb:1; 1988 uint64_t reserved_57_57:1; 1989 uint64_t mpi:1; 1990 uint64_t twsi2:1; 1991 uint64_t powiq:1; 1992 uint64_t ipdppthr:1; 1993 uint64_t mii:1; 1994 uint64_t bootdma:1; 1995 #endif 1996 } cn66xx; 1997 struct cvmx_ciu_intx_en0_w1c_cnf71xx { 1998 #ifdef __BIG_ENDIAN_BITFIELD 1999 uint64_t bootdma:1; 2000 uint64_t reserved_62_62:1; 2001 uint64_t ipdppthr:1; 2002 uint64_t powiq:1; 2003 uint64_t twsi2:1; 2004 uint64_t mpi:1; 2005 uint64_t pcm:1; 2006 uint64_t usb:1; 2007 uint64_t timer:4; 2008 uint64_t reserved_51_51:1; 2009 uint64_t ipd_drp:1; 2010 uint64_t reserved_49_49:1; 2011 uint64_t gmx_drp:1; 2012 uint64_t trace:1; 2013 uint64_t rml:1; 2014 uint64_t twsi:1; 2015 uint64_t reserved_44_44:1; 2016 uint64_t pci_msi:4; 2017 uint64_t pci_int:4; 2018 uint64_t uart:2; 2019 uint64_t mbox:2; 2020 uint64_t gpio:16; 2021 uint64_t workq:16; 2022 #else 2023 uint64_t workq:16; 2024 uint64_t gpio:16; 2025 uint64_t mbox:2; 2026 uint64_t uart:2; 2027 uint64_t pci_int:4; 2028 uint64_t pci_msi:4; 2029 uint64_t reserved_44_44:1; 2030 uint64_t twsi:1; 2031 uint64_t rml:1; 2032 uint64_t trace:1; 2033 uint64_t gmx_drp:1; 2034 uint64_t reserved_49_49:1; 2035 uint64_t ipd_drp:1; 2036 uint64_t reserved_51_51:1; 2037 uint64_t timer:4; 2038 uint64_t usb:1; 2039 uint64_t pcm:1; 2040 uint64_t mpi:1; 2041 uint64_t twsi2:1; 2042 uint64_t powiq:1; 2043 uint64_t ipdppthr:1; 2044 uint64_t reserved_62_62:1; 2045 uint64_t bootdma:1; 2046 #endif 2047 } cnf71xx; 2048 }; 2049 2050 union cvmx_ciu_intx_en0_w1s { 2051 uint64_t u64; 2052 struct cvmx_ciu_intx_en0_w1s_s { 2053 #ifdef __BIG_ENDIAN_BITFIELD 2054 uint64_t bootdma:1; 2055 uint64_t mii:1; 2056 uint64_t ipdppthr:1; 2057 uint64_t powiq:1; 2058 uint64_t twsi2:1; 2059 uint64_t mpi:1; 2060 uint64_t pcm:1; 2061 uint64_t usb:1; 2062 uint64_t timer:4; 2063 uint64_t key_zero:1; 2064 uint64_t ipd_drp:1; 2065 uint64_t gmx_drp:2; 2066 uint64_t trace:1; 2067 uint64_t rml:1; 2068 uint64_t twsi:1; 2069 uint64_t reserved_44_44:1; 2070 uint64_t pci_msi:4; 2071 uint64_t pci_int:4; 2072 uint64_t uart:2; 2073 uint64_t mbox:2; 2074 uint64_t gpio:16; 2075 uint64_t workq:16; 2076 #else 2077 uint64_t workq:16; 2078 uint64_t gpio:16; 2079 uint64_t mbox:2; 2080 uint64_t uart:2; 2081 uint64_t pci_int:4; 2082 uint64_t pci_msi:4; 2083 uint64_t reserved_44_44:1; 2084 uint64_t twsi:1; 2085 uint64_t rml:1; 2086 uint64_t trace:1; 2087 uint64_t gmx_drp:2; 2088 uint64_t ipd_drp:1; 2089 uint64_t key_zero:1; 2090 uint64_t timer:4; 2091 uint64_t usb:1; 2092 uint64_t pcm:1; 2093 uint64_t mpi:1; 2094 uint64_t twsi2:1; 2095 uint64_t powiq:1; 2096 uint64_t ipdppthr:1; 2097 uint64_t mii:1; 2098 uint64_t bootdma:1; 2099 #endif 2100 } s; 2101 struct cvmx_ciu_intx_en0_w1s_cn52xx { 2102 #ifdef __BIG_ENDIAN_BITFIELD 2103 uint64_t bootdma:1; 2104 uint64_t mii:1; 2105 uint64_t ipdppthr:1; 2106 uint64_t powiq:1; 2107 uint64_t twsi2:1; 2108 uint64_t reserved_57_58:2; 2109 uint64_t usb:1; 2110 uint64_t timer:4; 2111 uint64_t reserved_51_51:1; 2112 uint64_t ipd_drp:1; 2113 uint64_t reserved_49_49:1; 2114 uint64_t gmx_drp:1; 2115 uint64_t trace:1; 2116 uint64_t rml:1; 2117 uint64_t twsi:1; 2118 uint64_t reserved_44_44:1; 2119 uint64_t pci_msi:4; 2120 uint64_t pci_int:4; 2121 uint64_t uart:2; 2122 uint64_t mbox:2; 2123 uint64_t gpio:16; 2124 uint64_t workq:16; 2125 #else 2126 uint64_t workq:16; 2127 uint64_t gpio:16; 2128 uint64_t mbox:2; 2129 uint64_t uart:2; 2130 uint64_t pci_int:4; 2131 uint64_t pci_msi:4; 2132 uint64_t reserved_44_44:1; 2133 uint64_t twsi:1; 2134 uint64_t rml:1; 2135 uint64_t trace:1; 2136 uint64_t gmx_drp:1; 2137 uint64_t reserved_49_49:1; 2138 uint64_t ipd_drp:1; 2139 uint64_t reserved_51_51:1; 2140 uint64_t timer:4; 2141 uint64_t usb:1; 2142 uint64_t reserved_57_58:2; 2143 uint64_t twsi2:1; 2144 uint64_t powiq:1; 2145 uint64_t ipdppthr:1; 2146 uint64_t mii:1; 2147 uint64_t bootdma:1; 2148 #endif 2149 } cn52xx; 2150 struct cvmx_ciu_intx_en0_w1s_cn56xx { 2151 #ifdef __BIG_ENDIAN_BITFIELD 2152 uint64_t bootdma:1; 2153 uint64_t mii:1; 2154 uint64_t ipdppthr:1; 2155 uint64_t powiq:1; 2156 uint64_t twsi2:1; 2157 uint64_t reserved_57_58:2; 2158 uint64_t usb:1; 2159 uint64_t timer:4; 2160 uint64_t key_zero:1; 2161 uint64_t ipd_drp:1; 2162 uint64_t gmx_drp:2; 2163 uint64_t trace:1; 2164 uint64_t rml:1; 2165 uint64_t twsi:1; 2166 uint64_t reserved_44_44:1; 2167 uint64_t pci_msi:4; 2168 uint64_t pci_int:4; 2169 uint64_t uart:2; 2170 uint64_t mbox:2; 2171 uint64_t gpio:16; 2172 uint64_t workq:16; 2173 #else 2174 uint64_t workq:16; 2175 uint64_t gpio:16; 2176 uint64_t mbox:2; 2177 uint64_t uart:2; 2178 uint64_t pci_int:4; 2179 uint64_t pci_msi:4; 2180 uint64_t reserved_44_44:1; 2181 uint64_t twsi:1; 2182 uint64_t rml:1; 2183 uint64_t trace:1; 2184 uint64_t gmx_drp:2; 2185 uint64_t ipd_drp:1; 2186 uint64_t key_zero:1; 2187 uint64_t timer:4; 2188 uint64_t usb:1; 2189 uint64_t reserved_57_58:2; 2190 uint64_t twsi2:1; 2191 uint64_t powiq:1; 2192 uint64_t ipdppthr:1; 2193 uint64_t mii:1; 2194 uint64_t bootdma:1; 2195 #endif 2196 } cn56xx; 2197 struct cvmx_ciu_intx_en0_w1s_cn58xx { 2198 #ifdef __BIG_ENDIAN_BITFIELD 2199 uint64_t reserved_56_63:8; 2200 uint64_t timer:4; 2201 uint64_t key_zero:1; 2202 uint64_t ipd_drp:1; 2203 uint64_t gmx_drp:2; 2204 uint64_t trace:1; 2205 uint64_t rml:1; 2206 uint64_t twsi:1; 2207 uint64_t reserved_44_44:1; 2208 uint64_t pci_msi:4; 2209 uint64_t pci_int:4; 2210 uint64_t uart:2; 2211 uint64_t mbox:2; 2212 uint64_t gpio:16; 2213 uint64_t workq:16; 2214 #else 2215 uint64_t workq:16; 2216 uint64_t gpio:16; 2217 uint64_t mbox:2; 2218 uint64_t uart:2; 2219 uint64_t pci_int:4; 2220 uint64_t pci_msi:4; 2221 uint64_t reserved_44_44:1; 2222 uint64_t twsi:1; 2223 uint64_t rml:1; 2224 uint64_t trace:1; 2225 uint64_t gmx_drp:2; 2226 uint64_t ipd_drp:1; 2227 uint64_t key_zero:1; 2228 uint64_t timer:4; 2229 uint64_t reserved_56_63:8; 2230 #endif 2231 } cn58xx; 2232 struct cvmx_ciu_intx_en0_w1s_cn61xx { 2233 #ifdef __BIG_ENDIAN_BITFIELD 2234 uint64_t bootdma:1; 2235 uint64_t mii:1; 2236 uint64_t ipdppthr:1; 2237 uint64_t powiq:1; 2238 uint64_t twsi2:1; 2239 uint64_t mpi:1; 2240 uint64_t pcm:1; 2241 uint64_t usb:1; 2242 uint64_t timer:4; 2243 uint64_t reserved_51_51:1; 2244 uint64_t ipd_drp:1; 2245 uint64_t gmx_drp:2; 2246 uint64_t trace:1; 2247 uint64_t rml:1; 2248 uint64_t twsi:1; 2249 uint64_t reserved_44_44:1; 2250 uint64_t pci_msi:4; 2251 uint64_t pci_int:4; 2252 uint64_t uart:2; 2253 uint64_t mbox:2; 2254 uint64_t gpio:16; 2255 uint64_t workq:16; 2256 #else 2257 uint64_t workq:16; 2258 uint64_t gpio:16; 2259 uint64_t mbox:2; 2260 uint64_t uart:2; 2261 uint64_t pci_int:4; 2262 uint64_t pci_msi:4; 2263 uint64_t reserved_44_44:1; 2264 uint64_t twsi:1; 2265 uint64_t rml:1; 2266 uint64_t trace:1; 2267 uint64_t gmx_drp:2; 2268 uint64_t ipd_drp:1; 2269 uint64_t reserved_51_51:1; 2270 uint64_t timer:4; 2271 uint64_t usb:1; 2272 uint64_t pcm:1; 2273 uint64_t mpi:1; 2274 uint64_t twsi2:1; 2275 uint64_t powiq:1; 2276 uint64_t ipdppthr:1; 2277 uint64_t mii:1; 2278 uint64_t bootdma:1; 2279 #endif 2280 } cn61xx; 2281 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx; 2282 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1; 2283 struct cvmx_ciu_intx_en0_w1s_cn66xx { 2284 #ifdef __BIG_ENDIAN_BITFIELD 2285 uint64_t bootdma:1; 2286 uint64_t mii:1; 2287 uint64_t ipdppthr:1; 2288 uint64_t powiq:1; 2289 uint64_t twsi2:1; 2290 uint64_t mpi:1; 2291 uint64_t reserved_57_57:1; 2292 uint64_t usb:1; 2293 uint64_t timer:4; 2294 uint64_t reserved_51_51:1; 2295 uint64_t ipd_drp:1; 2296 uint64_t gmx_drp:2; 2297 uint64_t trace:1; 2298 uint64_t rml:1; 2299 uint64_t twsi:1; 2300 uint64_t reserved_44_44:1; 2301 uint64_t pci_msi:4; 2302 uint64_t pci_int:4; 2303 uint64_t uart:2; 2304 uint64_t mbox:2; 2305 uint64_t gpio:16; 2306 uint64_t workq:16; 2307 #else 2308 uint64_t workq:16; 2309 uint64_t gpio:16; 2310 uint64_t mbox:2; 2311 uint64_t uart:2; 2312 uint64_t pci_int:4; 2313 uint64_t pci_msi:4; 2314 uint64_t reserved_44_44:1; 2315 uint64_t twsi:1; 2316 uint64_t rml:1; 2317 uint64_t trace:1; 2318 uint64_t gmx_drp:2; 2319 uint64_t ipd_drp:1; 2320 uint64_t reserved_51_51:1; 2321 uint64_t timer:4; 2322 uint64_t usb:1; 2323 uint64_t reserved_57_57:1; 2324 uint64_t mpi:1; 2325 uint64_t twsi2:1; 2326 uint64_t powiq:1; 2327 uint64_t ipdppthr:1; 2328 uint64_t mii:1; 2329 uint64_t bootdma:1; 2330 #endif 2331 } cn66xx; 2332 struct cvmx_ciu_intx_en0_w1s_cnf71xx { 2333 #ifdef __BIG_ENDIAN_BITFIELD 2334 uint64_t bootdma:1; 2335 uint64_t reserved_62_62:1; 2336 uint64_t ipdppthr:1; 2337 uint64_t powiq:1; 2338 uint64_t twsi2:1; 2339 uint64_t mpi:1; 2340 uint64_t pcm:1; 2341 uint64_t usb:1; 2342 uint64_t timer:4; 2343 uint64_t reserved_51_51:1; 2344 uint64_t ipd_drp:1; 2345 uint64_t reserved_49_49:1; 2346 uint64_t gmx_drp:1; 2347 uint64_t trace:1; 2348 uint64_t rml:1; 2349 uint64_t twsi:1; 2350 uint64_t reserved_44_44:1; 2351 uint64_t pci_msi:4; 2352 uint64_t pci_int:4; 2353 uint64_t uart:2; 2354 uint64_t mbox:2; 2355 uint64_t gpio:16; 2356 uint64_t workq:16; 2357 #else 2358 uint64_t workq:16; 2359 uint64_t gpio:16; 2360 uint64_t mbox:2; 2361 uint64_t uart:2; 2362 uint64_t pci_int:4; 2363 uint64_t pci_msi:4; 2364 uint64_t reserved_44_44:1; 2365 uint64_t twsi:1; 2366 uint64_t rml:1; 2367 uint64_t trace:1; 2368 uint64_t gmx_drp:1; 2369 uint64_t reserved_49_49:1; 2370 uint64_t ipd_drp:1; 2371 uint64_t reserved_51_51:1; 2372 uint64_t timer:4; 2373 uint64_t usb:1; 2374 uint64_t pcm:1; 2375 uint64_t mpi:1; 2376 uint64_t twsi2:1; 2377 uint64_t powiq:1; 2378 uint64_t ipdppthr:1; 2379 uint64_t reserved_62_62:1; 2380 uint64_t bootdma:1; 2381 #endif 2382 } cnf71xx; 2383 }; 2384 2385 union cvmx_ciu_intx_en1 { 2386 uint64_t u64; 2387 struct cvmx_ciu_intx_en1_s { 2388 #ifdef __BIG_ENDIAN_BITFIELD 2389 uint64_t rst:1; 2390 uint64_t reserved_62_62:1; 2391 uint64_t srio3:1; 2392 uint64_t srio2:1; 2393 uint64_t reserved_57_59:3; 2394 uint64_t dfm:1; 2395 uint64_t reserved_53_55:3; 2396 uint64_t lmc0:1; 2397 uint64_t srio1:1; 2398 uint64_t srio0:1; 2399 uint64_t pem1:1; 2400 uint64_t pem0:1; 2401 uint64_t ptp:1; 2402 uint64_t agl:1; 2403 uint64_t reserved_41_45:5; 2404 uint64_t dpi_dma:1; 2405 uint64_t reserved_38_39:2; 2406 uint64_t agx1:1; 2407 uint64_t agx0:1; 2408 uint64_t dpi:1; 2409 uint64_t sli:1; 2410 uint64_t usb:1; 2411 uint64_t dfa:1; 2412 uint64_t key:1; 2413 uint64_t rad:1; 2414 uint64_t tim:1; 2415 uint64_t zip:1; 2416 uint64_t pko:1; 2417 uint64_t pip:1; 2418 uint64_t ipd:1; 2419 uint64_t l2c:1; 2420 uint64_t pow:1; 2421 uint64_t fpa:1; 2422 uint64_t iob:1; 2423 uint64_t mio:1; 2424 uint64_t nand:1; 2425 uint64_t mii1:1; 2426 uint64_t usb1:1; 2427 uint64_t uart2:1; 2428 uint64_t wdog:16; 2429 #else 2430 uint64_t wdog:16; 2431 uint64_t uart2:1; 2432 uint64_t usb1:1; 2433 uint64_t mii1:1; 2434 uint64_t nand:1; 2435 uint64_t mio:1; 2436 uint64_t iob:1; 2437 uint64_t fpa:1; 2438 uint64_t pow:1; 2439 uint64_t l2c:1; 2440 uint64_t ipd:1; 2441 uint64_t pip:1; 2442 uint64_t pko:1; 2443 uint64_t zip:1; 2444 uint64_t tim:1; 2445 uint64_t rad:1; 2446 uint64_t key:1; 2447 uint64_t dfa:1; 2448 uint64_t usb:1; 2449 uint64_t sli:1; 2450 uint64_t dpi:1; 2451 uint64_t agx0:1; 2452 uint64_t agx1:1; 2453 uint64_t reserved_38_39:2; 2454 uint64_t dpi_dma:1; 2455 uint64_t reserved_41_45:5; 2456 uint64_t agl:1; 2457 uint64_t ptp:1; 2458 uint64_t pem0:1; 2459 uint64_t pem1:1; 2460 uint64_t srio0:1; 2461 uint64_t srio1:1; 2462 uint64_t lmc0:1; 2463 uint64_t reserved_53_55:3; 2464 uint64_t dfm:1; 2465 uint64_t reserved_57_59:3; 2466 uint64_t srio2:1; 2467 uint64_t srio3:1; 2468 uint64_t reserved_62_62:1; 2469 uint64_t rst:1; 2470 #endif 2471 } s; 2472 struct cvmx_ciu_intx_en1_cn30xx { 2473 #ifdef __BIG_ENDIAN_BITFIELD 2474 uint64_t reserved_1_63:63; 2475 uint64_t wdog:1; 2476 #else 2477 uint64_t wdog:1; 2478 uint64_t reserved_1_63:63; 2479 #endif 2480 } cn30xx; 2481 struct cvmx_ciu_intx_en1_cn31xx { 2482 #ifdef __BIG_ENDIAN_BITFIELD 2483 uint64_t reserved_2_63:62; 2484 uint64_t wdog:2; 2485 #else 2486 uint64_t wdog:2; 2487 uint64_t reserved_2_63:62; 2488 #endif 2489 } cn31xx; 2490 struct cvmx_ciu_intx_en1_cn38xx { 2491 #ifdef __BIG_ENDIAN_BITFIELD 2492 uint64_t reserved_16_63:48; 2493 uint64_t wdog:16; 2494 #else 2495 uint64_t wdog:16; 2496 uint64_t reserved_16_63:48; 2497 #endif 2498 } cn38xx; 2499 struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; 2500 struct cvmx_ciu_intx_en1_cn31xx cn50xx; 2501 struct cvmx_ciu_intx_en1_cn52xx { 2502 #ifdef __BIG_ENDIAN_BITFIELD 2503 uint64_t reserved_20_63:44; 2504 uint64_t nand:1; 2505 uint64_t mii1:1; 2506 uint64_t usb1:1; 2507 uint64_t uart2:1; 2508 uint64_t reserved_4_15:12; 2509 uint64_t wdog:4; 2510 #else 2511 uint64_t wdog:4; 2512 uint64_t reserved_4_15:12; 2513 uint64_t uart2:1; 2514 uint64_t usb1:1; 2515 uint64_t mii1:1; 2516 uint64_t nand:1; 2517 uint64_t reserved_20_63:44; 2518 #endif 2519 } cn52xx; 2520 struct cvmx_ciu_intx_en1_cn52xxp1 { 2521 #ifdef __BIG_ENDIAN_BITFIELD 2522 uint64_t reserved_19_63:45; 2523 uint64_t mii1:1; 2524 uint64_t usb1:1; 2525 uint64_t uart2:1; 2526 uint64_t reserved_4_15:12; 2527 uint64_t wdog:4; 2528 #else 2529 uint64_t wdog:4; 2530 uint64_t reserved_4_15:12; 2531 uint64_t uart2:1; 2532 uint64_t usb1:1; 2533 uint64_t mii1:1; 2534 uint64_t reserved_19_63:45; 2535 #endif 2536 } cn52xxp1; 2537 struct cvmx_ciu_intx_en1_cn56xx { 2538 #ifdef __BIG_ENDIAN_BITFIELD 2539 uint64_t reserved_12_63:52; 2540 uint64_t wdog:12; 2541 #else 2542 uint64_t wdog:12; 2543 uint64_t reserved_12_63:52; 2544 #endif 2545 } cn56xx; 2546 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; 2547 struct cvmx_ciu_intx_en1_cn38xx cn58xx; 2548 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; 2549 struct cvmx_ciu_intx_en1_cn61xx { 2550 #ifdef __BIG_ENDIAN_BITFIELD 2551 uint64_t rst:1; 2552 uint64_t reserved_53_62:10; 2553 uint64_t lmc0:1; 2554 uint64_t reserved_50_51:2; 2555 uint64_t pem1:1; 2556 uint64_t pem0:1; 2557 uint64_t ptp:1; 2558 uint64_t agl:1; 2559 uint64_t reserved_41_45:5; 2560 uint64_t dpi_dma:1; 2561 uint64_t reserved_38_39:2; 2562 uint64_t agx1:1; 2563 uint64_t agx0:1; 2564 uint64_t dpi:1; 2565 uint64_t sli:1; 2566 uint64_t usb:1; 2567 uint64_t dfa:1; 2568 uint64_t key:1; 2569 uint64_t rad:1; 2570 uint64_t tim:1; 2571 uint64_t zip:1; 2572 uint64_t pko:1; 2573 uint64_t pip:1; 2574 uint64_t ipd:1; 2575 uint64_t l2c:1; 2576 uint64_t pow:1; 2577 uint64_t fpa:1; 2578 uint64_t iob:1; 2579 uint64_t mio:1; 2580 uint64_t nand:1; 2581 uint64_t mii1:1; 2582 uint64_t reserved_4_17:14; 2583 uint64_t wdog:4; 2584 #else 2585 uint64_t wdog:4; 2586 uint64_t reserved_4_17:14; 2587 uint64_t mii1:1; 2588 uint64_t nand:1; 2589 uint64_t mio:1; 2590 uint64_t iob:1; 2591 uint64_t fpa:1; 2592 uint64_t pow:1; 2593 uint64_t l2c:1; 2594 uint64_t ipd:1; 2595 uint64_t pip:1; 2596 uint64_t pko:1; 2597 uint64_t zip:1; 2598 uint64_t tim:1; 2599 uint64_t rad:1; 2600 uint64_t key:1; 2601 uint64_t dfa:1; 2602 uint64_t usb:1; 2603 uint64_t sli:1; 2604 uint64_t dpi:1; 2605 uint64_t agx0:1; 2606 uint64_t agx1:1; 2607 uint64_t reserved_38_39:2; 2608 uint64_t dpi_dma:1; 2609 uint64_t reserved_41_45:5; 2610 uint64_t agl:1; 2611 uint64_t ptp:1; 2612 uint64_t pem0:1; 2613 uint64_t pem1:1; 2614 uint64_t reserved_50_51:2; 2615 uint64_t lmc0:1; 2616 uint64_t reserved_53_62:10; 2617 uint64_t rst:1; 2618 #endif 2619 } cn61xx; 2620 struct cvmx_ciu_intx_en1_cn63xx { 2621 #ifdef __BIG_ENDIAN_BITFIELD 2622 uint64_t rst:1; 2623 uint64_t reserved_57_62:6; 2624 uint64_t dfm:1; 2625 uint64_t reserved_53_55:3; 2626 uint64_t lmc0:1; 2627 uint64_t srio1:1; 2628 uint64_t srio0:1; 2629 uint64_t pem1:1; 2630 uint64_t pem0:1; 2631 uint64_t ptp:1; 2632 uint64_t agl:1; 2633 uint64_t reserved_37_45:9; 2634 uint64_t agx0:1; 2635 uint64_t dpi:1; 2636 uint64_t sli:1; 2637 uint64_t usb:1; 2638 uint64_t dfa:1; 2639 uint64_t key:1; 2640 uint64_t rad:1; 2641 uint64_t tim:1; 2642 uint64_t zip:1; 2643 uint64_t pko:1; 2644 uint64_t pip:1; 2645 uint64_t ipd:1; 2646 uint64_t l2c:1; 2647 uint64_t pow:1; 2648 uint64_t fpa:1; 2649 uint64_t iob:1; 2650 uint64_t mio:1; 2651 uint64_t nand:1; 2652 uint64_t mii1:1; 2653 uint64_t reserved_6_17:12; 2654 uint64_t wdog:6; 2655 #else 2656 uint64_t wdog:6; 2657 uint64_t reserved_6_17:12; 2658 uint64_t mii1:1; 2659 uint64_t nand:1; 2660 uint64_t mio:1; 2661 uint64_t iob:1; 2662 uint64_t fpa:1; 2663 uint64_t pow:1; 2664 uint64_t l2c:1; 2665 uint64_t ipd:1; 2666 uint64_t pip:1; 2667 uint64_t pko:1; 2668 uint64_t zip:1; 2669 uint64_t tim:1; 2670 uint64_t rad:1; 2671 uint64_t key:1; 2672 uint64_t dfa:1; 2673 uint64_t usb:1; 2674 uint64_t sli:1; 2675 uint64_t dpi:1; 2676 uint64_t agx0:1; 2677 uint64_t reserved_37_45:9; 2678 uint64_t agl:1; 2679 uint64_t ptp:1; 2680 uint64_t pem0:1; 2681 uint64_t pem1:1; 2682 uint64_t srio0:1; 2683 uint64_t srio1:1; 2684 uint64_t lmc0:1; 2685 uint64_t reserved_53_55:3; 2686 uint64_t dfm:1; 2687 uint64_t reserved_57_62:6; 2688 uint64_t rst:1; 2689 #endif 2690 } cn63xx; 2691 struct cvmx_ciu_intx_en1_cn63xx cn63xxp1; 2692 struct cvmx_ciu_intx_en1_cn66xx { 2693 #ifdef __BIG_ENDIAN_BITFIELD 2694 uint64_t rst:1; 2695 uint64_t reserved_62_62:1; 2696 uint64_t srio3:1; 2697 uint64_t srio2:1; 2698 uint64_t reserved_57_59:3; 2699 uint64_t dfm:1; 2700 uint64_t reserved_53_55:3; 2701 uint64_t lmc0:1; 2702 uint64_t reserved_51_51:1; 2703 uint64_t srio0:1; 2704 uint64_t pem1:1; 2705 uint64_t pem0:1; 2706 uint64_t ptp:1; 2707 uint64_t agl:1; 2708 uint64_t reserved_38_45:8; 2709 uint64_t agx1:1; 2710 uint64_t agx0:1; 2711 uint64_t dpi:1; 2712 uint64_t sli:1; 2713 uint64_t usb:1; 2714 uint64_t dfa:1; 2715 uint64_t key:1; 2716 uint64_t rad:1; 2717 uint64_t tim:1; 2718 uint64_t zip:1; 2719 uint64_t pko:1; 2720 uint64_t pip:1; 2721 uint64_t ipd:1; 2722 uint64_t l2c:1; 2723 uint64_t pow:1; 2724 uint64_t fpa:1; 2725 uint64_t iob:1; 2726 uint64_t mio:1; 2727 uint64_t nand:1; 2728 uint64_t mii1:1; 2729 uint64_t reserved_10_17:8; 2730 uint64_t wdog:10; 2731 #else 2732 uint64_t wdog:10; 2733 uint64_t reserved_10_17:8; 2734 uint64_t mii1:1; 2735 uint64_t nand:1; 2736 uint64_t mio:1; 2737 uint64_t iob:1; 2738 uint64_t fpa:1; 2739 uint64_t pow:1; 2740 uint64_t l2c:1; 2741 uint64_t ipd:1; 2742 uint64_t pip:1; 2743 uint64_t pko:1; 2744 uint64_t zip:1; 2745 uint64_t tim:1; 2746 uint64_t rad:1; 2747 uint64_t key:1; 2748 uint64_t dfa:1; 2749 uint64_t usb:1; 2750 uint64_t sli:1; 2751 uint64_t dpi:1; 2752 uint64_t agx0:1; 2753 uint64_t agx1:1; 2754 uint64_t reserved_38_45:8; 2755 uint64_t agl:1; 2756 uint64_t ptp:1; 2757 uint64_t pem0:1; 2758 uint64_t pem1:1; 2759 uint64_t srio0:1; 2760 uint64_t reserved_51_51:1; 2761 uint64_t lmc0:1; 2762 uint64_t reserved_53_55:3; 2763 uint64_t dfm:1; 2764 uint64_t reserved_57_59:3; 2765 uint64_t srio2:1; 2766 uint64_t srio3:1; 2767 uint64_t reserved_62_62:1; 2768 uint64_t rst:1; 2769 #endif 2770 } cn66xx; 2771 struct cvmx_ciu_intx_en1_cnf71xx { 2772 #ifdef __BIG_ENDIAN_BITFIELD 2773 uint64_t rst:1; 2774 uint64_t reserved_53_62:10; 2775 uint64_t lmc0:1; 2776 uint64_t reserved_50_51:2; 2777 uint64_t pem1:1; 2778 uint64_t pem0:1; 2779 uint64_t ptp:1; 2780 uint64_t reserved_41_46:6; 2781 uint64_t dpi_dma:1; 2782 uint64_t reserved_37_39:3; 2783 uint64_t agx0:1; 2784 uint64_t dpi:1; 2785 uint64_t sli:1; 2786 uint64_t usb:1; 2787 uint64_t reserved_32_32:1; 2788 uint64_t key:1; 2789 uint64_t rad:1; 2790 uint64_t tim:1; 2791 uint64_t reserved_28_28:1; 2792 uint64_t pko:1; 2793 uint64_t pip:1; 2794 uint64_t ipd:1; 2795 uint64_t l2c:1; 2796 uint64_t pow:1; 2797 uint64_t fpa:1; 2798 uint64_t iob:1; 2799 uint64_t mio:1; 2800 uint64_t nand:1; 2801 uint64_t reserved_4_18:15; 2802 uint64_t wdog:4; 2803 #else 2804 uint64_t wdog:4; 2805 uint64_t reserved_4_18:15; 2806 uint64_t nand:1; 2807 uint64_t mio:1; 2808 uint64_t iob:1; 2809 uint64_t fpa:1; 2810 uint64_t pow:1; 2811 uint64_t l2c:1; 2812 uint64_t ipd:1; 2813 uint64_t pip:1; 2814 uint64_t pko:1; 2815 uint64_t reserved_28_28:1; 2816 uint64_t tim:1; 2817 uint64_t rad:1; 2818 uint64_t key:1; 2819 uint64_t reserved_32_32:1; 2820 uint64_t usb:1; 2821 uint64_t sli:1; 2822 uint64_t dpi:1; 2823 uint64_t agx0:1; 2824 uint64_t reserved_37_39:3; 2825 uint64_t dpi_dma:1; 2826 uint64_t reserved_41_46:6; 2827 uint64_t ptp:1; 2828 uint64_t pem0:1; 2829 uint64_t pem1:1; 2830 uint64_t reserved_50_51:2; 2831 uint64_t lmc0:1; 2832 uint64_t reserved_53_62:10; 2833 uint64_t rst:1; 2834 #endif 2835 } cnf71xx; 2836 }; 2837 2838 union cvmx_ciu_intx_en1_w1c { 2839 uint64_t u64; 2840 struct cvmx_ciu_intx_en1_w1c_s { 2841 #ifdef __BIG_ENDIAN_BITFIELD 2842 uint64_t rst:1; 2843 uint64_t reserved_62_62:1; 2844 uint64_t srio3:1; 2845 uint64_t srio2:1; 2846 uint64_t reserved_57_59:3; 2847 uint64_t dfm:1; 2848 uint64_t reserved_53_55:3; 2849 uint64_t lmc0:1; 2850 uint64_t srio1:1; 2851 uint64_t srio0:1; 2852 uint64_t pem1:1; 2853 uint64_t pem0:1; 2854 uint64_t ptp:1; 2855 uint64_t agl:1; 2856 uint64_t reserved_41_45:5; 2857 uint64_t dpi_dma:1; 2858 uint64_t reserved_38_39:2; 2859 uint64_t agx1:1; 2860 uint64_t agx0:1; 2861 uint64_t dpi:1; 2862 uint64_t sli:1; 2863 uint64_t usb:1; 2864 uint64_t dfa:1; 2865 uint64_t key:1; 2866 uint64_t rad:1; 2867 uint64_t tim:1; 2868 uint64_t zip:1; 2869 uint64_t pko:1; 2870 uint64_t pip:1; 2871 uint64_t ipd:1; 2872 uint64_t l2c:1; 2873 uint64_t pow:1; 2874 uint64_t fpa:1; 2875 uint64_t iob:1; 2876 uint64_t mio:1; 2877 uint64_t nand:1; 2878 uint64_t mii1:1; 2879 uint64_t usb1:1; 2880 uint64_t uart2:1; 2881 uint64_t wdog:16; 2882 #else 2883 uint64_t wdog:16; 2884 uint64_t uart2:1; 2885 uint64_t usb1:1; 2886 uint64_t mii1:1; 2887 uint64_t nand:1; 2888 uint64_t mio:1; 2889 uint64_t iob:1; 2890 uint64_t fpa:1; 2891 uint64_t pow:1; 2892 uint64_t l2c:1; 2893 uint64_t ipd:1; 2894 uint64_t pip:1; 2895 uint64_t pko:1; 2896 uint64_t zip:1; 2897 uint64_t tim:1; 2898 uint64_t rad:1; 2899 uint64_t key:1; 2900 uint64_t dfa:1; 2901 uint64_t usb:1; 2902 uint64_t sli:1; 2903 uint64_t dpi:1; 2904 uint64_t agx0:1; 2905 uint64_t agx1:1; 2906 uint64_t reserved_38_39:2; 2907 uint64_t dpi_dma:1; 2908 uint64_t reserved_41_45:5; 2909 uint64_t agl:1; 2910 uint64_t ptp:1; 2911 uint64_t pem0:1; 2912 uint64_t pem1:1; 2913 uint64_t srio0:1; 2914 uint64_t srio1:1; 2915 uint64_t lmc0:1; 2916 uint64_t reserved_53_55:3; 2917 uint64_t dfm:1; 2918 uint64_t reserved_57_59:3; 2919 uint64_t srio2:1; 2920 uint64_t srio3:1; 2921 uint64_t reserved_62_62:1; 2922 uint64_t rst:1; 2923 #endif 2924 } s; 2925 struct cvmx_ciu_intx_en1_w1c_cn52xx { 2926 #ifdef __BIG_ENDIAN_BITFIELD 2927 uint64_t reserved_20_63:44; 2928 uint64_t nand:1; 2929 uint64_t mii1:1; 2930 uint64_t usb1:1; 2931 uint64_t uart2:1; 2932 uint64_t reserved_4_15:12; 2933 uint64_t wdog:4; 2934 #else 2935 uint64_t wdog:4; 2936 uint64_t reserved_4_15:12; 2937 uint64_t uart2:1; 2938 uint64_t usb1:1; 2939 uint64_t mii1:1; 2940 uint64_t nand:1; 2941 uint64_t reserved_20_63:44; 2942 #endif 2943 } cn52xx; 2944 struct cvmx_ciu_intx_en1_w1c_cn56xx { 2945 #ifdef __BIG_ENDIAN_BITFIELD 2946 uint64_t reserved_12_63:52; 2947 uint64_t wdog:12; 2948 #else 2949 uint64_t wdog:12; 2950 uint64_t reserved_12_63:52; 2951 #endif 2952 } cn56xx; 2953 struct cvmx_ciu_intx_en1_w1c_cn58xx { 2954 #ifdef __BIG_ENDIAN_BITFIELD 2955 uint64_t reserved_16_63:48; 2956 uint64_t wdog:16; 2957 #else 2958 uint64_t wdog:16; 2959 uint64_t reserved_16_63:48; 2960 #endif 2961 } cn58xx; 2962 struct cvmx_ciu_intx_en1_w1c_cn61xx { 2963 #ifdef __BIG_ENDIAN_BITFIELD 2964 uint64_t rst:1; 2965 uint64_t reserved_53_62:10; 2966 uint64_t lmc0:1; 2967 uint64_t reserved_50_51:2; 2968 uint64_t pem1:1; 2969 uint64_t pem0:1; 2970 uint64_t ptp:1; 2971 uint64_t agl:1; 2972 uint64_t reserved_41_45:5; 2973 uint64_t dpi_dma:1; 2974 uint64_t reserved_38_39:2; 2975 uint64_t agx1:1; 2976 uint64_t agx0:1; 2977 uint64_t dpi:1; 2978 uint64_t sli:1; 2979 uint64_t usb:1; 2980 uint64_t dfa:1; 2981 uint64_t key:1; 2982 uint64_t rad:1; 2983 uint64_t tim:1; 2984 uint64_t zip:1; 2985 uint64_t pko:1; 2986 uint64_t pip:1; 2987 uint64_t ipd:1; 2988 uint64_t l2c:1; 2989 uint64_t pow:1; 2990 uint64_t fpa:1; 2991 uint64_t iob:1; 2992 uint64_t mio:1; 2993 uint64_t nand:1; 2994 uint64_t mii1:1; 2995 uint64_t reserved_4_17:14; 2996 uint64_t wdog:4; 2997 #else 2998 uint64_t wdog:4; 2999 uint64_t reserved_4_17:14; 3000 uint64_t mii1:1; 3001 uint64_t nand:1; 3002 uint64_t mio:1; 3003 uint64_t iob:1; 3004 uint64_t fpa:1; 3005 uint64_t pow:1; 3006 uint64_t l2c:1; 3007 uint64_t ipd:1; 3008 uint64_t pip:1; 3009 uint64_t pko:1; 3010 uint64_t zip:1; 3011 uint64_t tim:1; 3012 uint64_t rad:1; 3013 uint64_t key:1; 3014 uint64_t dfa:1; 3015 uint64_t usb:1; 3016 uint64_t sli:1; 3017 uint64_t dpi:1; 3018 uint64_t agx0:1; 3019 uint64_t agx1:1; 3020 uint64_t reserved_38_39:2; 3021 uint64_t dpi_dma:1; 3022 uint64_t reserved_41_45:5; 3023 uint64_t agl:1; 3024 uint64_t ptp:1; 3025 uint64_t pem0:1; 3026 uint64_t pem1:1; 3027 uint64_t reserved_50_51:2; 3028 uint64_t lmc0:1; 3029 uint64_t reserved_53_62:10; 3030 uint64_t rst:1; 3031 #endif 3032 } cn61xx; 3033 struct cvmx_ciu_intx_en1_w1c_cn63xx { 3034 #ifdef __BIG_ENDIAN_BITFIELD 3035 uint64_t rst:1; 3036 uint64_t reserved_57_62:6; 3037 uint64_t dfm:1; 3038 uint64_t reserved_53_55:3; 3039 uint64_t lmc0:1; 3040 uint64_t srio1:1; 3041 uint64_t srio0:1; 3042 uint64_t pem1:1; 3043 uint64_t pem0:1; 3044 uint64_t ptp:1; 3045 uint64_t agl:1; 3046 uint64_t reserved_37_45:9; 3047 uint64_t agx0:1; 3048 uint64_t dpi:1; 3049 uint64_t sli:1; 3050 uint64_t usb:1; 3051 uint64_t dfa:1; 3052 uint64_t key:1; 3053 uint64_t rad:1; 3054 uint64_t tim:1; 3055 uint64_t zip:1; 3056 uint64_t pko:1; 3057 uint64_t pip:1; 3058 uint64_t ipd:1; 3059 uint64_t l2c:1; 3060 uint64_t pow:1; 3061 uint64_t fpa:1; 3062 uint64_t iob:1; 3063 uint64_t mio:1; 3064 uint64_t nand:1; 3065 uint64_t mii1:1; 3066 uint64_t reserved_6_17:12; 3067 uint64_t wdog:6; 3068 #else 3069 uint64_t wdog:6; 3070 uint64_t reserved_6_17:12; 3071 uint64_t mii1:1; 3072 uint64_t nand:1; 3073 uint64_t mio:1; 3074 uint64_t iob:1; 3075 uint64_t fpa:1; 3076 uint64_t pow:1; 3077 uint64_t l2c:1; 3078 uint64_t ipd:1; 3079 uint64_t pip:1; 3080 uint64_t pko:1; 3081 uint64_t zip:1; 3082 uint64_t tim:1; 3083 uint64_t rad:1; 3084 uint64_t key:1; 3085 uint64_t dfa:1; 3086 uint64_t usb:1; 3087 uint64_t sli:1; 3088 uint64_t dpi:1; 3089 uint64_t agx0:1; 3090 uint64_t reserved_37_45:9; 3091 uint64_t agl:1; 3092 uint64_t ptp:1; 3093 uint64_t pem0:1; 3094 uint64_t pem1:1; 3095 uint64_t srio0:1; 3096 uint64_t srio1:1; 3097 uint64_t lmc0:1; 3098 uint64_t reserved_53_55:3; 3099 uint64_t dfm:1; 3100 uint64_t reserved_57_62:6; 3101 uint64_t rst:1; 3102 #endif 3103 } cn63xx; 3104 struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1; 3105 struct cvmx_ciu_intx_en1_w1c_cn66xx { 3106 #ifdef __BIG_ENDIAN_BITFIELD 3107 uint64_t rst:1; 3108 uint64_t reserved_62_62:1; 3109 uint64_t srio3:1; 3110 uint64_t srio2:1; 3111 uint64_t reserved_57_59:3; 3112 uint64_t dfm:1; 3113 uint64_t reserved_53_55:3; 3114 uint64_t lmc0:1; 3115 uint64_t reserved_51_51:1; 3116 uint64_t srio0:1; 3117 uint64_t pem1:1; 3118 uint64_t pem0:1; 3119 uint64_t ptp:1; 3120 uint64_t agl:1; 3121 uint64_t reserved_38_45:8; 3122 uint64_t agx1:1; 3123 uint64_t agx0:1; 3124 uint64_t dpi:1; 3125 uint64_t sli:1; 3126 uint64_t usb:1; 3127 uint64_t dfa:1; 3128 uint64_t key:1; 3129 uint64_t rad:1; 3130 uint64_t tim:1; 3131 uint64_t zip:1; 3132 uint64_t pko:1; 3133 uint64_t pip:1; 3134 uint64_t ipd:1; 3135 uint64_t l2c:1; 3136 uint64_t pow:1; 3137 uint64_t fpa:1; 3138 uint64_t iob:1; 3139 uint64_t mio:1; 3140 uint64_t nand:1; 3141 uint64_t mii1:1; 3142 uint64_t reserved_10_17:8; 3143 uint64_t wdog:10; 3144 #else 3145 uint64_t wdog:10; 3146 uint64_t reserved_10_17:8; 3147 uint64_t mii1:1; 3148 uint64_t nand:1; 3149 uint64_t mio:1; 3150 uint64_t iob:1; 3151 uint64_t fpa:1; 3152 uint64_t pow:1; 3153 uint64_t l2c:1; 3154 uint64_t ipd:1; 3155 uint64_t pip:1; 3156 uint64_t pko:1; 3157 uint64_t zip:1; 3158 uint64_t tim:1; 3159 uint64_t rad:1; 3160 uint64_t key:1; 3161 uint64_t dfa:1; 3162 uint64_t usb:1; 3163 uint64_t sli:1; 3164 uint64_t dpi:1; 3165 uint64_t agx0:1; 3166 uint64_t agx1:1; 3167 uint64_t reserved_38_45:8; 3168 uint64_t agl:1; 3169 uint64_t ptp:1; 3170 uint64_t pem0:1; 3171 uint64_t pem1:1; 3172 uint64_t srio0:1; 3173 uint64_t reserved_51_51:1; 3174 uint64_t lmc0:1; 3175 uint64_t reserved_53_55:3; 3176 uint64_t dfm:1; 3177 uint64_t reserved_57_59:3; 3178 uint64_t srio2:1; 3179 uint64_t srio3:1; 3180 uint64_t reserved_62_62:1; 3181 uint64_t rst:1; 3182 #endif 3183 } cn66xx; 3184 struct cvmx_ciu_intx_en1_w1c_cnf71xx { 3185 #ifdef __BIG_ENDIAN_BITFIELD 3186 uint64_t rst:1; 3187 uint64_t reserved_53_62:10; 3188 uint64_t lmc0:1; 3189 uint64_t reserved_50_51:2; 3190 uint64_t pem1:1; 3191 uint64_t pem0:1; 3192 uint64_t ptp:1; 3193 uint64_t reserved_41_46:6; 3194 uint64_t dpi_dma:1; 3195 uint64_t reserved_37_39:3; 3196 uint64_t agx0:1; 3197 uint64_t dpi:1; 3198 uint64_t sli:1; 3199 uint64_t usb:1; 3200 uint64_t reserved_32_32:1; 3201 uint64_t key:1; 3202 uint64_t rad:1; 3203 uint64_t tim:1; 3204 uint64_t reserved_28_28:1; 3205 uint64_t pko:1; 3206 uint64_t pip:1; 3207 uint64_t ipd:1; 3208 uint64_t l2c:1; 3209 uint64_t pow:1; 3210 uint64_t fpa:1; 3211 uint64_t iob:1; 3212 uint64_t mio:1; 3213 uint64_t nand:1; 3214 uint64_t reserved_4_18:15; 3215 uint64_t wdog:4; 3216 #else 3217 uint64_t wdog:4; 3218 uint64_t reserved_4_18:15; 3219 uint64_t nand:1; 3220 uint64_t mio:1; 3221 uint64_t iob:1; 3222 uint64_t fpa:1; 3223 uint64_t pow:1; 3224 uint64_t l2c:1; 3225 uint64_t ipd:1; 3226 uint64_t pip:1; 3227 uint64_t pko:1; 3228 uint64_t reserved_28_28:1; 3229 uint64_t tim:1; 3230 uint64_t rad:1; 3231 uint64_t key:1; 3232 uint64_t reserved_32_32:1; 3233 uint64_t usb:1; 3234 uint64_t sli:1; 3235 uint64_t dpi:1; 3236 uint64_t agx0:1; 3237 uint64_t reserved_37_39:3; 3238 uint64_t dpi_dma:1; 3239 uint64_t reserved_41_46:6; 3240 uint64_t ptp:1; 3241 uint64_t pem0:1; 3242 uint64_t pem1:1; 3243 uint64_t reserved_50_51:2; 3244 uint64_t lmc0:1; 3245 uint64_t reserved_53_62:10; 3246 uint64_t rst:1; 3247 #endif 3248 } cnf71xx; 3249 }; 3250 3251 union cvmx_ciu_intx_en1_w1s { 3252 uint64_t u64; 3253 struct cvmx_ciu_intx_en1_w1s_s { 3254 #ifdef __BIG_ENDIAN_BITFIELD 3255 uint64_t rst:1; 3256 uint64_t reserved_62_62:1; 3257 uint64_t srio3:1; 3258 uint64_t srio2:1; 3259 uint64_t reserved_57_59:3; 3260 uint64_t dfm:1; 3261 uint64_t reserved_53_55:3; 3262 uint64_t lmc0:1; 3263 uint64_t srio1:1; 3264 uint64_t srio0:1; 3265 uint64_t pem1:1; 3266 uint64_t pem0:1; 3267 uint64_t ptp:1; 3268 uint64_t agl:1; 3269 uint64_t reserved_41_45:5; 3270 uint64_t dpi_dma:1; 3271 uint64_t reserved_38_39:2; 3272 uint64_t agx1:1; 3273 uint64_t agx0:1; 3274 uint64_t dpi:1; 3275 uint64_t sli:1; 3276 uint64_t usb:1; 3277 uint64_t dfa:1; 3278 uint64_t key:1; 3279 uint64_t rad:1; 3280 uint64_t tim:1; 3281 uint64_t zip:1; 3282 uint64_t pko:1; 3283 uint64_t pip:1; 3284 uint64_t ipd:1; 3285 uint64_t l2c:1; 3286 uint64_t pow:1; 3287 uint64_t fpa:1; 3288 uint64_t iob:1; 3289 uint64_t mio:1; 3290 uint64_t nand:1; 3291 uint64_t mii1:1; 3292 uint64_t usb1:1; 3293 uint64_t uart2:1; 3294 uint64_t wdog:16; 3295 #else 3296 uint64_t wdog:16; 3297 uint64_t uart2:1; 3298 uint64_t usb1:1; 3299 uint64_t mii1:1; 3300 uint64_t nand:1; 3301 uint64_t mio:1; 3302 uint64_t iob:1; 3303 uint64_t fpa:1; 3304 uint64_t pow:1; 3305 uint64_t l2c:1; 3306 uint64_t ipd:1; 3307 uint64_t pip:1; 3308 uint64_t pko:1; 3309 uint64_t zip:1; 3310 uint64_t tim:1; 3311 uint64_t rad:1; 3312 uint64_t key:1; 3313 uint64_t dfa:1; 3314 uint64_t usb:1; 3315 uint64_t sli:1; 3316 uint64_t dpi:1; 3317 uint64_t agx0:1; 3318 uint64_t agx1:1; 3319 uint64_t reserved_38_39:2; 3320 uint64_t dpi_dma:1; 3321 uint64_t reserved_41_45:5; 3322 uint64_t agl:1; 3323 uint64_t ptp:1; 3324 uint64_t pem0:1; 3325 uint64_t pem1:1; 3326 uint64_t srio0:1; 3327 uint64_t srio1:1; 3328 uint64_t lmc0:1; 3329 uint64_t reserved_53_55:3; 3330 uint64_t dfm:1; 3331 uint64_t reserved_57_59:3; 3332 uint64_t srio2:1; 3333 uint64_t srio3:1; 3334 uint64_t reserved_62_62:1; 3335 uint64_t rst:1; 3336 #endif 3337 } s; 3338 struct cvmx_ciu_intx_en1_w1s_cn52xx { 3339 #ifdef __BIG_ENDIAN_BITFIELD 3340 uint64_t reserved_20_63:44; 3341 uint64_t nand:1; 3342 uint64_t mii1:1; 3343 uint64_t usb1:1; 3344 uint64_t uart2:1; 3345 uint64_t reserved_4_15:12; 3346 uint64_t wdog:4; 3347 #else 3348 uint64_t wdog:4; 3349 uint64_t reserved_4_15:12; 3350 uint64_t uart2:1; 3351 uint64_t usb1:1; 3352 uint64_t mii1:1; 3353 uint64_t nand:1; 3354 uint64_t reserved_20_63:44; 3355 #endif 3356 } cn52xx; 3357 struct cvmx_ciu_intx_en1_w1s_cn56xx { 3358 #ifdef __BIG_ENDIAN_BITFIELD 3359 uint64_t reserved_12_63:52; 3360 uint64_t wdog:12; 3361 #else 3362 uint64_t wdog:12; 3363 uint64_t reserved_12_63:52; 3364 #endif 3365 } cn56xx; 3366 struct cvmx_ciu_intx_en1_w1s_cn58xx { 3367 #ifdef __BIG_ENDIAN_BITFIELD 3368 uint64_t reserved_16_63:48; 3369 uint64_t wdog:16; 3370 #else 3371 uint64_t wdog:16; 3372 uint64_t reserved_16_63:48; 3373 #endif 3374 } cn58xx; 3375 struct cvmx_ciu_intx_en1_w1s_cn61xx { 3376 #ifdef __BIG_ENDIAN_BITFIELD 3377 uint64_t rst:1; 3378 uint64_t reserved_53_62:10; 3379 uint64_t lmc0:1; 3380 uint64_t reserved_50_51:2; 3381 uint64_t pem1:1; 3382 uint64_t pem0:1; 3383 uint64_t ptp:1; 3384 uint64_t agl:1; 3385 uint64_t reserved_41_45:5; 3386 uint64_t dpi_dma:1; 3387 uint64_t reserved_38_39:2; 3388 uint64_t agx1:1; 3389 uint64_t agx0:1; 3390 uint64_t dpi:1; 3391 uint64_t sli:1; 3392 uint64_t usb:1; 3393 uint64_t dfa:1; 3394 uint64_t key:1; 3395 uint64_t rad:1; 3396 uint64_t tim:1; 3397 uint64_t zip:1; 3398 uint64_t pko:1; 3399 uint64_t pip:1; 3400 uint64_t ipd:1; 3401 uint64_t l2c:1; 3402 uint64_t pow:1; 3403 uint64_t fpa:1; 3404 uint64_t iob:1; 3405 uint64_t mio:1; 3406 uint64_t nand:1; 3407 uint64_t mii1:1; 3408 uint64_t reserved_4_17:14; 3409 uint64_t wdog:4; 3410 #else 3411 uint64_t wdog:4; 3412 uint64_t reserved_4_17:14; 3413 uint64_t mii1:1; 3414 uint64_t nand:1; 3415 uint64_t mio:1; 3416 uint64_t iob:1; 3417 uint64_t fpa:1; 3418 uint64_t pow:1; 3419 uint64_t l2c:1; 3420 uint64_t ipd:1; 3421 uint64_t pip:1; 3422 uint64_t pko:1; 3423 uint64_t zip:1; 3424 uint64_t tim:1; 3425 uint64_t rad:1; 3426 uint64_t key:1; 3427 uint64_t dfa:1; 3428 uint64_t usb:1; 3429 uint64_t sli:1; 3430 uint64_t dpi:1; 3431 uint64_t agx0:1; 3432 uint64_t agx1:1; 3433 uint64_t reserved_38_39:2; 3434 uint64_t dpi_dma:1; 3435 uint64_t reserved_41_45:5; 3436 uint64_t agl:1; 3437 uint64_t ptp:1; 3438 uint64_t pem0:1; 3439 uint64_t pem1:1; 3440 uint64_t reserved_50_51:2; 3441 uint64_t lmc0:1; 3442 uint64_t reserved_53_62:10; 3443 uint64_t rst:1; 3444 #endif 3445 } cn61xx; 3446 struct cvmx_ciu_intx_en1_w1s_cn63xx { 3447 #ifdef __BIG_ENDIAN_BITFIELD 3448 uint64_t rst:1; 3449 uint64_t reserved_57_62:6; 3450 uint64_t dfm:1; 3451 uint64_t reserved_53_55:3; 3452 uint64_t lmc0:1; 3453 uint64_t srio1:1; 3454 uint64_t srio0:1; 3455 uint64_t pem1:1; 3456 uint64_t pem0:1; 3457 uint64_t ptp:1; 3458 uint64_t agl:1; 3459 uint64_t reserved_37_45:9; 3460 uint64_t agx0:1; 3461 uint64_t dpi:1; 3462 uint64_t sli:1; 3463 uint64_t usb:1; 3464 uint64_t dfa:1; 3465 uint64_t key:1; 3466 uint64_t rad:1; 3467 uint64_t tim:1; 3468 uint64_t zip:1; 3469 uint64_t pko:1; 3470 uint64_t pip:1; 3471 uint64_t ipd:1; 3472 uint64_t l2c:1; 3473 uint64_t pow:1; 3474 uint64_t fpa:1; 3475 uint64_t iob:1; 3476 uint64_t mio:1; 3477 uint64_t nand:1; 3478 uint64_t mii1:1; 3479 uint64_t reserved_6_17:12; 3480 uint64_t wdog:6; 3481 #else 3482 uint64_t wdog:6; 3483 uint64_t reserved_6_17:12; 3484 uint64_t mii1:1; 3485 uint64_t nand:1; 3486 uint64_t mio:1; 3487 uint64_t iob:1; 3488 uint64_t fpa:1; 3489 uint64_t pow:1; 3490 uint64_t l2c:1; 3491 uint64_t ipd:1; 3492 uint64_t pip:1; 3493 uint64_t pko:1; 3494 uint64_t zip:1; 3495 uint64_t tim:1; 3496 uint64_t rad:1; 3497 uint64_t key:1; 3498 uint64_t dfa:1; 3499 uint64_t usb:1; 3500 uint64_t sli:1; 3501 uint64_t dpi:1; 3502 uint64_t agx0:1; 3503 uint64_t reserved_37_45:9; 3504 uint64_t agl:1; 3505 uint64_t ptp:1; 3506 uint64_t pem0:1; 3507 uint64_t pem1:1; 3508 uint64_t srio0:1; 3509 uint64_t srio1:1; 3510 uint64_t lmc0:1; 3511 uint64_t reserved_53_55:3; 3512 uint64_t dfm:1; 3513 uint64_t reserved_57_62:6; 3514 uint64_t rst:1; 3515 #endif 3516 } cn63xx; 3517 struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1; 3518 struct cvmx_ciu_intx_en1_w1s_cn66xx { 3519 #ifdef __BIG_ENDIAN_BITFIELD 3520 uint64_t rst:1; 3521 uint64_t reserved_62_62:1; 3522 uint64_t srio3:1; 3523 uint64_t srio2:1; 3524 uint64_t reserved_57_59:3; 3525 uint64_t dfm:1; 3526 uint64_t reserved_53_55:3; 3527 uint64_t lmc0:1; 3528 uint64_t reserved_51_51:1; 3529 uint64_t srio0:1; 3530 uint64_t pem1:1; 3531 uint64_t pem0:1; 3532 uint64_t ptp:1; 3533 uint64_t agl:1; 3534 uint64_t reserved_38_45:8; 3535 uint64_t agx1:1; 3536 uint64_t agx0:1; 3537 uint64_t dpi:1; 3538 uint64_t sli:1; 3539 uint64_t usb:1; 3540 uint64_t dfa:1; 3541 uint64_t key:1; 3542 uint64_t rad:1; 3543 uint64_t tim:1; 3544 uint64_t zip:1; 3545 uint64_t pko:1; 3546 uint64_t pip:1; 3547 uint64_t ipd:1; 3548 uint64_t l2c:1; 3549 uint64_t pow:1; 3550 uint64_t fpa:1; 3551 uint64_t iob:1; 3552 uint64_t mio:1; 3553 uint64_t nand:1; 3554 uint64_t mii1:1; 3555 uint64_t reserved_10_17:8; 3556 uint64_t wdog:10; 3557 #else 3558 uint64_t wdog:10; 3559 uint64_t reserved_10_17:8; 3560 uint64_t mii1:1; 3561 uint64_t nand:1; 3562 uint64_t mio:1; 3563 uint64_t iob:1; 3564 uint64_t fpa:1; 3565 uint64_t pow:1; 3566 uint64_t l2c:1; 3567 uint64_t ipd:1; 3568 uint64_t pip:1; 3569 uint64_t pko:1; 3570 uint64_t zip:1; 3571 uint64_t tim:1; 3572 uint64_t rad:1; 3573 uint64_t key:1; 3574 uint64_t dfa:1; 3575 uint64_t usb:1; 3576 uint64_t sli:1; 3577 uint64_t dpi:1; 3578 uint64_t agx0:1; 3579 uint64_t agx1:1; 3580 uint64_t reserved_38_45:8; 3581 uint64_t agl:1; 3582 uint64_t ptp:1; 3583 uint64_t pem0:1; 3584 uint64_t pem1:1; 3585 uint64_t srio0:1; 3586 uint64_t reserved_51_51:1; 3587 uint64_t lmc0:1; 3588 uint64_t reserved_53_55:3; 3589 uint64_t dfm:1; 3590 uint64_t reserved_57_59:3; 3591 uint64_t srio2:1; 3592 uint64_t srio3:1; 3593 uint64_t reserved_62_62:1; 3594 uint64_t rst:1; 3595 #endif 3596 } cn66xx; 3597 struct cvmx_ciu_intx_en1_w1s_cnf71xx { 3598 #ifdef __BIG_ENDIAN_BITFIELD 3599 uint64_t rst:1; 3600 uint64_t reserved_53_62:10; 3601 uint64_t lmc0:1; 3602 uint64_t reserved_50_51:2; 3603 uint64_t pem1:1; 3604 uint64_t pem0:1; 3605 uint64_t ptp:1; 3606 uint64_t reserved_41_46:6; 3607 uint64_t dpi_dma:1; 3608 uint64_t reserved_37_39:3; 3609 uint64_t agx0:1; 3610 uint64_t dpi:1; 3611 uint64_t sli:1; 3612 uint64_t usb:1; 3613 uint64_t reserved_32_32:1; 3614 uint64_t key:1; 3615 uint64_t rad:1; 3616 uint64_t tim:1; 3617 uint64_t reserved_28_28:1; 3618 uint64_t pko:1; 3619 uint64_t pip:1; 3620 uint64_t ipd:1; 3621 uint64_t l2c:1; 3622 uint64_t pow:1; 3623 uint64_t fpa:1; 3624 uint64_t iob:1; 3625 uint64_t mio:1; 3626 uint64_t nand:1; 3627 uint64_t reserved_4_18:15; 3628 uint64_t wdog:4; 3629 #else 3630 uint64_t wdog:4; 3631 uint64_t reserved_4_18:15; 3632 uint64_t nand:1; 3633 uint64_t mio:1; 3634 uint64_t iob:1; 3635 uint64_t fpa:1; 3636 uint64_t pow:1; 3637 uint64_t l2c:1; 3638 uint64_t ipd:1; 3639 uint64_t pip:1; 3640 uint64_t pko:1; 3641 uint64_t reserved_28_28:1; 3642 uint64_t tim:1; 3643 uint64_t rad:1; 3644 uint64_t key:1; 3645 uint64_t reserved_32_32:1; 3646 uint64_t usb:1; 3647 uint64_t sli:1; 3648 uint64_t dpi:1; 3649 uint64_t agx0:1; 3650 uint64_t reserved_37_39:3; 3651 uint64_t dpi_dma:1; 3652 uint64_t reserved_41_46:6; 3653 uint64_t ptp:1; 3654 uint64_t pem0:1; 3655 uint64_t pem1:1; 3656 uint64_t reserved_50_51:2; 3657 uint64_t lmc0:1; 3658 uint64_t reserved_53_62:10; 3659 uint64_t rst:1; 3660 #endif 3661 } cnf71xx; 3662 }; 3663 3664 union cvmx_ciu_intx_en4_0 { 3665 uint64_t u64; 3666 struct cvmx_ciu_intx_en4_0_s { 3667 #ifdef __BIG_ENDIAN_BITFIELD 3668 uint64_t bootdma:1; 3669 uint64_t mii:1; 3670 uint64_t ipdppthr:1; 3671 uint64_t powiq:1; 3672 uint64_t twsi2:1; 3673 uint64_t mpi:1; 3674 uint64_t pcm:1; 3675 uint64_t usb:1; 3676 uint64_t timer:4; 3677 uint64_t key_zero:1; 3678 uint64_t ipd_drp:1; 3679 uint64_t gmx_drp:2; 3680 uint64_t trace:1; 3681 uint64_t rml:1; 3682 uint64_t twsi:1; 3683 uint64_t reserved_44_44:1; 3684 uint64_t pci_msi:4; 3685 uint64_t pci_int:4; 3686 uint64_t uart:2; 3687 uint64_t mbox:2; 3688 uint64_t gpio:16; 3689 uint64_t workq:16; 3690 #else 3691 uint64_t workq:16; 3692 uint64_t gpio:16; 3693 uint64_t mbox:2; 3694 uint64_t uart:2; 3695 uint64_t pci_int:4; 3696 uint64_t pci_msi:4; 3697 uint64_t reserved_44_44:1; 3698 uint64_t twsi:1; 3699 uint64_t rml:1; 3700 uint64_t trace:1; 3701 uint64_t gmx_drp:2; 3702 uint64_t ipd_drp:1; 3703 uint64_t key_zero:1; 3704 uint64_t timer:4; 3705 uint64_t usb:1; 3706 uint64_t pcm:1; 3707 uint64_t mpi:1; 3708 uint64_t twsi2:1; 3709 uint64_t powiq:1; 3710 uint64_t ipdppthr:1; 3711 uint64_t mii:1; 3712 uint64_t bootdma:1; 3713 #endif 3714 } s; 3715 struct cvmx_ciu_intx_en4_0_cn50xx { 3716 #ifdef __BIG_ENDIAN_BITFIELD 3717 uint64_t reserved_59_63:5; 3718 uint64_t mpi:1; 3719 uint64_t pcm:1; 3720 uint64_t usb:1; 3721 uint64_t timer:4; 3722 uint64_t reserved_51_51:1; 3723 uint64_t ipd_drp:1; 3724 uint64_t reserved_49_49:1; 3725 uint64_t gmx_drp:1; 3726 uint64_t reserved_47_47:1; 3727 uint64_t rml:1; 3728 uint64_t twsi:1; 3729 uint64_t reserved_44_44:1; 3730 uint64_t pci_msi:4; 3731 uint64_t pci_int:4; 3732 uint64_t uart:2; 3733 uint64_t mbox:2; 3734 uint64_t gpio:16; 3735 uint64_t workq:16; 3736 #else 3737 uint64_t workq:16; 3738 uint64_t gpio:16; 3739 uint64_t mbox:2; 3740 uint64_t uart:2; 3741 uint64_t pci_int:4; 3742 uint64_t pci_msi:4; 3743 uint64_t reserved_44_44:1; 3744 uint64_t twsi:1; 3745 uint64_t rml:1; 3746 uint64_t reserved_47_47:1; 3747 uint64_t gmx_drp:1; 3748 uint64_t reserved_49_49:1; 3749 uint64_t ipd_drp:1; 3750 uint64_t reserved_51_51:1; 3751 uint64_t timer:4; 3752 uint64_t usb:1; 3753 uint64_t pcm:1; 3754 uint64_t mpi:1; 3755 uint64_t reserved_59_63:5; 3756 #endif 3757 } cn50xx; 3758 struct cvmx_ciu_intx_en4_0_cn52xx { 3759 #ifdef __BIG_ENDIAN_BITFIELD 3760 uint64_t bootdma:1; 3761 uint64_t mii:1; 3762 uint64_t ipdppthr:1; 3763 uint64_t powiq:1; 3764 uint64_t twsi2:1; 3765 uint64_t reserved_57_58:2; 3766 uint64_t usb:1; 3767 uint64_t timer:4; 3768 uint64_t reserved_51_51:1; 3769 uint64_t ipd_drp:1; 3770 uint64_t reserved_49_49:1; 3771 uint64_t gmx_drp:1; 3772 uint64_t trace:1; 3773 uint64_t rml:1; 3774 uint64_t twsi:1; 3775 uint64_t reserved_44_44:1; 3776 uint64_t pci_msi:4; 3777 uint64_t pci_int:4; 3778 uint64_t uart:2; 3779 uint64_t mbox:2; 3780 uint64_t gpio:16; 3781 uint64_t workq:16; 3782 #else 3783 uint64_t workq:16; 3784 uint64_t gpio:16; 3785 uint64_t mbox:2; 3786 uint64_t uart:2; 3787 uint64_t pci_int:4; 3788 uint64_t pci_msi:4; 3789 uint64_t reserved_44_44:1; 3790 uint64_t twsi:1; 3791 uint64_t rml:1; 3792 uint64_t trace:1; 3793 uint64_t gmx_drp:1; 3794 uint64_t reserved_49_49:1; 3795 uint64_t ipd_drp:1; 3796 uint64_t reserved_51_51:1; 3797 uint64_t timer:4; 3798 uint64_t usb:1; 3799 uint64_t reserved_57_58:2; 3800 uint64_t twsi2:1; 3801 uint64_t powiq:1; 3802 uint64_t ipdppthr:1; 3803 uint64_t mii:1; 3804 uint64_t bootdma:1; 3805 #endif 3806 } cn52xx; 3807 struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; 3808 struct cvmx_ciu_intx_en4_0_cn56xx { 3809 #ifdef __BIG_ENDIAN_BITFIELD 3810 uint64_t bootdma:1; 3811 uint64_t mii:1; 3812 uint64_t ipdppthr:1; 3813 uint64_t powiq:1; 3814 uint64_t twsi2:1; 3815 uint64_t reserved_57_58:2; 3816 uint64_t usb:1; 3817 uint64_t timer:4; 3818 uint64_t key_zero:1; 3819 uint64_t ipd_drp:1; 3820 uint64_t gmx_drp:2; 3821 uint64_t trace:1; 3822 uint64_t rml:1; 3823 uint64_t twsi:1; 3824 uint64_t reserved_44_44:1; 3825 uint64_t pci_msi:4; 3826 uint64_t pci_int:4; 3827 uint64_t uart:2; 3828 uint64_t mbox:2; 3829 uint64_t gpio:16; 3830 uint64_t workq:16; 3831 #else 3832 uint64_t workq:16; 3833 uint64_t gpio:16; 3834 uint64_t mbox:2; 3835 uint64_t uart:2; 3836 uint64_t pci_int:4; 3837 uint64_t pci_msi:4; 3838 uint64_t reserved_44_44:1; 3839 uint64_t twsi:1; 3840 uint64_t rml:1; 3841 uint64_t trace:1; 3842 uint64_t gmx_drp:2; 3843 uint64_t ipd_drp:1; 3844 uint64_t key_zero:1; 3845 uint64_t timer:4; 3846 uint64_t usb:1; 3847 uint64_t reserved_57_58:2; 3848 uint64_t twsi2:1; 3849 uint64_t powiq:1; 3850 uint64_t ipdppthr:1; 3851 uint64_t mii:1; 3852 uint64_t bootdma:1; 3853 #endif 3854 } cn56xx; 3855 struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; 3856 struct cvmx_ciu_intx_en4_0_cn58xx { 3857 #ifdef __BIG_ENDIAN_BITFIELD 3858 uint64_t reserved_56_63:8; 3859 uint64_t timer:4; 3860 uint64_t key_zero:1; 3861 uint64_t ipd_drp:1; 3862 uint64_t gmx_drp:2; 3863 uint64_t trace:1; 3864 uint64_t rml:1; 3865 uint64_t twsi:1; 3866 uint64_t reserved_44_44:1; 3867 uint64_t pci_msi:4; 3868 uint64_t pci_int:4; 3869 uint64_t uart:2; 3870 uint64_t mbox:2; 3871 uint64_t gpio:16; 3872 uint64_t workq:16; 3873 #else 3874 uint64_t workq:16; 3875 uint64_t gpio:16; 3876 uint64_t mbox:2; 3877 uint64_t uart:2; 3878 uint64_t pci_int:4; 3879 uint64_t pci_msi:4; 3880 uint64_t reserved_44_44:1; 3881 uint64_t twsi:1; 3882 uint64_t rml:1; 3883 uint64_t trace:1; 3884 uint64_t gmx_drp:2; 3885 uint64_t ipd_drp:1; 3886 uint64_t key_zero:1; 3887 uint64_t timer:4; 3888 uint64_t reserved_56_63:8; 3889 #endif 3890 } cn58xx; 3891 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; 3892 struct cvmx_ciu_intx_en4_0_cn61xx { 3893 #ifdef __BIG_ENDIAN_BITFIELD 3894 uint64_t bootdma:1; 3895 uint64_t mii:1; 3896 uint64_t ipdppthr:1; 3897 uint64_t powiq:1; 3898 uint64_t twsi2:1; 3899 uint64_t mpi:1; 3900 uint64_t pcm:1; 3901 uint64_t usb:1; 3902 uint64_t timer:4; 3903 uint64_t reserved_51_51:1; 3904 uint64_t ipd_drp:1; 3905 uint64_t gmx_drp:2; 3906 uint64_t trace:1; 3907 uint64_t rml:1; 3908 uint64_t twsi:1; 3909 uint64_t reserved_44_44:1; 3910 uint64_t pci_msi:4; 3911 uint64_t pci_int:4; 3912 uint64_t uart:2; 3913 uint64_t mbox:2; 3914 uint64_t gpio:16; 3915 uint64_t workq:16; 3916 #else 3917 uint64_t workq:16; 3918 uint64_t gpio:16; 3919 uint64_t mbox:2; 3920 uint64_t uart:2; 3921 uint64_t pci_int:4; 3922 uint64_t pci_msi:4; 3923 uint64_t reserved_44_44:1; 3924 uint64_t twsi:1; 3925 uint64_t rml:1; 3926 uint64_t trace:1; 3927 uint64_t gmx_drp:2; 3928 uint64_t ipd_drp:1; 3929 uint64_t reserved_51_51:1; 3930 uint64_t timer:4; 3931 uint64_t usb:1; 3932 uint64_t pcm:1; 3933 uint64_t mpi:1; 3934 uint64_t twsi2:1; 3935 uint64_t powiq:1; 3936 uint64_t ipdppthr:1; 3937 uint64_t mii:1; 3938 uint64_t bootdma:1; 3939 #endif 3940 } cn61xx; 3941 struct cvmx_ciu_intx_en4_0_cn52xx cn63xx; 3942 struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1; 3943 struct cvmx_ciu_intx_en4_0_cn66xx { 3944 #ifdef __BIG_ENDIAN_BITFIELD 3945 uint64_t bootdma:1; 3946 uint64_t mii:1; 3947 uint64_t ipdppthr:1; 3948 uint64_t powiq:1; 3949 uint64_t twsi2:1; 3950 uint64_t mpi:1; 3951 uint64_t reserved_57_57:1; 3952 uint64_t usb:1; 3953 uint64_t timer:4; 3954 uint64_t reserved_51_51:1; 3955 uint64_t ipd_drp:1; 3956 uint64_t gmx_drp:2; 3957 uint64_t trace:1; 3958 uint64_t rml:1; 3959 uint64_t twsi:1; 3960 uint64_t reserved_44_44:1; 3961 uint64_t pci_msi:4; 3962 uint64_t pci_int:4; 3963 uint64_t uart:2; 3964 uint64_t mbox:2; 3965 uint64_t gpio:16; 3966 uint64_t workq:16; 3967 #else 3968 uint64_t workq:16; 3969 uint64_t gpio:16; 3970 uint64_t mbox:2; 3971 uint64_t uart:2; 3972 uint64_t pci_int:4; 3973 uint64_t pci_msi:4; 3974 uint64_t reserved_44_44:1; 3975 uint64_t twsi:1; 3976 uint64_t rml:1; 3977 uint64_t trace:1; 3978 uint64_t gmx_drp:2; 3979 uint64_t ipd_drp:1; 3980 uint64_t reserved_51_51:1; 3981 uint64_t timer:4; 3982 uint64_t usb:1; 3983 uint64_t reserved_57_57:1; 3984 uint64_t mpi:1; 3985 uint64_t twsi2:1; 3986 uint64_t powiq:1; 3987 uint64_t ipdppthr:1; 3988 uint64_t mii:1; 3989 uint64_t bootdma:1; 3990 #endif 3991 } cn66xx; 3992 struct cvmx_ciu_intx_en4_0_cnf71xx { 3993 #ifdef __BIG_ENDIAN_BITFIELD 3994 uint64_t bootdma:1; 3995 uint64_t reserved_62_62:1; 3996 uint64_t ipdppthr:1; 3997 uint64_t powiq:1; 3998 uint64_t twsi2:1; 3999 uint64_t mpi:1; 4000 uint64_t pcm:1; 4001 uint64_t usb:1; 4002 uint64_t timer:4; 4003 uint64_t reserved_51_51:1; 4004 uint64_t ipd_drp:1; 4005 uint64_t reserved_49_49:1; 4006 uint64_t gmx_drp:1; 4007 uint64_t trace:1; 4008 uint64_t rml:1; 4009 uint64_t twsi:1; 4010 uint64_t reserved_44_44:1; 4011 uint64_t pci_msi:4; 4012 uint64_t pci_int:4; 4013 uint64_t uart:2; 4014 uint64_t mbox:2; 4015 uint64_t gpio:16; 4016 uint64_t workq:16; 4017 #else 4018 uint64_t workq:16; 4019 uint64_t gpio:16; 4020 uint64_t mbox:2; 4021 uint64_t uart:2; 4022 uint64_t pci_int:4; 4023 uint64_t pci_msi:4; 4024 uint64_t reserved_44_44:1; 4025 uint64_t twsi:1; 4026 uint64_t rml:1; 4027 uint64_t trace:1; 4028 uint64_t gmx_drp:1; 4029 uint64_t reserved_49_49:1; 4030 uint64_t ipd_drp:1; 4031 uint64_t reserved_51_51:1; 4032 uint64_t timer:4; 4033 uint64_t usb:1; 4034 uint64_t pcm:1; 4035 uint64_t mpi:1; 4036 uint64_t twsi2:1; 4037 uint64_t powiq:1; 4038 uint64_t ipdppthr:1; 4039 uint64_t reserved_62_62:1; 4040 uint64_t bootdma:1; 4041 #endif 4042 } cnf71xx; 4043 }; 4044 4045 union cvmx_ciu_intx_en4_0_w1c { 4046 uint64_t u64; 4047 struct cvmx_ciu_intx_en4_0_w1c_s { 4048 #ifdef __BIG_ENDIAN_BITFIELD 4049 uint64_t bootdma:1; 4050 uint64_t mii:1; 4051 uint64_t ipdppthr:1; 4052 uint64_t powiq:1; 4053 uint64_t twsi2:1; 4054 uint64_t mpi:1; 4055 uint64_t pcm:1; 4056 uint64_t usb:1; 4057 uint64_t timer:4; 4058 uint64_t key_zero:1; 4059 uint64_t ipd_drp:1; 4060 uint64_t gmx_drp:2; 4061 uint64_t trace:1; 4062 uint64_t rml:1; 4063 uint64_t twsi:1; 4064 uint64_t reserved_44_44:1; 4065 uint64_t pci_msi:4; 4066 uint64_t pci_int:4; 4067 uint64_t uart:2; 4068 uint64_t mbox:2; 4069 uint64_t gpio:16; 4070 uint64_t workq:16; 4071 #else 4072 uint64_t workq:16; 4073 uint64_t gpio:16; 4074 uint64_t mbox:2; 4075 uint64_t uart:2; 4076 uint64_t pci_int:4; 4077 uint64_t pci_msi:4; 4078 uint64_t reserved_44_44:1; 4079 uint64_t twsi:1; 4080 uint64_t rml:1; 4081 uint64_t trace:1; 4082 uint64_t gmx_drp:2; 4083 uint64_t ipd_drp:1; 4084 uint64_t key_zero:1; 4085 uint64_t timer:4; 4086 uint64_t usb:1; 4087 uint64_t pcm:1; 4088 uint64_t mpi:1; 4089 uint64_t twsi2:1; 4090 uint64_t powiq:1; 4091 uint64_t ipdppthr:1; 4092 uint64_t mii:1; 4093 uint64_t bootdma:1; 4094 #endif 4095 } s; 4096 struct cvmx_ciu_intx_en4_0_w1c_cn52xx { 4097 #ifdef __BIG_ENDIAN_BITFIELD 4098 uint64_t bootdma:1; 4099 uint64_t mii:1; 4100 uint64_t ipdppthr:1; 4101 uint64_t powiq:1; 4102 uint64_t twsi2:1; 4103 uint64_t reserved_57_58:2; 4104 uint64_t usb:1; 4105 uint64_t timer:4; 4106 uint64_t reserved_51_51:1; 4107 uint64_t ipd_drp:1; 4108 uint64_t reserved_49_49:1; 4109 uint64_t gmx_drp:1; 4110 uint64_t trace:1; 4111 uint64_t rml:1; 4112 uint64_t twsi:1; 4113 uint64_t reserved_44_44:1; 4114 uint64_t pci_msi:4; 4115 uint64_t pci_int:4; 4116 uint64_t uart:2; 4117 uint64_t mbox:2; 4118 uint64_t gpio:16; 4119 uint64_t workq:16; 4120 #else 4121 uint64_t workq:16; 4122 uint64_t gpio:16; 4123 uint64_t mbox:2; 4124 uint64_t uart:2; 4125 uint64_t pci_int:4; 4126 uint64_t pci_msi:4; 4127 uint64_t reserved_44_44:1; 4128 uint64_t twsi:1; 4129 uint64_t rml:1; 4130 uint64_t trace:1; 4131 uint64_t gmx_drp:1; 4132 uint64_t reserved_49_49:1; 4133 uint64_t ipd_drp:1; 4134 uint64_t reserved_51_51:1; 4135 uint64_t timer:4; 4136 uint64_t usb:1; 4137 uint64_t reserved_57_58:2; 4138 uint64_t twsi2:1; 4139 uint64_t powiq:1; 4140 uint64_t ipdppthr:1; 4141 uint64_t mii:1; 4142 uint64_t bootdma:1; 4143 #endif 4144 } cn52xx; 4145 struct cvmx_ciu_intx_en4_0_w1c_cn56xx { 4146 #ifdef __BIG_ENDIAN_BITFIELD 4147 uint64_t bootdma:1; 4148 uint64_t mii:1; 4149 uint64_t ipdppthr:1; 4150 uint64_t powiq:1; 4151 uint64_t twsi2:1; 4152 uint64_t reserved_57_58:2; 4153 uint64_t usb:1; 4154 uint64_t timer:4; 4155 uint64_t key_zero:1; 4156 uint64_t ipd_drp:1; 4157 uint64_t gmx_drp:2; 4158 uint64_t trace:1; 4159 uint64_t rml:1; 4160 uint64_t twsi:1; 4161 uint64_t reserved_44_44:1; 4162 uint64_t pci_msi:4; 4163 uint64_t pci_int:4; 4164 uint64_t uart:2; 4165 uint64_t mbox:2; 4166 uint64_t gpio:16; 4167 uint64_t workq:16; 4168 #else 4169 uint64_t workq:16; 4170 uint64_t gpio:16; 4171 uint64_t mbox:2; 4172 uint64_t uart:2; 4173 uint64_t pci_int:4; 4174 uint64_t pci_msi:4; 4175 uint64_t reserved_44_44:1; 4176 uint64_t twsi:1; 4177 uint64_t rml:1; 4178 uint64_t trace:1; 4179 uint64_t gmx_drp:2; 4180 uint64_t ipd_drp:1; 4181 uint64_t key_zero:1; 4182 uint64_t timer:4; 4183 uint64_t usb:1; 4184 uint64_t reserved_57_58:2; 4185 uint64_t twsi2:1; 4186 uint64_t powiq:1; 4187 uint64_t ipdppthr:1; 4188 uint64_t mii:1; 4189 uint64_t bootdma:1; 4190 #endif 4191 } cn56xx; 4192 struct cvmx_ciu_intx_en4_0_w1c_cn58xx { 4193 #ifdef __BIG_ENDIAN_BITFIELD 4194 uint64_t reserved_56_63:8; 4195 uint64_t timer:4; 4196 uint64_t key_zero:1; 4197 uint64_t ipd_drp:1; 4198 uint64_t gmx_drp:2; 4199 uint64_t trace:1; 4200 uint64_t rml:1; 4201 uint64_t twsi:1; 4202 uint64_t reserved_44_44:1; 4203 uint64_t pci_msi:4; 4204 uint64_t pci_int:4; 4205 uint64_t uart:2; 4206 uint64_t mbox:2; 4207 uint64_t gpio:16; 4208 uint64_t workq:16; 4209 #else 4210 uint64_t workq:16; 4211 uint64_t gpio:16; 4212 uint64_t mbox:2; 4213 uint64_t uart:2; 4214 uint64_t pci_int:4; 4215 uint64_t pci_msi:4; 4216 uint64_t reserved_44_44:1; 4217 uint64_t twsi:1; 4218 uint64_t rml:1; 4219 uint64_t trace:1; 4220 uint64_t gmx_drp:2; 4221 uint64_t ipd_drp:1; 4222 uint64_t key_zero:1; 4223 uint64_t timer:4; 4224 uint64_t reserved_56_63:8; 4225 #endif 4226 } cn58xx; 4227 struct cvmx_ciu_intx_en4_0_w1c_cn61xx { 4228 #ifdef __BIG_ENDIAN_BITFIELD 4229 uint64_t bootdma:1; 4230 uint64_t mii:1; 4231 uint64_t ipdppthr:1; 4232 uint64_t powiq:1; 4233 uint64_t twsi2:1; 4234 uint64_t mpi:1; 4235 uint64_t pcm:1; 4236 uint64_t usb:1; 4237 uint64_t timer:4; 4238 uint64_t reserved_51_51:1; 4239 uint64_t ipd_drp:1; 4240 uint64_t gmx_drp:2; 4241 uint64_t trace:1; 4242 uint64_t rml:1; 4243 uint64_t twsi:1; 4244 uint64_t reserved_44_44:1; 4245 uint64_t pci_msi:4; 4246 uint64_t pci_int:4; 4247 uint64_t uart:2; 4248 uint64_t mbox:2; 4249 uint64_t gpio:16; 4250 uint64_t workq:16; 4251 #else 4252 uint64_t workq:16; 4253 uint64_t gpio:16; 4254 uint64_t mbox:2; 4255 uint64_t uart:2; 4256 uint64_t pci_int:4; 4257 uint64_t pci_msi:4; 4258 uint64_t reserved_44_44:1; 4259 uint64_t twsi:1; 4260 uint64_t rml:1; 4261 uint64_t trace:1; 4262 uint64_t gmx_drp:2; 4263 uint64_t ipd_drp:1; 4264 uint64_t reserved_51_51:1; 4265 uint64_t timer:4; 4266 uint64_t usb:1; 4267 uint64_t pcm:1; 4268 uint64_t mpi:1; 4269 uint64_t twsi2:1; 4270 uint64_t powiq:1; 4271 uint64_t ipdppthr:1; 4272 uint64_t mii:1; 4273 uint64_t bootdma:1; 4274 #endif 4275 } cn61xx; 4276 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx; 4277 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1; 4278 struct cvmx_ciu_intx_en4_0_w1c_cn66xx { 4279 #ifdef __BIG_ENDIAN_BITFIELD 4280 uint64_t bootdma:1; 4281 uint64_t mii:1; 4282 uint64_t ipdppthr:1; 4283 uint64_t powiq:1; 4284 uint64_t twsi2:1; 4285 uint64_t mpi:1; 4286 uint64_t reserved_57_57:1; 4287 uint64_t usb:1; 4288 uint64_t timer:4; 4289 uint64_t reserved_51_51:1; 4290 uint64_t ipd_drp:1; 4291 uint64_t gmx_drp:2; 4292 uint64_t trace:1; 4293 uint64_t rml:1; 4294 uint64_t twsi:1; 4295 uint64_t reserved_44_44:1; 4296 uint64_t pci_msi:4; 4297 uint64_t pci_int:4; 4298 uint64_t uart:2; 4299 uint64_t mbox:2; 4300 uint64_t gpio:16; 4301 uint64_t workq:16; 4302 #else 4303 uint64_t workq:16; 4304 uint64_t gpio:16; 4305 uint64_t mbox:2; 4306 uint64_t uart:2; 4307 uint64_t pci_int:4; 4308 uint64_t pci_msi:4; 4309 uint64_t reserved_44_44:1; 4310 uint64_t twsi:1; 4311 uint64_t rml:1; 4312 uint64_t trace:1; 4313 uint64_t gmx_drp:2; 4314 uint64_t ipd_drp:1; 4315 uint64_t reserved_51_51:1; 4316 uint64_t timer:4; 4317 uint64_t usb:1; 4318 uint64_t reserved_57_57:1; 4319 uint64_t mpi:1; 4320 uint64_t twsi2:1; 4321 uint64_t powiq:1; 4322 uint64_t ipdppthr:1; 4323 uint64_t mii:1; 4324 uint64_t bootdma:1; 4325 #endif 4326 } cn66xx; 4327 struct cvmx_ciu_intx_en4_0_w1c_cnf71xx { 4328 #ifdef __BIG_ENDIAN_BITFIELD 4329 uint64_t bootdma:1; 4330 uint64_t reserved_62_62:1; 4331 uint64_t ipdppthr:1; 4332 uint64_t powiq:1; 4333 uint64_t twsi2:1; 4334 uint64_t mpi:1; 4335 uint64_t pcm:1; 4336 uint64_t usb:1; 4337 uint64_t timer:4; 4338 uint64_t reserved_51_51:1; 4339 uint64_t ipd_drp:1; 4340 uint64_t reserved_49_49:1; 4341 uint64_t gmx_drp:1; 4342 uint64_t trace:1; 4343 uint64_t rml:1; 4344 uint64_t twsi:1; 4345 uint64_t reserved_44_44:1; 4346 uint64_t pci_msi:4; 4347 uint64_t pci_int:4; 4348 uint64_t uart:2; 4349 uint64_t mbox:2; 4350 uint64_t gpio:16; 4351 uint64_t workq:16; 4352 #else 4353 uint64_t workq:16; 4354 uint64_t gpio:16; 4355 uint64_t mbox:2; 4356 uint64_t uart:2; 4357 uint64_t pci_int:4; 4358 uint64_t pci_msi:4; 4359 uint64_t reserved_44_44:1; 4360 uint64_t twsi:1; 4361 uint64_t rml:1; 4362 uint64_t trace:1; 4363 uint64_t gmx_drp:1; 4364 uint64_t reserved_49_49:1; 4365 uint64_t ipd_drp:1; 4366 uint64_t reserved_51_51:1; 4367 uint64_t timer:4; 4368 uint64_t usb:1; 4369 uint64_t pcm:1; 4370 uint64_t mpi:1; 4371 uint64_t twsi2:1; 4372 uint64_t powiq:1; 4373 uint64_t ipdppthr:1; 4374 uint64_t reserved_62_62:1; 4375 uint64_t bootdma:1; 4376 #endif 4377 } cnf71xx; 4378 }; 4379 4380 union cvmx_ciu_intx_en4_0_w1s { 4381 uint64_t u64; 4382 struct cvmx_ciu_intx_en4_0_w1s_s { 4383 #ifdef __BIG_ENDIAN_BITFIELD 4384 uint64_t bootdma:1; 4385 uint64_t mii:1; 4386 uint64_t ipdppthr:1; 4387 uint64_t powiq:1; 4388 uint64_t twsi2:1; 4389 uint64_t mpi:1; 4390 uint64_t pcm:1; 4391 uint64_t usb:1; 4392 uint64_t timer:4; 4393 uint64_t key_zero:1; 4394 uint64_t ipd_drp:1; 4395 uint64_t gmx_drp:2; 4396 uint64_t trace:1; 4397 uint64_t rml:1; 4398 uint64_t twsi:1; 4399 uint64_t reserved_44_44:1; 4400 uint64_t pci_msi:4; 4401 uint64_t pci_int:4; 4402 uint64_t uart:2; 4403 uint64_t mbox:2; 4404 uint64_t gpio:16; 4405 uint64_t workq:16; 4406 #else 4407 uint64_t workq:16; 4408 uint64_t gpio:16; 4409 uint64_t mbox:2; 4410 uint64_t uart:2; 4411 uint64_t pci_int:4; 4412 uint64_t pci_msi:4; 4413 uint64_t reserved_44_44:1; 4414 uint64_t twsi:1; 4415 uint64_t rml:1; 4416 uint64_t trace:1; 4417 uint64_t gmx_drp:2; 4418 uint64_t ipd_drp:1; 4419 uint64_t key_zero:1; 4420 uint64_t timer:4; 4421 uint64_t usb:1; 4422 uint64_t pcm:1; 4423 uint64_t mpi:1; 4424 uint64_t twsi2:1; 4425 uint64_t powiq:1; 4426 uint64_t ipdppthr:1; 4427 uint64_t mii:1; 4428 uint64_t bootdma:1; 4429 #endif 4430 } s; 4431 struct cvmx_ciu_intx_en4_0_w1s_cn52xx { 4432 #ifdef __BIG_ENDIAN_BITFIELD 4433 uint64_t bootdma:1; 4434 uint64_t mii:1; 4435 uint64_t ipdppthr:1; 4436 uint64_t powiq:1; 4437 uint64_t twsi2:1; 4438 uint64_t reserved_57_58:2; 4439 uint64_t usb:1; 4440 uint64_t timer:4; 4441 uint64_t reserved_51_51:1; 4442 uint64_t ipd_drp:1; 4443 uint64_t reserved_49_49:1; 4444 uint64_t gmx_drp:1; 4445 uint64_t trace:1; 4446 uint64_t rml:1; 4447 uint64_t twsi:1; 4448 uint64_t reserved_44_44:1; 4449 uint64_t pci_msi:4; 4450 uint64_t pci_int:4; 4451 uint64_t uart:2; 4452 uint64_t mbox:2; 4453 uint64_t gpio:16; 4454 uint64_t workq:16; 4455 #else 4456 uint64_t workq:16; 4457 uint64_t gpio:16; 4458 uint64_t mbox:2; 4459 uint64_t uart:2; 4460 uint64_t pci_int:4; 4461 uint64_t pci_msi:4; 4462 uint64_t reserved_44_44:1; 4463 uint64_t twsi:1; 4464 uint64_t rml:1; 4465 uint64_t trace:1; 4466 uint64_t gmx_drp:1; 4467 uint64_t reserved_49_49:1; 4468 uint64_t ipd_drp:1; 4469 uint64_t reserved_51_51:1; 4470 uint64_t timer:4; 4471 uint64_t usb:1; 4472 uint64_t reserved_57_58:2; 4473 uint64_t twsi2:1; 4474 uint64_t powiq:1; 4475 uint64_t ipdppthr:1; 4476 uint64_t mii:1; 4477 uint64_t bootdma:1; 4478 #endif 4479 } cn52xx; 4480 struct cvmx_ciu_intx_en4_0_w1s_cn56xx { 4481 #ifdef __BIG_ENDIAN_BITFIELD 4482 uint64_t bootdma:1; 4483 uint64_t mii:1; 4484 uint64_t ipdppthr:1; 4485 uint64_t powiq:1; 4486 uint64_t twsi2:1; 4487 uint64_t reserved_57_58:2; 4488 uint64_t usb:1; 4489 uint64_t timer:4; 4490 uint64_t key_zero:1; 4491 uint64_t ipd_drp:1; 4492 uint64_t gmx_drp:2; 4493 uint64_t trace:1; 4494 uint64_t rml:1; 4495 uint64_t twsi:1; 4496 uint64_t reserved_44_44:1; 4497 uint64_t pci_msi:4; 4498 uint64_t pci_int:4; 4499 uint64_t uart:2; 4500 uint64_t mbox:2; 4501 uint64_t gpio:16; 4502 uint64_t workq:16; 4503 #else 4504 uint64_t workq:16; 4505 uint64_t gpio:16; 4506 uint64_t mbox:2; 4507 uint64_t uart:2; 4508 uint64_t pci_int:4; 4509 uint64_t pci_msi:4; 4510 uint64_t reserved_44_44:1; 4511 uint64_t twsi:1; 4512 uint64_t rml:1; 4513 uint64_t trace:1; 4514 uint64_t gmx_drp:2; 4515 uint64_t ipd_drp:1; 4516 uint64_t key_zero:1; 4517 uint64_t timer:4; 4518 uint64_t usb:1; 4519 uint64_t reserved_57_58:2; 4520 uint64_t twsi2:1; 4521 uint64_t powiq:1; 4522 uint64_t ipdppthr:1; 4523 uint64_t mii:1; 4524 uint64_t bootdma:1; 4525 #endif 4526 } cn56xx; 4527 struct cvmx_ciu_intx_en4_0_w1s_cn58xx { 4528 #ifdef __BIG_ENDIAN_BITFIELD 4529 uint64_t reserved_56_63:8; 4530 uint64_t timer:4; 4531 uint64_t key_zero:1; 4532 uint64_t ipd_drp:1; 4533 uint64_t gmx_drp:2; 4534 uint64_t trace:1; 4535 uint64_t rml:1; 4536 uint64_t twsi:1; 4537 uint64_t reserved_44_44:1; 4538 uint64_t pci_msi:4; 4539 uint64_t pci_int:4; 4540 uint64_t uart:2; 4541 uint64_t mbox:2; 4542 uint64_t gpio:16; 4543 uint64_t workq:16; 4544 #else 4545 uint64_t workq:16; 4546 uint64_t gpio:16; 4547 uint64_t mbox:2; 4548 uint64_t uart:2; 4549 uint64_t pci_int:4; 4550 uint64_t pci_msi:4; 4551 uint64_t reserved_44_44:1; 4552 uint64_t twsi:1; 4553 uint64_t rml:1; 4554 uint64_t trace:1; 4555 uint64_t gmx_drp:2; 4556 uint64_t ipd_drp:1; 4557 uint64_t key_zero:1; 4558 uint64_t timer:4; 4559 uint64_t reserved_56_63:8; 4560 #endif 4561 } cn58xx; 4562 struct cvmx_ciu_intx_en4_0_w1s_cn61xx { 4563 #ifdef __BIG_ENDIAN_BITFIELD 4564 uint64_t bootdma:1; 4565 uint64_t mii:1; 4566 uint64_t ipdppthr:1; 4567 uint64_t powiq:1; 4568 uint64_t twsi2:1; 4569 uint64_t mpi:1; 4570 uint64_t pcm:1; 4571 uint64_t usb:1; 4572 uint64_t timer:4; 4573 uint64_t reserved_51_51:1; 4574 uint64_t ipd_drp:1; 4575 uint64_t gmx_drp:2; 4576 uint64_t trace:1; 4577 uint64_t rml:1; 4578 uint64_t twsi:1; 4579 uint64_t reserved_44_44:1; 4580 uint64_t pci_msi:4; 4581 uint64_t pci_int:4; 4582 uint64_t uart:2; 4583 uint64_t mbox:2; 4584 uint64_t gpio:16; 4585 uint64_t workq:16; 4586 #else 4587 uint64_t workq:16; 4588 uint64_t gpio:16; 4589 uint64_t mbox:2; 4590 uint64_t uart:2; 4591 uint64_t pci_int:4; 4592 uint64_t pci_msi:4; 4593 uint64_t reserved_44_44:1; 4594 uint64_t twsi:1; 4595 uint64_t rml:1; 4596 uint64_t trace:1; 4597 uint64_t gmx_drp:2; 4598 uint64_t ipd_drp:1; 4599 uint64_t reserved_51_51:1; 4600 uint64_t timer:4; 4601 uint64_t usb:1; 4602 uint64_t pcm:1; 4603 uint64_t mpi:1; 4604 uint64_t twsi2:1; 4605 uint64_t powiq:1; 4606 uint64_t ipdppthr:1; 4607 uint64_t mii:1; 4608 uint64_t bootdma:1; 4609 #endif 4610 } cn61xx; 4611 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx; 4612 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1; 4613 struct cvmx_ciu_intx_en4_0_w1s_cn66xx { 4614 #ifdef __BIG_ENDIAN_BITFIELD 4615 uint64_t bootdma:1; 4616 uint64_t mii:1; 4617 uint64_t ipdppthr:1; 4618 uint64_t powiq:1; 4619 uint64_t twsi2:1; 4620 uint64_t mpi:1; 4621 uint64_t reserved_57_57:1; 4622 uint64_t usb:1; 4623 uint64_t timer:4; 4624 uint64_t reserved_51_51:1; 4625 uint64_t ipd_drp:1; 4626 uint64_t gmx_drp:2; 4627 uint64_t trace:1; 4628 uint64_t rml:1; 4629 uint64_t twsi:1; 4630 uint64_t reserved_44_44:1; 4631 uint64_t pci_msi:4; 4632 uint64_t pci_int:4; 4633 uint64_t uart:2; 4634 uint64_t mbox:2; 4635 uint64_t gpio:16; 4636 uint64_t workq:16; 4637 #else 4638 uint64_t workq:16; 4639 uint64_t gpio:16; 4640 uint64_t mbox:2; 4641 uint64_t uart:2; 4642 uint64_t pci_int:4; 4643 uint64_t pci_msi:4; 4644 uint64_t reserved_44_44:1; 4645 uint64_t twsi:1; 4646 uint64_t rml:1; 4647 uint64_t trace:1; 4648 uint64_t gmx_drp:2; 4649 uint64_t ipd_drp:1; 4650 uint64_t reserved_51_51:1; 4651 uint64_t timer:4; 4652 uint64_t usb:1; 4653 uint64_t reserved_57_57:1; 4654 uint64_t mpi:1; 4655 uint64_t twsi2:1; 4656 uint64_t powiq:1; 4657 uint64_t ipdppthr:1; 4658 uint64_t mii:1; 4659 uint64_t bootdma:1; 4660 #endif 4661 } cn66xx; 4662 struct cvmx_ciu_intx_en4_0_w1s_cnf71xx { 4663 #ifdef __BIG_ENDIAN_BITFIELD 4664 uint64_t bootdma:1; 4665 uint64_t reserved_62_62:1; 4666 uint64_t ipdppthr:1; 4667 uint64_t powiq:1; 4668 uint64_t twsi2:1; 4669 uint64_t mpi:1; 4670 uint64_t pcm:1; 4671 uint64_t usb:1; 4672 uint64_t timer:4; 4673 uint64_t reserved_51_51:1; 4674 uint64_t ipd_drp:1; 4675 uint64_t reserved_49_49:1; 4676 uint64_t gmx_drp:1; 4677 uint64_t trace:1; 4678 uint64_t rml:1; 4679 uint64_t twsi:1; 4680 uint64_t reserved_44_44:1; 4681 uint64_t pci_msi:4; 4682 uint64_t pci_int:4; 4683 uint64_t uart:2; 4684 uint64_t mbox:2; 4685 uint64_t gpio:16; 4686 uint64_t workq:16; 4687 #else 4688 uint64_t workq:16; 4689 uint64_t gpio:16; 4690 uint64_t mbox:2; 4691 uint64_t uart:2; 4692 uint64_t pci_int:4; 4693 uint64_t pci_msi:4; 4694 uint64_t reserved_44_44:1; 4695 uint64_t twsi:1; 4696 uint64_t rml:1; 4697 uint64_t trace:1; 4698 uint64_t gmx_drp:1; 4699 uint64_t reserved_49_49:1; 4700 uint64_t ipd_drp:1; 4701 uint64_t reserved_51_51:1; 4702 uint64_t timer:4; 4703 uint64_t usb:1; 4704 uint64_t pcm:1; 4705 uint64_t mpi:1; 4706 uint64_t twsi2:1; 4707 uint64_t powiq:1; 4708 uint64_t ipdppthr:1; 4709 uint64_t reserved_62_62:1; 4710 uint64_t bootdma:1; 4711 #endif 4712 } cnf71xx; 4713 }; 4714 4715 union cvmx_ciu_intx_en4_1 { 4716 uint64_t u64; 4717 struct cvmx_ciu_intx_en4_1_s { 4718 #ifdef __BIG_ENDIAN_BITFIELD 4719 uint64_t rst:1; 4720 uint64_t reserved_62_62:1; 4721 uint64_t srio3:1; 4722 uint64_t srio2:1; 4723 uint64_t reserved_57_59:3; 4724 uint64_t dfm:1; 4725 uint64_t reserved_53_55:3; 4726 uint64_t lmc0:1; 4727 uint64_t srio1:1; 4728 uint64_t srio0:1; 4729 uint64_t pem1:1; 4730 uint64_t pem0:1; 4731 uint64_t ptp:1; 4732 uint64_t agl:1; 4733 uint64_t reserved_41_45:5; 4734 uint64_t dpi_dma:1; 4735 uint64_t reserved_38_39:2; 4736 uint64_t agx1:1; 4737 uint64_t agx0:1; 4738 uint64_t dpi:1; 4739 uint64_t sli:1; 4740 uint64_t usb:1; 4741 uint64_t dfa:1; 4742 uint64_t key:1; 4743 uint64_t rad:1; 4744 uint64_t tim:1; 4745 uint64_t zip:1; 4746 uint64_t pko:1; 4747 uint64_t pip:1; 4748 uint64_t ipd:1; 4749 uint64_t l2c:1; 4750 uint64_t pow:1; 4751 uint64_t fpa:1; 4752 uint64_t iob:1; 4753 uint64_t mio:1; 4754 uint64_t nand:1; 4755 uint64_t mii1:1; 4756 uint64_t usb1:1; 4757 uint64_t uart2:1; 4758 uint64_t wdog:16; 4759 #else 4760 uint64_t wdog:16; 4761 uint64_t uart2:1; 4762 uint64_t usb1:1; 4763 uint64_t mii1:1; 4764 uint64_t nand:1; 4765 uint64_t mio:1; 4766 uint64_t iob:1; 4767 uint64_t fpa:1; 4768 uint64_t pow:1; 4769 uint64_t l2c:1; 4770 uint64_t ipd:1; 4771 uint64_t pip:1; 4772 uint64_t pko:1; 4773 uint64_t zip:1; 4774 uint64_t tim:1; 4775 uint64_t rad:1; 4776 uint64_t key:1; 4777 uint64_t dfa:1; 4778 uint64_t usb:1; 4779 uint64_t sli:1; 4780 uint64_t dpi:1; 4781 uint64_t agx0:1; 4782 uint64_t agx1:1; 4783 uint64_t reserved_38_39:2; 4784 uint64_t dpi_dma:1; 4785 uint64_t reserved_41_45:5; 4786 uint64_t agl:1; 4787 uint64_t ptp:1; 4788 uint64_t pem0:1; 4789 uint64_t pem1:1; 4790 uint64_t srio0:1; 4791 uint64_t srio1:1; 4792 uint64_t lmc0:1; 4793 uint64_t reserved_53_55:3; 4794 uint64_t dfm:1; 4795 uint64_t reserved_57_59:3; 4796 uint64_t srio2:1; 4797 uint64_t srio3:1; 4798 uint64_t reserved_62_62:1; 4799 uint64_t rst:1; 4800 #endif 4801 } s; 4802 struct cvmx_ciu_intx_en4_1_cn50xx { 4803 #ifdef __BIG_ENDIAN_BITFIELD 4804 uint64_t reserved_2_63:62; 4805 uint64_t wdog:2; 4806 #else 4807 uint64_t wdog:2; 4808 uint64_t reserved_2_63:62; 4809 #endif 4810 } cn50xx; 4811 struct cvmx_ciu_intx_en4_1_cn52xx { 4812 #ifdef __BIG_ENDIAN_BITFIELD 4813 uint64_t reserved_20_63:44; 4814 uint64_t nand:1; 4815 uint64_t mii1:1; 4816 uint64_t usb1:1; 4817 uint64_t uart2:1; 4818 uint64_t reserved_4_15:12; 4819 uint64_t wdog:4; 4820 #else 4821 uint64_t wdog:4; 4822 uint64_t reserved_4_15:12; 4823 uint64_t uart2:1; 4824 uint64_t usb1:1; 4825 uint64_t mii1:1; 4826 uint64_t nand:1; 4827 uint64_t reserved_20_63:44; 4828 #endif 4829 } cn52xx; 4830 struct cvmx_ciu_intx_en4_1_cn52xxp1 { 4831 #ifdef __BIG_ENDIAN_BITFIELD 4832 uint64_t reserved_19_63:45; 4833 uint64_t mii1:1; 4834 uint64_t usb1:1; 4835 uint64_t uart2:1; 4836 uint64_t reserved_4_15:12; 4837 uint64_t wdog:4; 4838 #else 4839 uint64_t wdog:4; 4840 uint64_t reserved_4_15:12; 4841 uint64_t uart2:1; 4842 uint64_t usb1:1; 4843 uint64_t mii1:1; 4844 uint64_t reserved_19_63:45; 4845 #endif 4846 } cn52xxp1; 4847 struct cvmx_ciu_intx_en4_1_cn56xx { 4848 #ifdef __BIG_ENDIAN_BITFIELD 4849 uint64_t reserved_12_63:52; 4850 uint64_t wdog:12; 4851 #else 4852 uint64_t wdog:12; 4853 uint64_t reserved_12_63:52; 4854 #endif 4855 } cn56xx; 4856 struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; 4857 struct cvmx_ciu_intx_en4_1_cn58xx { 4858 #ifdef __BIG_ENDIAN_BITFIELD 4859 uint64_t reserved_16_63:48; 4860 uint64_t wdog:16; 4861 #else 4862 uint64_t wdog:16; 4863 uint64_t reserved_16_63:48; 4864 #endif 4865 } cn58xx; 4866 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; 4867 struct cvmx_ciu_intx_en4_1_cn61xx { 4868 #ifdef __BIG_ENDIAN_BITFIELD 4869 uint64_t rst:1; 4870 uint64_t reserved_53_62:10; 4871 uint64_t lmc0:1; 4872 uint64_t reserved_50_51:2; 4873 uint64_t pem1:1; 4874 uint64_t pem0:1; 4875 uint64_t ptp:1; 4876 uint64_t agl:1; 4877 uint64_t reserved_41_45:5; 4878 uint64_t dpi_dma:1; 4879 uint64_t reserved_38_39:2; 4880 uint64_t agx1:1; 4881 uint64_t agx0:1; 4882 uint64_t dpi:1; 4883 uint64_t sli:1; 4884 uint64_t usb:1; 4885 uint64_t dfa:1; 4886 uint64_t key:1; 4887 uint64_t rad:1; 4888 uint64_t tim:1; 4889 uint64_t zip:1; 4890 uint64_t pko:1; 4891 uint64_t pip:1; 4892 uint64_t ipd:1; 4893 uint64_t l2c:1; 4894 uint64_t pow:1; 4895 uint64_t fpa:1; 4896 uint64_t iob:1; 4897 uint64_t mio:1; 4898 uint64_t nand:1; 4899 uint64_t mii1:1; 4900 uint64_t reserved_4_17:14; 4901 uint64_t wdog:4; 4902 #else 4903 uint64_t wdog:4; 4904 uint64_t reserved_4_17:14; 4905 uint64_t mii1:1; 4906 uint64_t nand:1; 4907 uint64_t mio:1; 4908 uint64_t iob:1; 4909 uint64_t fpa:1; 4910 uint64_t pow:1; 4911 uint64_t l2c:1; 4912 uint64_t ipd:1; 4913 uint64_t pip:1; 4914 uint64_t pko:1; 4915 uint64_t zip:1; 4916 uint64_t tim:1; 4917 uint64_t rad:1; 4918 uint64_t key:1; 4919 uint64_t dfa:1; 4920 uint64_t usb:1; 4921 uint64_t sli:1; 4922 uint64_t dpi:1; 4923 uint64_t agx0:1; 4924 uint64_t agx1:1; 4925 uint64_t reserved_38_39:2; 4926 uint64_t dpi_dma:1; 4927 uint64_t reserved_41_45:5; 4928 uint64_t agl:1; 4929 uint64_t ptp:1; 4930 uint64_t pem0:1; 4931 uint64_t pem1:1; 4932 uint64_t reserved_50_51:2; 4933 uint64_t lmc0:1; 4934 uint64_t reserved_53_62:10; 4935 uint64_t rst:1; 4936 #endif 4937 } cn61xx; 4938 struct cvmx_ciu_intx_en4_1_cn63xx { 4939 #ifdef __BIG_ENDIAN_BITFIELD 4940 uint64_t rst:1; 4941 uint64_t reserved_57_62:6; 4942 uint64_t dfm:1; 4943 uint64_t reserved_53_55:3; 4944 uint64_t lmc0:1; 4945 uint64_t srio1:1; 4946 uint64_t srio0:1; 4947 uint64_t pem1:1; 4948 uint64_t pem0:1; 4949 uint64_t ptp:1; 4950 uint64_t agl:1; 4951 uint64_t reserved_37_45:9; 4952 uint64_t agx0:1; 4953 uint64_t dpi:1; 4954 uint64_t sli:1; 4955 uint64_t usb:1; 4956 uint64_t dfa:1; 4957 uint64_t key:1; 4958 uint64_t rad:1; 4959 uint64_t tim:1; 4960 uint64_t zip:1; 4961 uint64_t pko:1; 4962 uint64_t pip:1; 4963 uint64_t ipd:1; 4964 uint64_t l2c:1; 4965 uint64_t pow:1; 4966 uint64_t fpa:1; 4967 uint64_t iob:1; 4968 uint64_t mio:1; 4969 uint64_t nand:1; 4970 uint64_t mii1:1; 4971 uint64_t reserved_6_17:12; 4972 uint64_t wdog:6; 4973 #else 4974 uint64_t wdog:6; 4975 uint64_t reserved_6_17:12; 4976 uint64_t mii1:1; 4977 uint64_t nand:1; 4978 uint64_t mio:1; 4979 uint64_t iob:1; 4980 uint64_t fpa:1; 4981 uint64_t pow:1; 4982 uint64_t l2c:1; 4983 uint64_t ipd:1; 4984 uint64_t pip:1; 4985 uint64_t pko:1; 4986 uint64_t zip:1; 4987 uint64_t tim:1; 4988 uint64_t rad:1; 4989 uint64_t key:1; 4990 uint64_t dfa:1; 4991 uint64_t usb:1; 4992 uint64_t sli:1; 4993 uint64_t dpi:1; 4994 uint64_t agx0:1; 4995 uint64_t reserved_37_45:9; 4996 uint64_t agl:1; 4997 uint64_t ptp:1; 4998 uint64_t pem0:1; 4999 uint64_t pem1:1; 5000 uint64_t srio0:1; 5001 uint64_t srio1:1; 5002 uint64_t lmc0:1; 5003 uint64_t reserved_53_55:3; 5004 uint64_t dfm:1; 5005 uint64_t reserved_57_62:6; 5006 uint64_t rst:1; 5007 #endif 5008 } cn63xx; 5009 struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1; 5010 struct cvmx_ciu_intx_en4_1_cn66xx { 5011 #ifdef __BIG_ENDIAN_BITFIELD 5012 uint64_t rst:1; 5013 uint64_t reserved_62_62:1; 5014 uint64_t srio3:1; 5015 uint64_t srio2:1; 5016 uint64_t reserved_57_59:3; 5017 uint64_t dfm:1; 5018 uint64_t reserved_53_55:3; 5019 uint64_t lmc0:1; 5020 uint64_t reserved_51_51:1; 5021 uint64_t srio0:1; 5022 uint64_t pem1:1; 5023 uint64_t pem0:1; 5024 uint64_t ptp:1; 5025 uint64_t agl:1; 5026 uint64_t reserved_38_45:8; 5027 uint64_t agx1:1; 5028 uint64_t agx0:1; 5029 uint64_t dpi:1; 5030 uint64_t sli:1; 5031 uint64_t usb:1; 5032 uint64_t dfa:1; 5033 uint64_t key:1; 5034 uint64_t rad:1; 5035 uint64_t tim:1; 5036 uint64_t zip:1; 5037 uint64_t pko:1; 5038 uint64_t pip:1; 5039 uint64_t ipd:1; 5040 uint64_t l2c:1; 5041 uint64_t pow:1; 5042 uint64_t fpa:1; 5043 uint64_t iob:1; 5044 uint64_t mio:1; 5045 uint64_t nand:1; 5046 uint64_t mii1:1; 5047 uint64_t reserved_10_17:8; 5048 uint64_t wdog:10; 5049 #else 5050 uint64_t wdog:10; 5051 uint64_t reserved_10_17:8; 5052 uint64_t mii1:1; 5053 uint64_t nand:1; 5054 uint64_t mio:1; 5055 uint64_t iob:1; 5056 uint64_t fpa:1; 5057 uint64_t pow:1; 5058 uint64_t l2c:1; 5059 uint64_t ipd:1; 5060 uint64_t pip:1; 5061 uint64_t pko:1; 5062 uint64_t zip:1; 5063 uint64_t tim:1; 5064 uint64_t rad:1; 5065 uint64_t key:1; 5066 uint64_t dfa:1; 5067 uint64_t usb:1; 5068 uint64_t sli:1; 5069 uint64_t dpi:1; 5070 uint64_t agx0:1; 5071 uint64_t agx1:1; 5072 uint64_t reserved_38_45:8; 5073 uint64_t agl:1; 5074 uint64_t ptp:1; 5075 uint64_t pem0:1; 5076 uint64_t pem1:1; 5077 uint64_t srio0:1; 5078 uint64_t reserved_51_51:1; 5079 uint64_t lmc0:1; 5080 uint64_t reserved_53_55:3; 5081 uint64_t dfm:1; 5082 uint64_t reserved_57_59:3; 5083 uint64_t srio2:1; 5084 uint64_t srio3:1; 5085 uint64_t reserved_62_62:1; 5086 uint64_t rst:1; 5087 #endif 5088 } cn66xx; 5089 struct cvmx_ciu_intx_en4_1_cnf71xx { 5090 #ifdef __BIG_ENDIAN_BITFIELD 5091 uint64_t rst:1; 5092 uint64_t reserved_53_62:10; 5093 uint64_t lmc0:1; 5094 uint64_t reserved_50_51:2; 5095 uint64_t pem1:1; 5096 uint64_t pem0:1; 5097 uint64_t ptp:1; 5098 uint64_t reserved_41_46:6; 5099 uint64_t dpi_dma:1; 5100 uint64_t reserved_37_39:3; 5101 uint64_t agx0:1; 5102 uint64_t dpi:1; 5103 uint64_t sli:1; 5104 uint64_t usb:1; 5105 uint64_t reserved_32_32:1; 5106 uint64_t key:1; 5107 uint64_t rad:1; 5108 uint64_t tim:1; 5109 uint64_t reserved_28_28:1; 5110 uint64_t pko:1; 5111 uint64_t pip:1; 5112 uint64_t ipd:1; 5113 uint64_t l2c:1; 5114 uint64_t pow:1; 5115 uint64_t fpa:1; 5116 uint64_t iob:1; 5117 uint64_t mio:1; 5118 uint64_t nand:1; 5119 uint64_t reserved_4_18:15; 5120 uint64_t wdog:4; 5121 #else 5122 uint64_t wdog:4; 5123 uint64_t reserved_4_18:15; 5124 uint64_t nand:1; 5125 uint64_t mio:1; 5126 uint64_t iob:1; 5127 uint64_t fpa:1; 5128 uint64_t pow:1; 5129 uint64_t l2c:1; 5130 uint64_t ipd:1; 5131 uint64_t pip:1; 5132 uint64_t pko:1; 5133 uint64_t reserved_28_28:1; 5134 uint64_t tim:1; 5135 uint64_t rad:1; 5136 uint64_t key:1; 5137 uint64_t reserved_32_32:1; 5138 uint64_t usb:1; 5139 uint64_t sli:1; 5140 uint64_t dpi:1; 5141 uint64_t agx0:1; 5142 uint64_t reserved_37_39:3; 5143 uint64_t dpi_dma:1; 5144 uint64_t reserved_41_46:6; 5145 uint64_t ptp:1; 5146 uint64_t pem0:1; 5147 uint64_t pem1:1; 5148 uint64_t reserved_50_51:2; 5149 uint64_t lmc0:1; 5150 uint64_t reserved_53_62:10; 5151 uint64_t rst:1; 5152 #endif 5153 } cnf71xx; 5154 }; 5155 5156 union cvmx_ciu_intx_en4_1_w1c { 5157 uint64_t u64; 5158 struct cvmx_ciu_intx_en4_1_w1c_s { 5159 #ifdef __BIG_ENDIAN_BITFIELD 5160 uint64_t rst:1; 5161 uint64_t reserved_62_62:1; 5162 uint64_t srio3:1; 5163 uint64_t srio2:1; 5164 uint64_t reserved_57_59:3; 5165 uint64_t dfm:1; 5166 uint64_t reserved_53_55:3; 5167 uint64_t lmc0:1; 5168 uint64_t srio1:1; 5169 uint64_t srio0:1; 5170 uint64_t pem1:1; 5171 uint64_t pem0:1; 5172 uint64_t ptp:1; 5173 uint64_t agl:1; 5174 uint64_t reserved_41_45:5; 5175 uint64_t dpi_dma:1; 5176 uint64_t reserved_38_39:2; 5177 uint64_t agx1:1; 5178 uint64_t agx0:1; 5179 uint64_t dpi:1; 5180 uint64_t sli:1; 5181 uint64_t usb:1; 5182 uint64_t dfa:1; 5183 uint64_t key:1; 5184 uint64_t rad:1; 5185 uint64_t tim:1; 5186 uint64_t zip:1; 5187 uint64_t pko:1; 5188 uint64_t pip:1; 5189 uint64_t ipd:1; 5190 uint64_t l2c:1; 5191 uint64_t pow:1; 5192 uint64_t fpa:1; 5193 uint64_t iob:1; 5194 uint64_t mio:1; 5195 uint64_t nand:1; 5196 uint64_t mii1:1; 5197 uint64_t usb1:1; 5198 uint64_t uart2:1; 5199 uint64_t wdog:16; 5200 #else 5201 uint64_t wdog:16; 5202 uint64_t uart2:1; 5203 uint64_t usb1:1; 5204 uint64_t mii1:1; 5205 uint64_t nand:1; 5206 uint64_t mio:1; 5207 uint64_t iob:1; 5208 uint64_t fpa:1; 5209 uint64_t pow:1; 5210 uint64_t l2c:1; 5211 uint64_t ipd:1; 5212 uint64_t pip:1; 5213 uint64_t pko:1; 5214 uint64_t zip:1; 5215 uint64_t tim:1; 5216 uint64_t rad:1; 5217 uint64_t key:1; 5218 uint64_t dfa:1; 5219 uint64_t usb:1; 5220 uint64_t sli:1; 5221 uint64_t dpi:1; 5222 uint64_t agx0:1; 5223 uint64_t agx1:1; 5224 uint64_t reserved_38_39:2; 5225 uint64_t dpi_dma:1; 5226 uint64_t reserved_41_45:5; 5227 uint64_t agl:1; 5228 uint64_t ptp:1; 5229 uint64_t pem0:1; 5230 uint64_t pem1:1; 5231 uint64_t srio0:1; 5232 uint64_t srio1:1; 5233 uint64_t lmc0:1; 5234 uint64_t reserved_53_55:3; 5235 uint64_t dfm:1; 5236 uint64_t reserved_57_59:3; 5237 uint64_t srio2:1; 5238 uint64_t srio3:1; 5239 uint64_t reserved_62_62:1; 5240 uint64_t rst:1; 5241 #endif 5242 } s; 5243 struct cvmx_ciu_intx_en4_1_w1c_cn52xx { 5244 #ifdef __BIG_ENDIAN_BITFIELD 5245 uint64_t reserved_20_63:44; 5246 uint64_t nand:1; 5247 uint64_t mii1:1; 5248 uint64_t usb1:1; 5249 uint64_t uart2:1; 5250 uint64_t reserved_4_15:12; 5251 uint64_t wdog:4; 5252 #else 5253 uint64_t wdog:4; 5254 uint64_t reserved_4_15:12; 5255 uint64_t uart2:1; 5256 uint64_t usb1:1; 5257 uint64_t mii1:1; 5258 uint64_t nand:1; 5259 uint64_t reserved_20_63:44; 5260 #endif 5261 } cn52xx; 5262 struct cvmx_ciu_intx_en4_1_w1c_cn56xx { 5263 #ifdef __BIG_ENDIAN_BITFIELD 5264 uint64_t reserved_12_63:52; 5265 uint64_t wdog:12; 5266 #else 5267 uint64_t wdog:12; 5268 uint64_t reserved_12_63:52; 5269 #endif 5270 } cn56xx; 5271 struct cvmx_ciu_intx_en4_1_w1c_cn58xx { 5272 #ifdef __BIG_ENDIAN_BITFIELD 5273 uint64_t reserved_16_63:48; 5274 uint64_t wdog:16; 5275 #else 5276 uint64_t wdog:16; 5277 uint64_t reserved_16_63:48; 5278 #endif 5279 } cn58xx; 5280 struct cvmx_ciu_intx_en4_1_w1c_cn61xx { 5281 #ifdef __BIG_ENDIAN_BITFIELD 5282 uint64_t rst:1; 5283 uint64_t reserved_53_62:10; 5284 uint64_t lmc0:1; 5285 uint64_t reserved_50_51:2; 5286 uint64_t pem1:1; 5287 uint64_t pem0:1; 5288 uint64_t ptp:1; 5289 uint64_t agl:1; 5290 uint64_t reserved_41_45:5; 5291 uint64_t dpi_dma:1; 5292 uint64_t reserved_38_39:2; 5293 uint64_t agx1:1; 5294 uint64_t agx0:1; 5295 uint64_t dpi:1; 5296 uint64_t sli:1; 5297 uint64_t usb:1; 5298 uint64_t dfa:1; 5299 uint64_t key:1; 5300 uint64_t rad:1; 5301 uint64_t tim:1; 5302 uint64_t zip:1; 5303 uint64_t pko:1; 5304 uint64_t pip:1; 5305 uint64_t ipd:1; 5306 uint64_t l2c:1; 5307 uint64_t pow:1; 5308 uint64_t fpa:1; 5309 uint64_t iob:1; 5310 uint64_t mio:1; 5311 uint64_t nand:1; 5312 uint64_t mii1:1; 5313 uint64_t reserved_4_17:14; 5314 uint64_t wdog:4; 5315 #else 5316 uint64_t wdog:4; 5317 uint64_t reserved_4_17:14; 5318 uint64_t mii1:1; 5319 uint64_t nand:1; 5320 uint64_t mio:1; 5321 uint64_t iob:1; 5322 uint64_t fpa:1; 5323 uint64_t pow:1; 5324 uint64_t l2c:1; 5325 uint64_t ipd:1; 5326 uint64_t pip:1; 5327 uint64_t pko:1; 5328 uint64_t zip:1; 5329 uint64_t tim:1; 5330 uint64_t rad:1; 5331 uint64_t key:1; 5332 uint64_t dfa:1; 5333 uint64_t usb:1; 5334 uint64_t sli:1; 5335 uint64_t dpi:1; 5336 uint64_t agx0:1; 5337 uint64_t agx1:1; 5338 uint64_t reserved_38_39:2; 5339 uint64_t dpi_dma:1; 5340 uint64_t reserved_41_45:5; 5341 uint64_t agl:1; 5342 uint64_t ptp:1; 5343 uint64_t pem0:1; 5344 uint64_t pem1:1; 5345 uint64_t reserved_50_51:2; 5346 uint64_t lmc0:1; 5347 uint64_t reserved_53_62:10; 5348 uint64_t rst:1; 5349 #endif 5350 } cn61xx; 5351 struct cvmx_ciu_intx_en4_1_w1c_cn63xx { 5352 #ifdef __BIG_ENDIAN_BITFIELD 5353 uint64_t rst:1; 5354 uint64_t reserved_57_62:6; 5355 uint64_t dfm:1; 5356 uint64_t reserved_53_55:3; 5357 uint64_t lmc0:1; 5358 uint64_t srio1:1; 5359 uint64_t srio0:1; 5360 uint64_t pem1:1; 5361 uint64_t pem0:1; 5362 uint64_t ptp:1; 5363 uint64_t agl:1; 5364 uint64_t reserved_37_45:9; 5365 uint64_t agx0:1; 5366 uint64_t dpi:1; 5367 uint64_t sli:1; 5368 uint64_t usb:1; 5369 uint64_t dfa:1; 5370 uint64_t key:1; 5371 uint64_t rad:1; 5372 uint64_t tim:1; 5373 uint64_t zip:1; 5374 uint64_t pko:1; 5375 uint64_t pip:1; 5376 uint64_t ipd:1; 5377 uint64_t l2c:1; 5378 uint64_t pow:1; 5379 uint64_t fpa:1; 5380 uint64_t iob:1; 5381 uint64_t mio:1; 5382 uint64_t nand:1; 5383 uint64_t mii1:1; 5384 uint64_t reserved_6_17:12; 5385 uint64_t wdog:6; 5386 #else 5387 uint64_t wdog:6; 5388 uint64_t reserved_6_17:12; 5389 uint64_t mii1:1; 5390 uint64_t nand:1; 5391 uint64_t mio:1; 5392 uint64_t iob:1; 5393 uint64_t fpa:1; 5394 uint64_t pow:1; 5395 uint64_t l2c:1; 5396 uint64_t ipd:1; 5397 uint64_t pip:1; 5398 uint64_t pko:1; 5399 uint64_t zip:1; 5400 uint64_t tim:1; 5401 uint64_t rad:1; 5402 uint64_t key:1; 5403 uint64_t dfa:1; 5404 uint64_t usb:1; 5405 uint64_t sli:1; 5406 uint64_t dpi:1; 5407 uint64_t agx0:1; 5408 uint64_t reserved_37_45:9; 5409 uint64_t agl:1; 5410 uint64_t ptp:1; 5411 uint64_t pem0:1; 5412 uint64_t pem1:1; 5413 uint64_t srio0:1; 5414 uint64_t srio1:1; 5415 uint64_t lmc0:1; 5416 uint64_t reserved_53_55:3; 5417 uint64_t dfm:1; 5418 uint64_t reserved_57_62:6; 5419 uint64_t rst:1; 5420 #endif 5421 } cn63xx; 5422 struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1; 5423 struct cvmx_ciu_intx_en4_1_w1c_cn66xx { 5424 #ifdef __BIG_ENDIAN_BITFIELD 5425 uint64_t rst:1; 5426 uint64_t reserved_62_62:1; 5427 uint64_t srio3:1; 5428 uint64_t srio2:1; 5429 uint64_t reserved_57_59:3; 5430 uint64_t dfm:1; 5431 uint64_t reserved_53_55:3; 5432 uint64_t lmc0:1; 5433 uint64_t reserved_51_51:1; 5434 uint64_t srio0:1; 5435 uint64_t pem1:1; 5436 uint64_t pem0:1; 5437 uint64_t ptp:1; 5438 uint64_t agl:1; 5439 uint64_t reserved_38_45:8; 5440 uint64_t agx1:1; 5441 uint64_t agx0:1; 5442 uint64_t dpi:1; 5443 uint64_t sli:1; 5444 uint64_t usb:1; 5445 uint64_t dfa:1; 5446 uint64_t key:1; 5447 uint64_t rad:1; 5448 uint64_t tim:1; 5449 uint64_t zip:1; 5450 uint64_t pko:1; 5451 uint64_t pip:1; 5452 uint64_t ipd:1; 5453 uint64_t l2c:1; 5454 uint64_t pow:1; 5455 uint64_t fpa:1; 5456 uint64_t iob:1; 5457 uint64_t mio:1; 5458 uint64_t nand:1; 5459 uint64_t mii1:1; 5460 uint64_t reserved_10_17:8; 5461 uint64_t wdog:10; 5462 #else 5463 uint64_t wdog:10; 5464 uint64_t reserved_10_17:8; 5465 uint64_t mii1:1; 5466 uint64_t nand:1; 5467 uint64_t mio:1; 5468 uint64_t iob:1; 5469 uint64_t fpa:1; 5470 uint64_t pow:1; 5471 uint64_t l2c:1; 5472 uint64_t ipd:1; 5473 uint64_t pip:1; 5474 uint64_t pko:1; 5475 uint64_t zip:1; 5476 uint64_t tim:1; 5477 uint64_t rad:1; 5478 uint64_t key:1; 5479 uint64_t dfa:1; 5480 uint64_t usb:1; 5481 uint64_t sli:1; 5482 uint64_t dpi:1; 5483 uint64_t agx0:1; 5484 uint64_t agx1:1; 5485 uint64_t reserved_38_45:8; 5486 uint64_t agl:1; 5487 uint64_t ptp:1; 5488 uint64_t pem0:1; 5489 uint64_t pem1:1; 5490 uint64_t srio0:1; 5491 uint64_t reserved_51_51:1; 5492 uint64_t lmc0:1; 5493 uint64_t reserved_53_55:3; 5494 uint64_t dfm:1; 5495 uint64_t reserved_57_59:3; 5496 uint64_t srio2:1; 5497 uint64_t srio3:1; 5498 uint64_t reserved_62_62:1; 5499 uint64_t rst:1; 5500 #endif 5501 } cn66xx; 5502 struct cvmx_ciu_intx_en4_1_w1c_cnf71xx { 5503 #ifdef __BIG_ENDIAN_BITFIELD 5504 uint64_t rst:1; 5505 uint64_t reserved_53_62:10; 5506 uint64_t lmc0:1; 5507 uint64_t reserved_50_51:2; 5508 uint64_t pem1:1; 5509 uint64_t pem0:1; 5510 uint64_t ptp:1; 5511 uint64_t reserved_41_46:6; 5512 uint64_t dpi_dma:1; 5513 uint64_t reserved_37_39:3; 5514 uint64_t agx0:1; 5515 uint64_t dpi:1; 5516 uint64_t sli:1; 5517 uint64_t usb:1; 5518 uint64_t reserved_32_32:1; 5519 uint64_t key:1; 5520 uint64_t rad:1; 5521 uint64_t tim:1; 5522 uint64_t reserved_28_28:1; 5523 uint64_t pko:1; 5524 uint64_t pip:1; 5525 uint64_t ipd:1; 5526 uint64_t l2c:1; 5527 uint64_t pow:1; 5528 uint64_t fpa:1; 5529 uint64_t iob:1; 5530 uint64_t mio:1; 5531 uint64_t nand:1; 5532 uint64_t reserved_4_18:15; 5533 uint64_t wdog:4; 5534 #else 5535 uint64_t wdog:4; 5536 uint64_t reserved_4_18:15; 5537 uint64_t nand:1; 5538 uint64_t mio:1; 5539 uint64_t iob:1; 5540 uint64_t fpa:1; 5541 uint64_t pow:1; 5542 uint64_t l2c:1; 5543 uint64_t ipd:1; 5544 uint64_t pip:1; 5545 uint64_t pko:1; 5546 uint64_t reserved_28_28:1; 5547 uint64_t tim:1; 5548 uint64_t rad:1; 5549 uint64_t key:1; 5550 uint64_t reserved_32_32:1; 5551 uint64_t usb:1; 5552 uint64_t sli:1; 5553 uint64_t dpi:1; 5554 uint64_t agx0:1; 5555 uint64_t reserved_37_39:3; 5556 uint64_t dpi_dma:1; 5557 uint64_t reserved_41_46:6; 5558 uint64_t ptp:1; 5559 uint64_t pem0:1; 5560 uint64_t pem1:1; 5561 uint64_t reserved_50_51:2; 5562 uint64_t lmc0:1; 5563 uint64_t reserved_53_62:10; 5564 uint64_t rst:1; 5565 #endif 5566 } cnf71xx; 5567 }; 5568 5569 union cvmx_ciu_intx_en4_1_w1s { 5570 uint64_t u64; 5571 struct cvmx_ciu_intx_en4_1_w1s_s { 5572 #ifdef __BIG_ENDIAN_BITFIELD 5573 uint64_t rst:1; 5574 uint64_t reserved_62_62:1; 5575 uint64_t srio3:1; 5576 uint64_t srio2:1; 5577 uint64_t reserved_57_59:3; 5578 uint64_t dfm:1; 5579 uint64_t reserved_53_55:3; 5580 uint64_t lmc0:1; 5581 uint64_t srio1:1; 5582 uint64_t srio0:1; 5583 uint64_t pem1:1; 5584 uint64_t pem0:1; 5585 uint64_t ptp:1; 5586 uint64_t agl:1; 5587 uint64_t reserved_41_45:5; 5588 uint64_t dpi_dma:1; 5589 uint64_t reserved_38_39:2; 5590 uint64_t agx1:1; 5591 uint64_t agx0:1; 5592 uint64_t dpi:1; 5593 uint64_t sli:1; 5594 uint64_t usb:1; 5595 uint64_t dfa:1; 5596 uint64_t key:1; 5597 uint64_t rad:1; 5598 uint64_t tim:1; 5599 uint64_t zip:1; 5600 uint64_t pko:1; 5601 uint64_t pip:1; 5602 uint64_t ipd:1; 5603 uint64_t l2c:1; 5604 uint64_t pow:1; 5605 uint64_t fpa:1; 5606 uint64_t iob:1; 5607 uint64_t mio:1; 5608 uint64_t nand:1; 5609 uint64_t mii1:1; 5610 uint64_t usb1:1; 5611 uint64_t uart2:1; 5612 uint64_t wdog:16; 5613 #else 5614 uint64_t wdog:16; 5615 uint64_t uart2:1; 5616 uint64_t usb1:1; 5617 uint64_t mii1:1; 5618 uint64_t nand:1; 5619 uint64_t mio:1; 5620 uint64_t iob:1; 5621 uint64_t fpa:1; 5622 uint64_t pow:1; 5623 uint64_t l2c:1; 5624 uint64_t ipd:1; 5625 uint64_t pip:1; 5626 uint64_t pko:1; 5627 uint64_t zip:1; 5628 uint64_t tim:1; 5629 uint64_t rad:1; 5630 uint64_t key:1; 5631 uint64_t dfa:1; 5632 uint64_t usb:1; 5633 uint64_t sli:1; 5634 uint64_t dpi:1; 5635 uint64_t agx0:1; 5636 uint64_t agx1:1; 5637 uint64_t reserved_38_39:2; 5638 uint64_t dpi_dma:1; 5639 uint64_t reserved_41_45:5; 5640 uint64_t agl:1; 5641 uint64_t ptp:1; 5642 uint64_t pem0:1; 5643 uint64_t pem1:1; 5644 uint64_t srio0:1; 5645 uint64_t srio1:1; 5646 uint64_t lmc0:1; 5647 uint64_t reserved_53_55:3; 5648 uint64_t dfm:1; 5649 uint64_t reserved_57_59:3; 5650 uint64_t srio2:1; 5651 uint64_t srio3:1; 5652 uint64_t reserved_62_62:1; 5653 uint64_t rst:1; 5654 #endif 5655 } s; 5656 struct cvmx_ciu_intx_en4_1_w1s_cn52xx { 5657 #ifdef __BIG_ENDIAN_BITFIELD 5658 uint64_t reserved_20_63:44; 5659 uint64_t nand:1; 5660 uint64_t mii1:1; 5661 uint64_t usb1:1; 5662 uint64_t uart2:1; 5663 uint64_t reserved_4_15:12; 5664 uint64_t wdog:4; 5665 #else 5666 uint64_t wdog:4; 5667 uint64_t reserved_4_15:12; 5668 uint64_t uart2:1; 5669 uint64_t usb1:1; 5670 uint64_t mii1:1; 5671 uint64_t nand:1; 5672 uint64_t reserved_20_63:44; 5673 #endif 5674 } cn52xx; 5675 struct cvmx_ciu_intx_en4_1_w1s_cn56xx { 5676 #ifdef __BIG_ENDIAN_BITFIELD 5677 uint64_t reserved_12_63:52; 5678 uint64_t wdog:12; 5679 #else 5680 uint64_t wdog:12; 5681 uint64_t reserved_12_63:52; 5682 #endif 5683 } cn56xx; 5684 struct cvmx_ciu_intx_en4_1_w1s_cn58xx { 5685 #ifdef __BIG_ENDIAN_BITFIELD 5686 uint64_t reserved_16_63:48; 5687 uint64_t wdog:16; 5688 #else 5689 uint64_t wdog:16; 5690 uint64_t reserved_16_63:48; 5691 #endif 5692 } cn58xx; 5693 struct cvmx_ciu_intx_en4_1_w1s_cn61xx { 5694 #ifdef __BIG_ENDIAN_BITFIELD 5695 uint64_t rst:1; 5696 uint64_t reserved_53_62:10; 5697 uint64_t lmc0:1; 5698 uint64_t reserved_50_51:2; 5699 uint64_t pem1:1; 5700 uint64_t pem0:1; 5701 uint64_t ptp:1; 5702 uint64_t agl:1; 5703 uint64_t reserved_41_45:5; 5704 uint64_t dpi_dma:1; 5705 uint64_t reserved_38_39:2; 5706 uint64_t agx1:1; 5707 uint64_t agx0:1; 5708 uint64_t dpi:1; 5709 uint64_t sli:1; 5710 uint64_t usb:1; 5711 uint64_t dfa:1; 5712 uint64_t key:1; 5713 uint64_t rad:1; 5714 uint64_t tim:1; 5715 uint64_t zip:1; 5716 uint64_t pko:1; 5717 uint64_t pip:1; 5718 uint64_t ipd:1; 5719 uint64_t l2c:1; 5720 uint64_t pow:1; 5721 uint64_t fpa:1; 5722 uint64_t iob:1; 5723 uint64_t mio:1; 5724 uint64_t nand:1; 5725 uint64_t mii1:1; 5726 uint64_t reserved_4_17:14; 5727 uint64_t wdog:4; 5728 #else 5729 uint64_t wdog:4; 5730 uint64_t reserved_4_17:14; 5731 uint64_t mii1:1; 5732 uint64_t nand:1; 5733 uint64_t mio:1; 5734 uint64_t iob:1; 5735 uint64_t fpa:1; 5736 uint64_t pow:1; 5737 uint64_t l2c:1; 5738 uint64_t ipd:1; 5739 uint64_t pip:1; 5740 uint64_t pko:1; 5741 uint64_t zip:1; 5742 uint64_t tim:1; 5743 uint64_t rad:1; 5744 uint64_t key:1; 5745 uint64_t dfa:1; 5746 uint64_t usb:1; 5747 uint64_t sli:1; 5748 uint64_t dpi:1; 5749 uint64_t agx0:1; 5750 uint64_t agx1:1; 5751 uint64_t reserved_38_39:2; 5752 uint64_t dpi_dma:1; 5753 uint64_t reserved_41_45:5; 5754 uint64_t agl:1; 5755 uint64_t ptp:1; 5756 uint64_t pem0:1; 5757 uint64_t pem1:1; 5758 uint64_t reserved_50_51:2; 5759 uint64_t lmc0:1; 5760 uint64_t reserved_53_62:10; 5761 uint64_t rst:1; 5762 #endif 5763 } cn61xx; 5764 struct cvmx_ciu_intx_en4_1_w1s_cn63xx { 5765 #ifdef __BIG_ENDIAN_BITFIELD 5766 uint64_t rst:1; 5767 uint64_t reserved_57_62:6; 5768 uint64_t dfm:1; 5769 uint64_t reserved_53_55:3; 5770 uint64_t lmc0:1; 5771 uint64_t srio1:1; 5772 uint64_t srio0:1; 5773 uint64_t pem1:1; 5774 uint64_t pem0:1; 5775 uint64_t ptp:1; 5776 uint64_t agl:1; 5777 uint64_t reserved_37_45:9; 5778 uint64_t agx0:1; 5779 uint64_t dpi:1; 5780 uint64_t sli:1; 5781 uint64_t usb:1; 5782 uint64_t dfa:1; 5783 uint64_t key:1; 5784 uint64_t rad:1; 5785 uint64_t tim:1; 5786 uint64_t zip:1; 5787 uint64_t pko:1; 5788 uint64_t pip:1; 5789 uint64_t ipd:1; 5790 uint64_t l2c:1; 5791 uint64_t pow:1; 5792 uint64_t fpa:1; 5793 uint64_t iob:1; 5794 uint64_t mio:1; 5795 uint64_t nand:1; 5796 uint64_t mii1:1; 5797 uint64_t reserved_6_17:12; 5798 uint64_t wdog:6; 5799 #else 5800 uint64_t wdog:6; 5801 uint64_t reserved_6_17:12; 5802 uint64_t mii1:1; 5803 uint64_t nand:1; 5804 uint64_t mio:1; 5805 uint64_t iob:1; 5806 uint64_t fpa:1; 5807 uint64_t pow:1; 5808 uint64_t l2c:1; 5809 uint64_t ipd:1; 5810 uint64_t pip:1; 5811 uint64_t pko:1; 5812 uint64_t zip:1; 5813 uint64_t tim:1; 5814 uint64_t rad:1; 5815 uint64_t key:1; 5816 uint64_t dfa:1; 5817 uint64_t usb:1; 5818 uint64_t sli:1; 5819 uint64_t dpi:1; 5820 uint64_t agx0:1; 5821 uint64_t reserved_37_45:9; 5822 uint64_t agl:1; 5823 uint64_t ptp:1; 5824 uint64_t pem0:1; 5825 uint64_t pem1:1; 5826 uint64_t srio0:1; 5827 uint64_t srio1:1; 5828 uint64_t lmc0:1; 5829 uint64_t reserved_53_55:3; 5830 uint64_t dfm:1; 5831 uint64_t reserved_57_62:6; 5832 uint64_t rst:1; 5833 #endif 5834 } cn63xx; 5835 struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1; 5836 struct cvmx_ciu_intx_en4_1_w1s_cn66xx { 5837 #ifdef __BIG_ENDIAN_BITFIELD 5838 uint64_t rst:1; 5839 uint64_t reserved_62_62:1; 5840 uint64_t srio3:1; 5841 uint64_t srio2:1; 5842 uint64_t reserved_57_59:3; 5843 uint64_t dfm:1; 5844 uint64_t reserved_53_55:3; 5845 uint64_t lmc0:1; 5846 uint64_t reserved_51_51:1; 5847 uint64_t srio0:1; 5848 uint64_t pem1:1; 5849 uint64_t pem0:1; 5850 uint64_t ptp:1; 5851 uint64_t agl:1; 5852 uint64_t reserved_38_45:8; 5853 uint64_t agx1:1; 5854 uint64_t agx0:1; 5855 uint64_t dpi:1; 5856 uint64_t sli:1; 5857 uint64_t usb:1; 5858 uint64_t dfa:1; 5859 uint64_t key:1; 5860 uint64_t rad:1; 5861 uint64_t tim:1; 5862 uint64_t zip:1; 5863 uint64_t pko:1; 5864 uint64_t pip:1; 5865 uint64_t ipd:1; 5866 uint64_t l2c:1; 5867 uint64_t pow:1; 5868 uint64_t fpa:1; 5869 uint64_t iob:1; 5870 uint64_t mio:1; 5871 uint64_t nand:1; 5872 uint64_t mii1:1; 5873 uint64_t reserved_10_17:8; 5874 uint64_t wdog:10; 5875 #else 5876 uint64_t wdog:10; 5877 uint64_t reserved_10_17:8; 5878 uint64_t mii1:1; 5879 uint64_t nand:1; 5880 uint64_t mio:1; 5881 uint64_t iob:1; 5882 uint64_t fpa:1; 5883 uint64_t pow:1; 5884 uint64_t l2c:1; 5885 uint64_t ipd:1; 5886 uint64_t pip:1; 5887 uint64_t pko:1; 5888 uint64_t zip:1; 5889 uint64_t tim:1; 5890 uint64_t rad:1; 5891 uint64_t key:1; 5892 uint64_t dfa:1; 5893 uint64_t usb:1; 5894 uint64_t sli:1; 5895 uint64_t dpi:1; 5896 uint64_t agx0:1; 5897 uint64_t agx1:1; 5898 uint64_t reserved_38_45:8; 5899 uint64_t agl:1; 5900 uint64_t ptp:1; 5901 uint64_t pem0:1; 5902 uint64_t pem1:1; 5903 uint64_t srio0:1; 5904 uint64_t reserved_51_51:1; 5905 uint64_t lmc0:1; 5906 uint64_t reserved_53_55:3; 5907 uint64_t dfm:1; 5908 uint64_t reserved_57_59:3; 5909 uint64_t srio2:1; 5910 uint64_t srio3:1; 5911 uint64_t reserved_62_62:1; 5912 uint64_t rst:1; 5913 #endif 5914 } cn66xx; 5915 struct cvmx_ciu_intx_en4_1_w1s_cnf71xx { 5916 #ifdef __BIG_ENDIAN_BITFIELD 5917 uint64_t rst:1; 5918 uint64_t reserved_53_62:10; 5919 uint64_t lmc0:1; 5920 uint64_t reserved_50_51:2; 5921 uint64_t pem1:1; 5922 uint64_t pem0:1; 5923 uint64_t ptp:1; 5924 uint64_t reserved_41_46:6; 5925 uint64_t dpi_dma:1; 5926 uint64_t reserved_37_39:3; 5927 uint64_t agx0:1; 5928 uint64_t dpi:1; 5929 uint64_t sli:1; 5930 uint64_t usb:1; 5931 uint64_t reserved_32_32:1; 5932 uint64_t key:1; 5933 uint64_t rad:1; 5934 uint64_t tim:1; 5935 uint64_t reserved_28_28:1; 5936 uint64_t pko:1; 5937 uint64_t pip:1; 5938 uint64_t ipd:1; 5939 uint64_t l2c:1; 5940 uint64_t pow:1; 5941 uint64_t fpa:1; 5942 uint64_t iob:1; 5943 uint64_t mio:1; 5944 uint64_t nand:1; 5945 uint64_t reserved_4_18:15; 5946 uint64_t wdog:4; 5947 #else 5948 uint64_t wdog:4; 5949 uint64_t reserved_4_18:15; 5950 uint64_t nand:1; 5951 uint64_t mio:1; 5952 uint64_t iob:1; 5953 uint64_t fpa:1; 5954 uint64_t pow:1; 5955 uint64_t l2c:1; 5956 uint64_t ipd:1; 5957 uint64_t pip:1; 5958 uint64_t pko:1; 5959 uint64_t reserved_28_28:1; 5960 uint64_t tim:1; 5961 uint64_t rad:1; 5962 uint64_t key:1; 5963 uint64_t reserved_32_32:1; 5964 uint64_t usb:1; 5965 uint64_t sli:1; 5966 uint64_t dpi:1; 5967 uint64_t agx0:1; 5968 uint64_t reserved_37_39:3; 5969 uint64_t dpi_dma:1; 5970 uint64_t reserved_41_46:6; 5971 uint64_t ptp:1; 5972 uint64_t pem0:1; 5973 uint64_t pem1:1; 5974 uint64_t reserved_50_51:2; 5975 uint64_t lmc0:1; 5976 uint64_t reserved_53_62:10; 5977 uint64_t rst:1; 5978 #endif 5979 } cnf71xx; 5980 }; 5981 5982 union cvmx_ciu_intx_sum0 { 5983 uint64_t u64; 5984 struct cvmx_ciu_intx_sum0_s { 5985 #ifdef __BIG_ENDIAN_BITFIELD 5986 uint64_t bootdma:1; 5987 uint64_t mii:1; 5988 uint64_t ipdppthr:1; 5989 uint64_t powiq:1; 5990 uint64_t twsi2:1; 5991 uint64_t mpi:1; 5992 uint64_t pcm:1; 5993 uint64_t usb:1; 5994 uint64_t timer:4; 5995 uint64_t reserved_51_51:1; 5996 uint64_t ipd_drp:1; 5997 uint64_t gmx_drp:2; 5998 uint64_t trace:1; 5999 uint64_t rml:1; 6000 uint64_t twsi:1; 6001 uint64_t wdog_sum:1; 6002 uint64_t pci_msi:4; 6003 uint64_t pci_int:4; 6004 uint64_t uart:2; 6005 uint64_t mbox:2; 6006 uint64_t gpio:16; 6007 uint64_t workq:16; 6008 #else 6009 uint64_t workq:16; 6010 uint64_t gpio:16; 6011 uint64_t mbox:2; 6012 uint64_t uart:2; 6013 uint64_t pci_int:4; 6014 uint64_t pci_msi:4; 6015 uint64_t wdog_sum:1; 6016 uint64_t twsi:1; 6017 uint64_t rml:1; 6018 uint64_t trace:1; 6019 uint64_t gmx_drp:2; 6020 uint64_t ipd_drp:1; 6021 uint64_t reserved_51_51:1; 6022 uint64_t timer:4; 6023 uint64_t usb:1; 6024 uint64_t pcm:1; 6025 uint64_t mpi:1; 6026 uint64_t twsi2:1; 6027 uint64_t powiq:1; 6028 uint64_t ipdppthr:1; 6029 uint64_t mii:1; 6030 uint64_t bootdma:1; 6031 #endif 6032 } s; 6033 struct cvmx_ciu_intx_sum0_cn30xx { 6034 #ifdef __BIG_ENDIAN_BITFIELD 6035 uint64_t reserved_59_63:5; 6036 uint64_t mpi:1; 6037 uint64_t pcm:1; 6038 uint64_t usb:1; 6039 uint64_t timer:4; 6040 uint64_t reserved_51_51:1; 6041 uint64_t ipd_drp:1; 6042 uint64_t reserved_49_49:1; 6043 uint64_t gmx_drp:1; 6044 uint64_t reserved_47_47:1; 6045 uint64_t rml:1; 6046 uint64_t twsi:1; 6047 uint64_t wdog_sum:1; 6048 uint64_t pci_msi:4; 6049 uint64_t pci_int:4; 6050 uint64_t uart:2; 6051 uint64_t mbox:2; 6052 uint64_t gpio:16; 6053 uint64_t workq:16; 6054 #else 6055 uint64_t workq:16; 6056 uint64_t gpio:16; 6057 uint64_t mbox:2; 6058 uint64_t uart:2; 6059 uint64_t pci_int:4; 6060 uint64_t pci_msi:4; 6061 uint64_t wdog_sum:1; 6062 uint64_t twsi:1; 6063 uint64_t rml:1; 6064 uint64_t reserved_47_47:1; 6065 uint64_t gmx_drp:1; 6066 uint64_t reserved_49_49:1; 6067 uint64_t ipd_drp:1; 6068 uint64_t reserved_51_51:1; 6069 uint64_t timer:4; 6070 uint64_t usb:1; 6071 uint64_t pcm:1; 6072 uint64_t mpi:1; 6073 uint64_t reserved_59_63:5; 6074 #endif 6075 } cn30xx; 6076 struct cvmx_ciu_intx_sum0_cn31xx { 6077 #ifdef __BIG_ENDIAN_BITFIELD 6078 uint64_t reserved_59_63:5; 6079 uint64_t mpi:1; 6080 uint64_t pcm:1; 6081 uint64_t usb:1; 6082 uint64_t timer:4; 6083 uint64_t reserved_51_51:1; 6084 uint64_t ipd_drp:1; 6085 uint64_t reserved_49_49:1; 6086 uint64_t gmx_drp:1; 6087 uint64_t trace:1; 6088 uint64_t rml:1; 6089 uint64_t twsi:1; 6090 uint64_t wdog_sum:1; 6091 uint64_t pci_msi:4; 6092 uint64_t pci_int:4; 6093 uint64_t uart:2; 6094 uint64_t mbox:2; 6095 uint64_t gpio:16; 6096 uint64_t workq:16; 6097 #else 6098 uint64_t workq:16; 6099 uint64_t gpio:16; 6100 uint64_t mbox:2; 6101 uint64_t uart:2; 6102 uint64_t pci_int:4; 6103 uint64_t pci_msi:4; 6104 uint64_t wdog_sum:1; 6105 uint64_t twsi:1; 6106 uint64_t rml:1; 6107 uint64_t trace:1; 6108 uint64_t gmx_drp:1; 6109 uint64_t reserved_49_49:1; 6110 uint64_t ipd_drp:1; 6111 uint64_t reserved_51_51:1; 6112 uint64_t timer:4; 6113 uint64_t usb:1; 6114 uint64_t pcm:1; 6115 uint64_t mpi:1; 6116 uint64_t reserved_59_63:5; 6117 #endif 6118 } cn31xx; 6119 struct cvmx_ciu_intx_sum0_cn38xx { 6120 #ifdef __BIG_ENDIAN_BITFIELD 6121 uint64_t reserved_56_63:8; 6122 uint64_t timer:4; 6123 uint64_t key_zero:1; 6124 uint64_t ipd_drp:1; 6125 uint64_t gmx_drp:2; 6126 uint64_t trace:1; 6127 uint64_t rml:1; 6128 uint64_t twsi:1; 6129 uint64_t wdog_sum:1; 6130 uint64_t pci_msi:4; 6131 uint64_t pci_int:4; 6132 uint64_t uart:2; 6133 uint64_t mbox:2; 6134 uint64_t gpio:16; 6135 uint64_t workq:16; 6136 #else 6137 uint64_t workq:16; 6138 uint64_t gpio:16; 6139 uint64_t mbox:2; 6140 uint64_t uart:2; 6141 uint64_t pci_int:4; 6142 uint64_t pci_msi:4; 6143 uint64_t wdog_sum:1; 6144 uint64_t twsi:1; 6145 uint64_t rml:1; 6146 uint64_t trace:1; 6147 uint64_t gmx_drp:2; 6148 uint64_t ipd_drp:1; 6149 uint64_t key_zero:1; 6150 uint64_t timer:4; 6151 uint64_t reserved_56_63:8; 6152 #endif 6153 } cn38xx; 6154 struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; 6155 struct cvmx_ciu_intx_sum0_cn30xx cn50xx; 6156 struct cvmx_ciu_intx_sum0_cn52xx { 6157 #ifdef __BIG_ENDIAN_BITFIELD 6158 uint64_t bootdma:1; 6159 uint64_t mii:1; 6160 uint64_t ipdppthr:1; 6161 uint64_t powiq:1; 6162 uint64_t twsi2:1; 6163 uint64_t reserved_57_58:2; 6164 uint64_t usb:1; 6165 uint64_t timer:4; 6166 uint64_t reserved_51_51:1; 6167 uint64_t ipd_drp:1; 6168 uint64_t reserved_49_49:1; 6169 uint64_t gmx_drp:1; 6170 uint64_t trace:1; 6171 uint64_t rml:1; 6172 uint64_t twsi:1; 6173 uint64_t wdog_sum:1; 6174 uint64_t pci_msi:4; 6175 uint64_t pci_int:4; 6176 uint64_t uart:2; 6177 uint64_t mbox:2; 6178 uint64_t gpio:16; 6179 uint64_t workq:16; 6180 #else 6181 uint64_t workq:16; 6182 uint64_t gpio:16; 6183 uint64_t mbox:2; 6184 uint64_t uart:2; 6185 uint64_t pci_int:4; 6186 uint64_t pci_msi:4; 6187 uint64_t wdog_sum:1; 6188 uint64_t twsi:1; 6189 uint64_t rml:1; 6190 uint64_t trace:1; 6191 uint64_t gmx_drp:1; 6192 uint64_t reserved_49_49:1; 6193 uint64_t ipd_drp:1; 6194 uint64_t reserved_51_51:1; 6195 uint64_t timer:4; 6196 uint64_t usb:1; 6197 uint64_t reserved_57_58:2; 6198 uint64_t twsi2:1; 6199 uint64_t powiq:1; 6200 uint64_t ipdppthr:1; 6201 uint64_t mii:1; 6202 uint64_t bootdma:1; 6203 #endif 6204 } cn52xx; 6205 struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; 6206 struct cvmx_ciu_intx_sum0_cn56xx { 6207 #ifdef __BIG_ENDIAN_BITFIELD 6208 uint64_t bootdma:1; 6209 uint64_t mii:1; 6210 uint64_t ipdppthr:1; 6211 uint64_t powiq:1; 6212 uint64_t twsi2:1; 6213 uint64_t reserved_57_58:2; 6214 uint64_t usb:1; 6215 uint64_t timer:4; 6216 uint64_t key_zero:1; 6217 uint64_t ipd_drp:1; 6218 uint64_t gmx_drp:2; 6219 uint64_t trace:1; 6220 uint64_t rml:1; 6221 uint64_t twsi:1; 6222 uint64_t wdog_sum:1; 6223 uint64_t pci_msi:4; 6224 uint64_t pci_int:4; 6225 uint64_t uart:2; 6226 uint64_t mbox:2; 6227 uint64_t gpio:16; 6228 uint64_t workq:16; 6229 #else 6230 uint64_t workq:16; 6231 uint64_t gpio:16; 6232 uint64_t mbox:2; 6233 uint64_t uart:2; 6234 uint64_t pci_int:4; 6235 uint64_t pci_msi:4; 6236 uint64_t wdog_sum:1; 6237 uint64_t twsi:1; 6238 uint64_t rml:1; 6239 uint64_t trace:1; 6240 uint64_t gmx_drp:2; 6241 uint64_t ipd_drp:1; 6242 uint64_t key_zero:1; 6243 uint64_t timer:4; 6244 uint64_t usb:1; 6245 uint64_t reserved_57_58:2; 6246 uint64_t twsi2:1; 6247 uint64_t powiq:1; 6248 uint64_t ipdppthr:1; 6249 uint64_t mii:1; 6250 uint64_t bootdma:1; 6251 #endif 6252 } cn56xx; 6253 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; 6254 struct cvmx_ciu_intx_sum0_cn38xx cn58xx; 6255 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; 6256 struct cvmx_ciu_intx_sum0_cn61xx { 6257 #ifdef __BIG_ENDIAN_BITFIELD 6258 uint64_t bootdma:1; 6259 uint64_t mii:1; 6260 uint64_t ipdppthr:1; 6261 uint64_t powiq:1; 6262 uint64_t twsi2:1; 6263 uint64_t mpi:1; 6264 uint64_t pcm:1; 6265 uint64_t usb:1; 6266 uint64_t timer:4; 6267 uint64_t sum2:1; 6268 uint64_t ipd_drp:1; 6269 uint64_t gmx_drp:2; 6270 uint64_t trace:1; 6271 uint64_t rml:1; 6272 uint64_t twsi:1; 6273 uint64_t wdog_sum:1; 6274 uint64_t pci_msi:4; 6275 uint64_t pci_int:4; 6276 uint64_t uart:2; 6277 uint64_t mbox:2; 6278 uint64_t gpio:16; 6279 uint64_t workq:16; 6280 #else 6281 uint64_t workq:16; 6282 uint64_t gpio:16; 6283 uint64_t mbox:2; 6284 uint64_t uart:2; 6285 uint64_t pci_int:4; 6286 uint64_t pci_msi:4; 6287 uint64_t wdog_sum:1; 6288 uint64_t twsi:1; 6289 uint64_t rml:1; 6290 uint64_t trace:1; 6291 uint64_t gmx_drp:2; 6292 uint64_t ipd_drp:1; 6293 uint64_t sum2:1; 6294 uint64_t timer:4; 6295 uint64_t usb:1; 6296 uint64_t pcm:1; 6297 uint64_t mpi:1; 6298 uint64_t twsi2:1; 6299 uint64_t powiq:1; 6300 uint64_t ipdppthr:1; 6301 uint64_t mii:1; 6302 uint64_t bootdma:1; 6303 #endif 6304 } cn61xx; 6305 struct cvmx_ciu_intx_sum0_cn52xx cn63xx; 6306 struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1; 6307 struct cvmx_ciu_intx_sum0_cn66xx { 6308 #ifdef __BIG_ENDIAN_BITFIELD 6309 uint64_t bootdma:1; 6310 uint64_t mii:1; 6311 uint64_t ipdppthr:1; 6312 uint64_t powiq:1; 6313 uint64_t twsi2:1; 6314 uint64_t mpi:1; 6315 uint64_t reserved_57_57:1; 6316 uint64_t usb:1; 6317 uint64_t timer:4; 6318 uint64_t sum2:1; 6319 uint64_t ipd_drp:1; 6320 uint64_t gmx_drp:2; 6321 uint64_t trace:1; 6322 uint64_t rml:1; 6323 uint64_t twsi:1; 6324 uint64_t wdog_sum:1; 6325 uint64_t pci_msi:4; 6326 uint64_t pci_int:4; 6327 uint64_t uart:2; 6328 uint64_t mbox:2; 6329 uint64_t gpio:16; 6330 uint64_t workq:16; 6331 #else 6332 uint64_t workq:16; 6333 uint64_t gpio:16; 6334 uint64_t mbox:2; 6335 uint64_t uart:2; 6336 uint64_t pci_int:4; 6337 uint64_t pci_msi:4; 6338 uint64_t wdog_sum:1; 6339 uint64_t twsi:1; 6340 uint64_t rml:1; 6341 uint64_t trace:1; 6342 uint64_t gmx_drp:2; 6343 uint64_t ipd_drp:1; 6344 uint64_t sum2:1; 6345 uint64_t timer:4; 6346 uint64_t usb:1; 6347 uint64_t reserved_57_57:1; 6348 uint64_t mpi:1; 6349 uint64_t twsi2:1; 6350 uint64_t powiq:1; 6351 uint64_t ipdppthr:1; 6352 uint64_t mii:1; 6353 uint64_t bootdma:1; 6354 #endif 6355 } cn66xx; 6356 struct cvmx_ciu_intx_sum0_cnf71xx { 6357 #ifdef __BIG_ENDIAN_BITFIELD 6358 uint64_t bootdma:1; 6359 uint64_t reserved_62_62:1; 6360 uint64_t ipdppthr:1; 6361 uint64_t powiq:1; 6362 uint64_t twsi2:1; 6363 uint64_t mpi:1; 6364 uint64_t pcm:1; 6365 uint64_t usb:1; 6366 uint64_t timer:4; 6367 uint64_t sum2:1; 6368 uint64_t ipd_drp:1; 6369 uint64_t reserved_49_49:1; 6370 uint64_t gmx_drp:1; 6371 uint64_t trace:1; 6372 uint64_t rml:1; 6373 uint64_t twsi:1; 6374 uint64_t wdog_sum:1; 6375 uint64_t pci_msi:4; 6376 uint64_t pci_int:4; 6377 uint64_t uart:2; 6378 uint64_t mbox:2; 6379 uint64_t gpio:16; 6380 uint64_t workq:16; 6381 #else 6382 uint64_t workq:16; 6383 uint64_t gpio:16; 6384 uint64_t mbox:2; 6385 uint64_t uart:2; 6386 uint64_t pci_int:4; 6387 uint64_t pci_msi:4; 6388 uint64_t wdog_sum:1; 6389 uint64_t twsi:1; 6390 uint64_t rml:1; 6391 uint64_t trace:1; 6392 uint64_t gmx_drp:1; 6393 uint64_t reserved_49_49:1; 6394 uint64_t ipd_drp:1; 6395 uint64_t sum2:1; 6396 uint64_t timer:4; 6397 uint64_t usb:1; 6398 uint64_t pcm:1; 6399 uint64_t mpi:1; 6400 uint64_t twsi2:1; 6401 uint64_t powiq:1; 6402 uint64_t ipdppthr:1; 6403 uint64_t reserved_62_62:1; 6404 uint64_t bootdma:1; 6405 #endif 6406 } cnf71xx; 6407 }; 6408 6409 union cvmx_ciu_intx_sum4 { 6410 uint64_t u64; 6411 struct cvmx_ciu_intx_sum4_s { 6412 #ifdef __BIG_ENDIAN_BITFIELD 6413 uint64_t bootdma:1; 6414 uint64_t mii:1; 6415 uint64_t ipdppthr:1; 6416 uint64_t powiq:1; 6417 uint64_t twsi2:1; 6418 uint64_t mpi:1; 6419 uint64_t pcm:1; 6420 uint64_t usb:1; 6421 uint64_t timer:4; 6422 uint64_t reserved_51_51:1; 6423 uint64_t ipd_drp:1; 6424 uint64_t gmx_drp:2; 6425 uint64_t trace:1; 6426 uint64_t rml:1; 6427 uint64_t twsi:1; 6428 uint64_t wdog_sum:1; 6429 uint64_t pci_msi:4; 6430 uint64_t pci_int:4; 6431 uint64_t uart:2; 6432 uint64_t mbox:2; 6433 uint64_t gpio:16; 6434 uint64_t workq:16; 6435 #else 6436 uint64_t workq:16; 6437 uint64_t gpio:16; 6438 uint64_t mbox:2; 6439 uint64_t uart:2; 6440 uint64_t pci_int:4; 6441 uint64_t pci_msi:4; 6442 uint64_t wdog_sum:1; 6443 uint64_t twsi:1; 6444 uint64_t rml:1; 6445 uint64_t trace:1; 6446 uint64_t gmx_drp:2; 6447 uint64_t ipd_drp:1; 6448 uint64_t reserved_51_51:1; 6449 uint64_t timer:4; 6450 uint64_t usb:1; 6451 uint64_t pcm:1; 6452 uint64_t mpi:1; 6453 uint64_t twsi2:1; 6454 uint64_t powiq:1; 6455 uint64_t ipdppthr:1; 6456 uint64_t mii:1; 6457 uint64_t bootdma:1; 6458 #endif 6459 } s; 6460 struct cvmx_ciu_intx_sum4_cn50xx { 6461 #ifdef __BIG_ENDIAN_BITFIELD 6462 uint64_t reserved_59_63:5; 6463 uint64_t mpi:1; 6464 uint64_t pcm:1; 6465 uint64_t usb:1; 6466 uint64_t timer:4; 6467 uint64_t reserved_51_51:1; 6468 uint64_t ipd_drp:1; 6469 uint64_t reserved_49_49:1; 6470 uint64_t gmx_drp:1; 6471 uint64_t reserved_47_47:1; 6472 uint64_t rml:1; 6473 uint64_t twsi:1; 6474 uint64_t wdog_sum:1; 6475 uint64_t pci_msi:4; 6476 uint64_t pci_int:4; 6477 uint64_t uart:2; 6478 uint64_t mbox:2; 6479 uint64_t gpio:16; 6480 uint64_t workq:16; 6481 #else 6482 uint64_t workq:16; 6483 uint64_t gpio:16; 6484 uint64_t mbox:2; 6485 uint64_t uart:2; 6486 uint64_t pci_int:4; 6487 uint64_t pci_msi:4; 6488 uint64_t wdog_sum:1; 6489 uint64_t twsi:1; 6490 uint64_t rml:1; 6491 uint64_t reserved_47_47:1; 6492 uint64_t gmx_drp:1; 6493 uint64_t reserved_49_49:1; 6494 uint64_t ipd_drp:1; 6495 uint64_t reserved_51_51:1; 6496 uint64_t timer:4; 6497 uint64_t usb:1; 6498 uint64_t pcm:1; 6499 uint64_t mpi:1; 6500 uint64_t reserved_59_63:5; 6501 #endif 6502 } cn50xx; 6503 struct cvmx_ciu_intx_sum4_cn52xx { 6504 #ifdef __BIG_ENDIAN_BITFIELD 6505 uint64_t bootdma:1; 6506 uint64_t mii:1; 6507 uint64_t ipdppthr:1; 6508 uint64_t powiq:1; 6509 uint64_t twsi2:1; 6510 uint64_t reserved_57_58:2; 6511 uint64_t usb:1; 6512 uint64_t timer:4; 6513 uint64_t reserved_51_51:1; 6514 uint64_t ipd_drp:1; 6515 uint64_t reserved_49_49:1; 6516 uint64_t gmx_drp:1; 6517 uint64_t trace:1; 6518 uint64_t rml:1; 6519 uint64_t twsi:1; 6520 uint64_t wdog_sum:1; 6521 uint64_t pci_msi:4; 6522 uint64_t pci_int:4; 6523 uint64_t uart:2; 6524 uint64_t mbox:2; 6525 uint64_t gpio:16; 6526 uint64_t workq:16; 6527 #else 6528 uint64_t workq:16; 6529 uint64_t gpio:16; 6530 uint64_t mbox:2; 6531 uint64_t uart:2; 6532 uint64_t pci_int:4; 6533 uint64_t pci_msi:4; 6534 uint64_t wdog_sum:1; 6535 uint64_t twsi:1; 6536 uint64_t rml:1; 6537 uint64_t trace:1; 6538 uint64_t gmx_drp:1; 6539 uint64_t reserved_49_49:1; 6540 uint64_t ipd_drp:1; 6541 uint64_t reserved_51_51:1; 6542 uint64_t timer:4; 6543 uint64_t usb:1; 6544 uint64_t reserved_57_58:2; 6545 uint64_t twsi2:1; 6546 uint64_t powiq:1; 6547 uint64_t ipdppthr:1; 6548 uint64_t mii:1; 6549 uint64_t bootdma:1; 6550 #endif 6551 } cn52xx; 6552 struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; 6553 struct cvmx_ciu_intx_sum4_cn56xx { 6554 #ifdef __BIG_ENDIAN_BITFIELD 6555 uint64_t bootdma:1; 6556 uint64_t mii:1; 6557 uint64_t ipdppthr:1; 6558 uint64_t powiq:1; 6559 uint64_t twsi2:1; 6560 uint64_t reserved_57_58:2; 6561 uint64_t usb:1; 6562 uint64_t timer:4; 6563 uint64_t key_zero:1; 6564 uint64_t ipd_drp:1; 6565 uint64_t gmx_drp:2; 6566 uint64_t trace:1; 6567 uint64_t rml:1; 6568 uint64_t twsi:1; 6569 uint64_t wdog_sum:1; 6570 uint64_t pci_msi:4; 6571 uint64_t pci_int:4; 6572 uint64_t uart:2; 6573 uint64_t mbox:2; 6574 uint64_t gpio:16; 6575 uint64_t workq:16; 6576 #else 6577 uint64_t workq:16; 6578 uint64_t gpio:16; 6579 uint64_t mbox:2; 6580 uint64_t uart:2; 6581 uint64_t pci_int:4; 6582 uint64_t pci_msi:4; 6583 uint64_t wdog_sum:1; 6584 uint64_t twsi:1; 6585 uint64_t rml:1; 6586 uint64_t trace:1; 6587 uint64_t gmx_drp:2; 6588 uint64_t ipd_drp:1; 6589 uint64_t key_zero:1; 6590 uint64_t timer:4; 6591 uint64_t usb:1; 6592 uint64_t reserved_57_58:2; 6593 uint64_t twsi2:1; 6594 uint64_t powiq:1; 6595 uint64_t ipdppthr:1; 6596 uint64_t mii:1; 6597 uint64_t bootdma:1; 6598 #endif 6599 } cn56xx; 6600 struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; 6601 struct cvmx_ciu_intx_sum4_cn58xx { 6602 #ifdef __BIG_ENDIAN_BITFIELD 6603 uint64_t reserved_56_63:8; 6604 uint64_t timer:4; 6605 uint64_t key_zero:1; 6606 uint64_t ipd_drp:1; 6607 uint64_t gmx_drp:2; 6608 uint64_t trace:1; 6609 uint64_t rml:1; 6610 uint64_t twsi:1; 6611 uint64_t wdog_sum:1; 6612 uint64_t pci_msi:4; 6613 uint64_t pci_int:4; 6614 uint64_t uart:2; 6615 uint64_t mbox:2; 6616 uint64_t gpio:16; 6617 uint64_t workq:16; 6618 #else 6619 uint64_t workq:16; 6620 uint64_t gpio:16; 6621 uint64_t mbox:2; 6622 uint64_t uart:2; 6623 uint64_t pci_int:4; 6624 uint64_t pci_msi:4; 6625 uint64_t wdog_sum:1; 6626 uint64_t twsi:1; 6627 uint64_t rml:1; 6628 uint64_t trace:1; 6629 uint64_t gmx_drp:2; 6630 uint64_t ipd_drp:1; 6631 uint64_t key_zero:1; 6632 uint64_t timer:4; 6633 uint64_t reserved_56_63:8; 6634 #endif 6635 } cn58xx; 6636 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; 6637 struct cvmx_ciu_intx_sum4_cn61xx { 6638 #ifdef __BIG_ENDIAN_BITFIELD 6639 uint64_t bootdma:1; 6640 uint64_t mii:1; 6641 uint64_t ipdppthr:1; 6642 uint64_t powiq:1; 6643 uint64_t twsi2:1; 6644 uint64_t mpi:1; 6645 uint64_t pcm:1; 6646 uint64_t usb:1; 6647 uint64_t timer:4; 6648 uint64_t sum2:1; 6649 uint64_t ipd_drp:1; 6650 uint64_t gmx_drp:2; 6651 uint64_t trace:1; 6652 uint64_t rml:1; 6653 uint64_t twsi:1; 6654 uint64_t wdog_sum:1; 6655 uint64_t pci_msi:4; 6656 uint64_t pci_int:4; 6657 uint64_t uart:2; 6658 uint64_t mbox:2; 6659 uint64_t gpio:16; 6660 uint64_t workq:16; 6661 #else 6662 uint64_t workq:16; 6663 uint64_t gpio:16; 6664 uint64_t mbox:2; 6665 uint64_t uart:2; 6666 uint64_t pci_int:4; 6667 uint64_t pci_msi:4; 6668 uint64_t wdog_sum:1; 6669 uint64_t twsi:1; 6670 uint64_t rml:1; 6671 uint64_t trace:1; 6672 uint64_t gmx_drp:2; 6673 uint64_t ipd_drp:1; 6674 uint64_t sum2:1; 6675 uint64_t timer:4; 6676 uint64_t usb:1; 6677 uint64_t pcm:1; 6678 uint64_t mpi:1; 6679 uint64_t twsi2:1; 6680 uint64_t powiq:1; 6681 uint64_t ipdppthr:1; 6682 uint64_t mii:1; 6683 uint64_t bootdma:1; 6684 #endif 6685 } cn61xx; 6686 struct cvmx_ciu_intx_sum4_cn52xx cn63xx; 6687 struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1; 6688 struct cvmx_ciu_intx_sum4_cn66xx { 6689 #ifdef __BIG_ENDIAN_BITFIELD 6690 uint64_t bootdma:1; 6691 uint64_t mii:1; 6692 uint64_t ipdppthr:1; 6693 uint64_t powiq:1; 6694 uint64_t twsi2:1; 6695 uint64_t mpi:1; 6696 uint64_t reserved_57_57:1; 6697 uint64_t usb:1; 6698 uint64_t timer:4; 6699 uint64_t sum2:1; 6700 uint64_t ipd_drp:1; 6701 uint64_t gmx_drp:2; 6702 uint64_t trace:1; 6703 uint64_t rml:1; 6704 uint64_t twsi:1; 6705 uint64_t wdog_sum:1; 6706 uint64_t pci_msi:4; 6707 uint64_t pci_int:4; 6708 uint64_t uart:2; 6709 uint64_t mbox:2; 6710 uint64_t gpio:16; 6711 uint64_t workq:16; 6712 #else 6713 uint64_t workq:16; 6714 uint64_t gpio:16; 6715 uint64_t mbox:2; 6716 uint64_t uart:2; 6717 uint64_t pci_int:4; 6718 uint64_t pci_msi:4; 6719 uint64_t wdog_sum:1; 6720 uint64_t twsi:1; 6721 uint64_t rml:1; 6722 uint64_t trace:1; 6723 uint64_t gmx_drp:2; 6724 uint64_t ipd_drp:1; 6725 uint64_t sum2:1; 6726 uint64_t timer:4; 6727 uint64_t usb:1; 6728 uint64_t reserved_57_57:1; 6729 uint64_t mpi:1; 6730 uint64_t twsi2:1; 6731 uint64_t powiq:1; 6732 uint64_t ipdppthr:1; 6733 uint64_t mii:1; 6734 uint64_t bootdma:1; 6735 #endif 6736 } cn66xx; 6737 struct cvmx_ciu_intx_sum4_cnf71xx { 6738 #ifdef __BIG_ENDIAN_BITFIELD 6739 uint64_t bootdma:1; 6740 uint64_t reserved_62_62:1; 6741 uint64_t ipdppthr:1; 6742 uint64_t powiq:1; 6743 uint64_t twsi2:1; 6744 uint64_t mpi:1; 6745 uint64_t pcm:1; 6746 uint64_t usb:1; 6747 uint64_t timer:4; 6748 uint64_t sum2:1; 6749 uint64_t ipd_drp:1; 6750 uint64_t reserved_49_49:1; 6751 uint64_t gmx_drp:1; 6752 uint64_t trace:1; 6753 uint64_t rml:1; 6754 uint64_t twsi:1; 6755 uint64_t wdog_sum:1; 6756 uint64_t pci_msi:4; 6757 uint64_t pci_int:4; 6758 uint64_t uart:2; 6759 uint64_t mbox:2; 6760 uint64_t gpio:16; 6761 uint64_t workq:16; 6762 #else 6763 uint64_t workq:16; 6764 uint64_t gpio:16; 6765 uint64_t mbox:2; 6766 uint64_t uart:2; 6767 uint64_t pci_int:4; 6768 uint64_t pci_msi:4; 6769 uint64_t wdog_sum:1; 6770 uint64_t twsi:1; 6771 uint64_t rml:1; 6772 uint64_t trace:1; 6773 uint64_t gmx_drp:1; 6774 uint64_t reserved_49_49:1; 6775 uint64_t ipd_drp:1; 6776 uint64_t sum2:1; 6777 uint64_t timer:4; 6778 uint64_t usb:1; 6779 uint64_t pcm:1; 6780 uint64_t mpi:1; 6781 uint64_t twsi2:1; 6782 uint64_t powiq:1; 6783 uint64_t ipdppthr:1; 6784 uint64_t reserved_62_62:1; 6785 uint64_t bootdma:1; 6786 #endif 6787 } cnf71xx; 6788 }; 6789 6790 union cvmx_ciu_int33_sum0 { 6791 uint64_t u64; 6792 struct cvmx_ciu_int33_sum0_s { 6793 #ifdef __BIG_ENDIAN_BITFIELD 6794 uint64_t bootdma:1; 6795 uint64_t mii:1; 6796 uint64_t ipdppthr:1; 6797 uint64_t powiq:1; 6798 uint64_t twsi2:1; 6799 uint64_t mpi:1; 6800 uint64_t pcm:1; 6801 uint64_t usb:1; 6802 uint64_t timer:4; 6803 uint64_t sum2:1; 6804 uint64_t ipd_drp:1; 6805 uint64_t gmx_drp:2; 6806 uint64_t trace:1; 6807 uint64_t rml:1; 6808 uint64_t twsi:1; 6809 uint64_t wdog_sum:1; 6810 uint64_t pci_msi:4; 6811 uint64_t pci_int:4; 6812 uint64_t uart:2; 6813 uint64_t mbox:2; 6814 uint64_t gpio:16; 6815 uint64_t workq:16; 6816 #else 6817 uint64_t workq:16; 6818 uint64_t gpio:16; 6819 uint64_t mbox:2; 6820 uint64_t uart:2; 6821 uint64_t pci_int:4; 6822 uint64_t pci_msi:4; 6823 uint64_t wdog_sum:1; 6824 uint64_t twsi:1; 6825 uint64_t rml:1; 6826 uint64_t trace:1; 6827 uint64_t gmx_drp:2; 6828 uint64_t ipd_drp:1; 6829 uint64_t sum2:1; 6830 uint64_t timer:4; 6831 uint64_t usb:1; 6832 uint64_t pcm:1; 6833 uint64_t mpi:1; 6834 uint64_t twsi2:1; 6835 uint64_t powiq:1; 6836 uint64_t ipdppthr:1; 6837 uint64_t mii:1; 6838 uint64_t bootdma:1; 6839 #endif 6840 } s; 6841 struct cvmx_ciu_int33_sum0_s cn61xx; 6842 struct cvmx_ciu_int33_sum0_cn63xx { 6843 #ifdef __BIG_ENDIAN_BITFIELD 6844 uint64_t bootdma:1; 6845 uint64_t mii:1; 6846 uint64_t ipdppthr:1; 6847 uint64_t powiq:1; 6848 uint64_t twsi2:1; 6849 uint64_t reserved_57_58:2; 6850 uint64_t usb:1; 6851 uint64_t timer:4; 6852 uint64_t reserved_51_51:1; 6853 uint64_t ipd_drp:1; 6854 uint64_t reserved_49_49:1; 6855 uint64_t gmx_drp:1; 6856 uint64_t trace:1; 6857 uint64_t rml:1; 6858 uint64_t twsi:1; 6859 uint64_t wdog_sum:1; 6860 uint64_t pci_msi:4; 6861 uint64_t pci_int:4; 6862 uint64_t uart:2; 6863 uint64_t mbox:2; 6864 uint64_t gpio:16; 6865 uint64_t workq:16; 6866 #else 6867 uint64_t workq:16; 6868 uint64_t gpio:16; 6869 uint64_t mbox:2; 6870 uint64_t uart:2; 6871 uint64_t pci_int:4; 6872 uint64_t pci_msi:4; 6873 uint64_t wdog_sum:1; 6874 uint64_t twsi:1; 6875 uint64_t rml:1; 6876 uint64_t trace:1; 6877 uint64_t gmx_drp:1; 6878 uint64_t reserved_49_49:1; 6879 uint64_t ipd_drp:1; 6880 uint64_t reserved_51_51:1; 6881 uint64_t timer:4; 6882 uint64_t usb:1; 6883 uint64_t reserved_57_58:2; 6884 uint64_t twsi2:1; 6885 uint64_t powiq:1; 6886 uint64_t ipdppthr:1; 6887 uint64_t mii:1; 6888 uint64_t bootdma:1; 6889 #endif 6890 } cn63xx; 6891 struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1; 6892 struct cvmx_ciu_int33_sum0_cn66xx { 6893 #ifdef __BIG_ENDIAN_BITFIELD 6894 uint64_t bootdma:1; 6895 uint64_t mii:1; 6896 uint64_t ipdppthr:1; 6897 uint64_t powiq:1; 6898 uint64_t twsi2:1; 6899 uint64_t mpi:1; 6900 uint64_t reserved_57_57:1; 6901 uint64_t usb:1; 6902 uint64_t timer:4; 6903 uint64_t sum2:1; 6904 uint64_t ipd_drp:1; 6905 uint64_t gmx_drp:2; 6906 uint64_t trace:1; 6907 uint64_t rml:1; 6908 uint64_t twsi:1; 6909 uint64_t wdog_sum:1; 6910 uint64_t pci_msi:4; 6911 uint64_t pci_int:4; 6912 uint64_t uart:2; 6913 uint64_t mbox:2; 6914 uint64_t gpio:16; 6915 uint64_t workq:16; 6916 #else 6917 uint64_t workq:16; 6918 uint64_t gpio:16; 6919 uint64_t mbox:2; 6920 uint64_t uart:2; 6921 uint64_t pci_int:4; 6922 uint64_t pci_msi:4; 6923 uint64_t wdog_sum:1; 6924 uint64_t twsi:1; 6925 uint64_t rml:1; 6926 uint64_t trace:1; 6927 uint64_t gmx_drp:2; 6928 uint64_t ipd_drp:1; 6929 uint64_t sum2:1; 6930 uint64_t timer:4; 6931 uint64_t usb:1; 6932 uint64_t reserved_57_57:1; 6933 uint64_t mpi:1; 6934 uint64_t twsi2:1; 6935 uint64_t powiq:1; 6936 uint64_t ipdppthr:1; 6937 uint64_t mii:1; 6938 uint64_t bootdma:1; 6939 #endif 6940 } cn66xx; 6941 struct cvmx_ciu_int33_sum0_cnf71xx { 6942 #ifdef __BIG_ENDIAN_BITFIELD 6943 uint64_t bootdma:1; 6944 uint64_t reserved_62_62:1; 6945 uint64_t ipdppthr:1; 6946 uint64_t powiq:1; 6947 uint64_t twsi2:1; 6948 uint64_t mpi:1; 6949 uint64_t pcm:1; 6950 uint64_t usb:1; 6951 uint64_t timer:4; 6952 uint64_t sum2:1; 6953 uint64_t ipd_drp:1; 6954 uint64_t reserved_49_49:1; 6955 uint64_t gmx_drp:1; 6956 uint64_t trace:1; 6957 uint64_t rml:1; 6958 uint64_t twsi:1; 6959 uint64_t wdog_sum:1; 6960 uint64_t pci_msi:4; 6961 uint64_t pci_int:4; 6962 uint64_t uart:2; 6963 uint64_t mbox:2; 6964 uint64_t gpio:16; 6965 uint64_t workq:16; 6966 #else 6967 uint64_t workq:16; 6968 uint64_t gpio:16; 6969 uint64_t mbox:2; 6970 uint64_t uart:2; 6971 uint64_t pci_int:4; 6972 uint64_t pci_msi:4; 6973 uint64_t wdog_sum:1; 6974 uint64_t twsi:1; 6975 uint64_t rml:1; 6976 uint64_t trace:1; 6977 uint64_t gmx_drp:1; 6978 uint64_t reserved_49_49:1; 6979 uint64_t ipd_drp:1; 6980 uint64_t sum2:1; 6981 uint64_t timer:4; 6982 uint64_t usb:1; 6983 uint64_t pcm:1; 6984 uint64_t mpi:1; 6985 uint64_t twsi2:1; 6986 uint64_t powiq:1; 6987 uint64_t ipdppthr:1; 6988 uint64_t reserved_62_62:1; 6989 uint64_t bootdma:1; 6990 #endif 6991 } cnf71xx; 6992 }; 6993 6994 union cvmx_ciu_int_dbg_sel { 6995 uint64_t u64; 6996 struct cvmx_ciu_int_dbg_sel_s { 6997 #ifdef __BIG_ENDIAN_BITFIELD 6998 uint64_t reserved_19_63:45; 6999 uint64_t sel:3; 7000 uint64_t reserved_10_15:6; 7001 uint64_t irq:2; 7002 uint64_t reserved_5_7:3; 7003 uint64_t pp:5; 7004 #else 7005 uint64_t pp:5; 7006 uint64_t reserved_5_7:3; 7007 uint64_t irq:2; 7008 uint64_t reserved_10_15:6; 7009 uint64_t sel:3; 7010 uint64_t reserved_19_63:45; 7011 #endif 7012 } s; 7013 struct cvmx_ciu_int_dbg_sel_cn61xx { 7014 #ifdef __BIG_ENDIAN_BITFIELD 7015 uint64_t reserved_19_63:45; 7016 uint64_t sel:3; 7017 uint64_t reserved_10_15:6; 7018 uint64_t irq:2; 7019 uint64_t reserved_4_7:4; 7020 uint64_t pp:4; 7021 #else 7022 uint64_t pp:4; 7023 uint64_t reserved_4_7:4; 7024 uint64_t irq:2; 7025 uint64_t reserved_10_15:6; 7026 uint64_t sel:3; 7027 uint64_t reserved_19_63:45; 7028 #endif 7029 } cn61xx; 7030 struct cvmx_ciu_int_dbg_sel_cn63xx { 7031 #ifdef __BIG_ENDIAN_BITFIELD 7032 uint64_t reserved_19_63:45; 7033 uint64_t sel:3; 7034 uint64_t reserved_10_15:6; 7035 uint64_t irq:2; 7036 uint64_t reserved_3_7:5; 7037 uint64_t pp:3; 7038 #else 7039 uint64_t pp:3; 7040 uint64_t reserved_3_7:5; 7041 uint64_t irq:2; 7042 uint64_t reserved_10_15:6; 7043 uint64_t sel:3; 7044 uint64_t reserved_19_63:45; 7045 #endif 7046 } cn63xx; 7047 struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx; 7048 struct cvmx_ciu_int_dbg_sel_s cn68xx; 7049 struct cvmx_ciu_int_dbg_sel_s cn68xxp1; 7050 struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx; 7051 }; 7052 7053 union cvmx_ciu_int_sum1 { 7054 uint64_t u64; 7055 struct cvmx_ciu_int_sum1_s { 7056 #ifdef __BIG_ENDIAN_BITFIELD 7057 uint64_t rst:1; 7058 uint64_t reserved_62_62:1; 7059 uint64_t srio3:1; 7060 uint64_t srio2:1; 7061 uint64_t reserved_57_59:3; 7062 uint64_t dfm:1; 7063 uint64_t reserved_53_55:3; 7064 uint64_t lmc0:1; 7065 uint64_t srio1:1; 7066 uint64_t srio0:1; 7067 uint64_t pem1:1; 7068 uint64_t pem0:1; 7069 uint64_t ptp:1; 7070 uint64_t agl:1; 7071 uint64_t reserved_38_45:8; 7072 uint64_t agx1:1; 7073 uint64_t agx0:1; 7074 uint64_t dpi:1; 7075 uint64_t sli:1; 7076 uint64_t usb:1; 7077 uint64_t dfa:1; 7078 uint64_t key:1; 7079 uint64_t rad:1; 7080 uint64_t tim:1; 7081 uint64_t zip:1; 7082 uint64_t pko:1; 7083 uint64_t pip:1; 7084 uint64_t ipd:1; 7085 uint64_t l2c:1; 7086 uint64_t pow:1; 7087 uint64_t fpa:1; 7088 uint64_t iob:1; 7089 uint64_t mio:1; 7090 uint64_t nand:1; 7091 uint64_t mii1:1; 7092 uint64_t usb1:1; 7093 uint64_t uart2:1; 7094 uint64_t wdog:16; 7095 #else 7096 uint64_t wdog:16; 7097 uint64_t uart2:1; 7098 uint64_t usb1:1; 7099 uint64_t mii1:1; 7100 uint64_t nand:1; 7101 uint64_t mio:1; 7102 uint64_t iob:1; 7103 uint64_t fpa:1; 7104 uint64_t pow:1; 7105 uint64_t l2c:1; 7106 uint64_t ipd:1; 7107 uint64_t pip:1; 7108 uint64_t pko:1; 7109 uint64_t zip:1; 7110 uint64_t tim:1; 7111 uint64_t rad:1; 7112 uint64_t key:1; 7113 uint64_t dfa:1; 7114 uint64_t usb:1; 7115 uint64_t sli:1; 7116 uint64_t dpi:1; 7117 uint64_t agx0:1; 7118 uint64_t agx1:1; 7119 uint64_t reserved_38_45:8; 7120 uint64_t agl:1; 7121 uint64_t ptp:1; 7122 uint64_t pem0:1; 7123 uint64_t pem1:1; 7124 uint64_t srio0:1; 7125 uint64_t srio1:1; 7126 uint64_t lmc0:1; 7127 uint64_t reserved_53_55:3; 7128 uint64_t dfm:1; 7129 uint64_t reserved_57_59:3; 7130 uint64_t srio2:1; 7131 uint64_t srio3:1; 7132 uint64_t reserved_62_62:1; 7133 uint64_t rst:1; 7134 #endif 7135 } s; 7136 struct cvmx_ciu_int_sum1_cn30xx { 7137 #ifdef __BIG_ENDIAN_BITFIELD 7138 uint64_t reserved_1_63:63; 7139 uint64_t wdog:1; 7140 #else 7141 uint64_t wdog:1; 7142 uint64_t reserved_1_63:63; 7143 #endif 7144 } cn30xx; 7145 struct cvmx_ciu_int_sum1_cn31xx { 7146 #ifdef __BIG_ENDIAN_BITFIELD 7147 uint64_t reserved_2_63:62; 7148 uint64_t wdog:2; 7149 #else 7150 uint64_t wdog:2; 7151 uint64_t reserved_2_63:62; 7152 #endif 7153 } cn31xx; 7154 struct cvmx_ciu_int_sum1_cn38xx { 7155 #ifdef __BIG_ENDIAN_BITFIELD 7156 uint64_t reserved_16_63:48; 7157 uint64_t wdog:16; 7158 #else 7159 uint64_t wdog:16; 7160 uint64_t reserved_16_63:48; 7161 #endif 7162 } cn38xx; 7163 struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; 7164 struct cvmx_ciu_int_sum1_cn31xx cn50xx; 7165 struct cvmx_ciu_int_sum1_cn52xx { 7166 #ifdef __BIG_ENDIAN_BITFIELD 7167 uint64_t reserved_20_63:44; 7168 uint64_t nand:1; 7169 uint64_t mii1:1; 7170 uint64_t usb1:1; 7171 uint64_t uart2:1; 7172 uint64_t reserved_4_15:12; 7173 uint64_t wdog:4; 7174 #else 7175 uint64_t wdog:4; 7176 uint64_t reserved_4_15:12; 7177 uint64_t uart2:1; 7178 uint64_t usb1:1; 7179 uint64_t mii1:1; 7180 uint64_t nand:1; 7181 uint64_t reserved_20_63:44; 7182 #endif 7183 } cn52xx; 7184 struct cvmx_ciu_int_sum1_cn52xxp1 { 7185 #ifdef __BIG_ENDIAN_BITFIELD 7186 uint64_t reserved_19_63:45; 7187 uint64_t mii1:1; 7188 uint64_t usb1:1; 7189 uint64_t uart2:1; 7190 uint64_t reserved_4_15:12; 7191 uint64_t wdog:4; 7192 #else 7193 uint64_t wdog:4; 7194 uint64_t reserved_4_15:12; 7195 uint64_t uart2:1; 7196 uint64_t usb1:1; 7197 uint64_t mii1:1; 7198 uint64_t reserved_19_63:45; 7199 #endif 7200 } cn52xxp1; 7201 struct cvmx_ciu_int_sum1_cn56xx { 7202 #ifdef __BIG_ENDIAN_BITFIELD 7203 uint64_t reserved_12_63:52; 7204 uint64_t wdog:12; 7205 #else 7206 uint64_t wdog:12; 7207 uint64_t reserved_12_63:52; 7208 #endif 7209 } cn56xx; 7210 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; 7211 struct cvmx_ciu_int_sum1_cn38xx cn58xx; 7212 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; 7213 struct cvmx_ciu_int_sum1_cn61xx { 7214 #ifdef __BIG_ENDIAN_BITFIELD 7215 uint64_t rst:1; 7216 uint64_t reserved_53_62:10; 7217 uint64_t lmc0:1; 7218 uint64_t reserved_50_51:2; 7219 uint64_t pem1:1; 7220 uint64_t pem0:1; 7221 uint64_t ptp:1; 7222 uint64_t agl:1; 7223 uint64_t reserved_38_45:8; 7224 uint64_t agx1:1; 7225 uint64_t agx0:1; 7226 uint64_t dpi:1; 7227 uint64_t sli:1; 7228 uint64_t usb:1; 7229 uint64_t dfa:1; 7230 uint64_t key:1; 7231 uint64_t rad:1; 7232 uint64_t tim:1; 7233 uint64_t zip:1; 7234 uint64_t pko:1; 7235 uint64_t pip:1; 7236 uint64_t ipd:1; 7237 uint64_t l2c:1; 7238 uint64_t pow:1; 7239 uint64_t fpa:1; 7240 uint64_t iob:1; 7241 uint64_t mio:1; 7242 uint64_t nand:1; 7243 uint64_t mii1:1; 7244 uint64_t reserved_4_17:14; 7245 uint64_t wdog:4; 7246 #else 7247 uint64_t wdog:4; 7248 uint64_t reserved_4_17:14; 7249 uint64_t mii1:1; 7250 uint64_t nand:1; 7251 uint64_t mio:1; 7252 uint64_t iob:1; 7253 uint64_t fpa:1; 7254 uint64_t pow:1; 7255 uint64_t l2c:1; 7256 uint64_t ipd:1; 7257 uint64_t pip:1; 7258 uint64_t pko:1; 7259 uint64_t zip:1; 7260 uint64_t tim:1; 7261 uint64_t rad:1; 7262 uint64_t key:1; 7263 uint64_t dfa:1; 7264 uint64_t usb:1; 7265 uint64_t sli:1; 7266 uint64_t dpi:1; 7267 uint64_t agx0:1; 7268 uint64_t agx1:1; 7269 uint64_t reserved_38_45:8; 7270 uint64_t agl:1; 7271 uint64_t ptp:1; 7272 uint64_t pem0:1; 7273 uint64_t pem1:1; 7274 uint64_t reserved_50_51:2; 7275 uint64_t lmc0:1; 7276 uint64_t reserved_53_62:10; 7277 uint64_t rst:1; 7278 #endif 7279 } cn61xx; 7280 struct cvmx_ciu_int_sum1_cn63xx { 7281 #ifdef __BIG_ENDIAN_BITFIELD 7282 uint64_t rst:1; 7283 uint64_t reserved_57_62:6; 7284 uint64_t dfm:1; 7285 uint64_t reserved_53_55:3; 7286 uint64_t lmc0:1; 7287 uint64_t srio1:1; 7288 uint64_t srio0:1; 7289 uint64_t pem1:1; 7290 uint64_t pem0:1; 7291 uint64_t ptp:1; 7292 uint64_t agl:1; 7293 uint64_t reserved_37_45:9; 7294 uint64_t agx0:1; 7295 uint64_t dpi:1; 7296 uint64_t sli:1; 7297 uint64_t usb:1; 7298 uint64_t dfa:1; 7299 uint64_t key:1; 7300 uint64_t rad:1; 7301 uint64_t tim:1; 7302 uint64_t zip:1; 7303 uint64_t pko:1; 7304 uint64_t pip:1; 7305 uint64_t ipd:1; 7306 uint64_t l2c:1; 7307 uint64_t pow:1; 7308 uint64_t fpa:1; 7309 uint64_t iob:1; 7310 uint64_t mio:1; 7311 uint64_t nand:1; 7312 uint64_t mii1:1; 7313 uint64_t reserved_6_17:12; 7314 uint64_t wdog:6; 7315 #else 7316 uint64_t wdog:6; 7317 uint64_t reserved_6_17:12; 7318 uint64_t mii1:1; 7319 uint64_t nand:1; 7320 uint64_t mio:1; 7321 uint64_t iob:1; 7322 uint64_t fpa:1; 7323 uint64_t pow:1; 7324 uint64_t l2c:1; 7325 uint64_t ipd:1; 7326 uint64_t pip:1; 7327 uint64_t pko:1; 7328 uint64_t zip:1; 7329 uint64_t tim:1; 7330 uint64_t rad:1; 7331 uint64_t key:1; 7332 uint64_t dfa:1; 7333 uint64_t usb:1; 7334 uint64_t sli:1; 7335 uint64_t dpi:1; 7336 uint64_t agx0:1; 7337 uint64_t reserved_37_45:9; 7338 uint64_t agl:1; 7339 uint64_t ptp:1; 7340 uint64_t pem0:1; 7341 uint64_t pem1:1; 7342 uint64_t srio0:1; 7343 uint64_t srio1:1; 7344 uint64_t lmc0:1; 7345 uint64_t reserved_53_55:3; 7346 uint64_t dfm:1; 7347 uint64_t reserved_57_62:6; 7348 uint64_t rst:1; 7349 #endif 7350 } cn63xx; 7351 struct cvmx_ciu_int_sum1_cn63xx cn63xxp1; 7352 struct cvmx_ciu_int_sum1_cn66xx { 7353 #ifdef __BIG_ENDIAN_BITFIELD 7354 uint64_t rst:1; 7355 uint64_t reserved_62_62:1; 7356 uint64_t srio3:1; 7357 uint64_t srio2:1; 7358 uint64_t reserved_57_59:3; 7359 uint64_t dfm:1; 7360 uint64_t reserved_53_55:3; 7361 uint64_t lmc0:1; 7362 uint64_t reserved_51_51:1; 7363 uint64_t srio0:1; 7364 uint64_t pem1:1; 7365 uint64_t pem0:1; 7366 uint64_t ptp:1; 7367 uint64_t agl:1; 7368 uint64_t reserved_38_45:8; 7369 uint64_t agx1:1; 7370 uint64_t agx0:1; 7371 uint64_t dpi:1; 7372 uint64_t sli:1; 7373 uint64_t usb:1; 7374 uint64_t dfa:1; 7375 uint64_t key:1; 7376 uint64_t rad:1; 7377 uint64_t tim:1; 7378 uint64_t zip:1; 7379 uint64_t pko:1; 7380 uint64_t pip:1; 7381 uint64_t ipd:1; 7382 uint64_t l2c:1; 7383 uint64_t pow:1; 7384 uint64_t fpa:1; 7385 uint64_t iob:1; 7386 uint64_t mio:1; 7387 uint64_t nand:1; 7388 uint64_t mii1:1; 7389 uint64_t reserved_10_17:8; 7390 uint64_t wdog:10; 7391 #else 7392 uint64_t wdog:10; 7393 uint64_t reserved_10_17:8; 7394 uint64_t mii1:1; 7395 uint64_t nand:1; 7396 uint64_t mio:1; 7397 uint64_t iob:1; 7398 uint64_t fpa:1; 7399 uint64_t pow:1; 7400 uint64_t l2c:1; 7401 uint64_t ipd:1; 7402 uint64_t pip:1; 7403 uint64_t pko:1; 7404 uint64_t zip:1; 7405 uint64_t tim:1; 7406 uint64_t rad:1; 7407 uint64_t key:1; 7408 uint64_t dfa:1; 7409 uint64_t usb:1; 7410 uint64_t sli:1; 7411 uint64_t dpi:1; 7412 uint64_t agx0:1; 7413 uint64_t agx1:1; 7414 uint64_t reserved_38_45:8; 7415 uint64_t agl:1; 7416 uint64_t ptp:1; 7417 uint64_t pem0:1; 7418 uint64_t pem1:1; 7419 uint64_t srio0:1; 7420 uint64_t reserved_51_51:1; 7421 uint64_t lmc0:1; 7422 uint64_t reserved_53_55:3; 7423 uint64_t dfm:1; 7424 uint64_t reserved_57_59:3; 7425 uint64_t srio2:1; 7426 uint64_t srio3:1; 7427 uint64_t reserved_62_62:1; 7428 uint64_t rst:1; 7429 #endif 7430 } cn66xx; 7431 struct cvmx_ciu_int_sum1_cnf71xx { 7432 #ifdef __BIG_ENDIAN_BITFIELD 7433 uint64_t rst:1; 7434 uint64_t reserved_53_62:10; 7435 uint64_t lmc0:1; 7436 uint64_t reserved_50_51:2; 7437 uint64_t pem1:1; 7438 uint64_t pem0:1; 7439 uint64_t ptp:1; 7440 uint64_t reserved_37_46:10; 7441 uint64_t agx0:1; 7442 uint64_t dpi:1; 7443 uint64_t sli:1; 7444 uint64_t usb:1; 7445 uint64_t reserved_32_32:1; 7446 uint64_t key:1; 7447 uint64_t rad:1; 7448 uint64_t tim:1; 7449 uint64_t reserved_28_28:1; 7450 uint64_t pko:1; 7451 uint64_t pip:1; 7452 uint64_t ipd:1; 7453 uint64_t l2c:1; 7454 uint64_t pow:1; 7455 uint64_t fpa:1; 7456 uint64_t iob:1; 7457 uint64_t mio:1; 7458 uint64_t nand:1; 7459 uint64_t reserved_4_18:15; 7460 uint64_t wdog:4; 7461 #else 7462 uint64_t wdog:4; 7463 uint64_t reserved_4_18:15; 7464 uint64_t nand:1; 7465 uint64_t mio:1; 7466 uint64_t iob:1; 7467 uint64_t fpa:1; 7468 uint64_t pow:1; 7469 uint64_t l2c:1; 7470 uint64_t ipd:1; 7471 uint64_t pip:1; 7472 uint64_t pko:1; 7473 uint64_t reserved_28_28:1; 7474 uint64_t tim:1; 7475 uint64_t rad:1; 7476 uint64_t key:1; 7477 uint64_t reserved_32_32:1; 7478 uint64_t usb:1; 7479 uint64_t sli:1; 7480 uint64_t dpi:1; 7481 uint64_t agx0:1; 7482 uint64_t reserved_37_46:10; 7483 uint64_t ptp:1; 7484 uint64_t pem0:1; 7485 uint64_t pem1:1; 7486 uint64_t reserved_50_51:2; 7487 uint64_t lmc0:1; 7488 uint64_t reserved_53_62:10; 7489 uint64_t rst:1; 7490 #endif 7491 } cnf71xx; 7492 }; 7493 7494 union cvmx_ciu_mbox_clrx { 7495 uint64_t u64; 7496 struct cvmx_ciu_mbox_clrx_s { 7497 #ifdef __BIG_ENDIAN_BITFIELD 7498 uint64_t reserved_32_63:32; 7499 uint64_t bits:32; 7500 #else 7501 uint64_t bits:32; 7502 uint64_t reserved_32_63:32; 7503 #endif 7504 } s; 7505 struct cvmx_ciu_mbox_clrx_s cn30xx; 7506 struct cvmx_ciu_mbox_clrx_s cn31xx; 7507 struct cvmx_ciu_mbox_clrx_s cn38xx; 7508 struct cvmx_ciu_mbox_clrx_s cn38xxp2; 7509 struct cvmx_ciu_mbox_clrx_s cn50xx; 7510 struct cvmx_ciu_mbox_clrx_s cn52xx; 7511 struct cvmx_ciu_mbox_clrx_s cn52xxp1; 7512 struct cvmx_ciu_mbox_clrx_s cn56xx; 7513 struct cvmx_ciu_mbox_clrx_s cn56xxp1; 7514 struct cvmx_ciu_mbox_clrx_s cn58xx; 7515 struct cvmx_ciu_mbox_clrx_s cn58xxp1; 7516 struct cvmx_ciu_mbox_clrx_s cn61xx; 7517 struct cvmx_ciu_mbox_clrx_s cn63xx; 7518 struct cvmx_ciu_mbox_clrx_s cn63xxp1; 7519 struct cvmx_ciu_mbox_clrx_s cn66xx; 7520 struct cvmx_ciu_mbox_clrx_s cn68xx; 7521 struct cvmx_ciu_mbox_clrx_s cn68xxp1; 7522 struct cvmx_ciu_mbox_clrx_s cnf71xx; 7523 }; 7524 7525 union cvmx_ciu_mbox_setx { 7526 uint64_t u64; 7527 struct cvmx_ciu_mbox_setx_s { 7528 #ifdef __BIG_ENDIAN_BITFIELD 7529 uint64_t reserved_32_63:32; 7530 uint64_t bits:32; 7531 #else 7532 uint64_t bits:32; 7533 uint64_t reserved_32_63:32; 7534 #endif 7535 } s; 7536 struct cvmx_ciu_mbox_setx_s cn30xx; 7537 struct cvmx_ciu_mbox_setx_s cn31xx; 7538 struct cvmx_ciu_mbox_setx_s cn38xx; 7539 struct cvmx_ciu_mbox_setx_s cn38xxp2; 7540 struct cvmx_ciu_mbox_setx_s cn50xx; 7541 struct cvmx_ciu_mbox_setx_s cn52xx; 7542 struct cvmx_ciu_mbox_setx_s cn52xxp1; 7543 struct cvmx_ciu_mbox_setx_s cn56xx; 7544 struct cvmx_ciu_mbox_setx_s cn56xxp1; 7545 struct cvmx_ciu_mbox_setx_s cn58xx; 7546 struct cvmx_ciu_mbox_setx_s cn58xxp1; 7547 struct cvmx_ciu_mbox_setx_s cn61xx; 7548 struct cvmx_ciu_mbox_setx_s cn63xx; 7549 struct cvmx_ciu_mbox_setx_s cn63xxp1; 7550 struct cvmx_ciu_mbox_setx_s cn66xx; 7551 struct cvmx_ciu_mbox_setx_s cn68xx; 7552 struct cvmx_ciu_mbox_setx_s cn68xxp1; 7553 struct cvmx_ciu_mbox_setx_s cnf71xx; 7554 }; 7555 7556 union cvmx_ciu_nmi { 7557 uint64_t u64; 7558 struct cvmx_ciu_nmi_s { 7559 #ifdef __BIG_ENDIAN_BITFIELD 7560 uint64_t reserved_32_63:32; 7561 uint64_t nmi:32; 7562 #else 7563 uint64_t nmi:32; 7564 uint64_t reserved_32_63:32; 7565 #endif 7566 } s; 7567 struct cvmx_ciu_nmi_cn30xx { 7568 #ifdef __BIG_ENDIAN_BITFIELD 7569 uint64_t reserved_1_63:63; 7570 uint64_t nmi:1; 7571 #else 7572 uint64_t nmi:1; 7573 uint64_t reserved_1_63:63; 7574 #endif 7575 } cn30xx; 7576 struct cvmx_ciu_nmi_cn31xx { 7577 #ifdef __BIG_ENDIAN_BITFIELD 7578 uint64_t reserved_2_63:62; 7579 uint64_t nmi:2; 7580 #else 7581 uint64_t nmi:2; 7582 uint64_t reserved_2_63:62; 7583 #endif 7584 } cn31xx; 7585 struct cvmx_ciu_nmi_cn38xx { 7586 #ifdef __BIG_ENDIAN_BITFIELD 7587 uint64_t reserved_16_63:48; 7588 uint64_t nmi:16; 7589 #else 7590 uint64_t nmi:16; 7591 uint64_t reserved_16_63:48; 7592 #endif 7593 } cn38xx; 7594 struct cvmx_ciu_nmi_cn38xx cn38xxp2; 7595 struct cvmx_ciu_nmi_cn31xx cn50xx; 7596 struct cvmx_ciu_nmi_cn52xx { 7597 #ifdef __BIG_ENDIAN_BITFIELD 7598 uint64_t reserved_4_63:60; 7599 uint64_t nmi:4; 7600 #else 7601 uint64_t nmi:4; 7602 uint64_t reserved_4_63:60; 7603 #endif 7604 } cn52xx; 7605 struct cvmx_ciu_nmi_cn52xx cn52xxp1; 7606 struct cvmx_ciu_nmi_cn56xx { 7607 #ifdef __BIG_ENDIAN_BITFIELD 7608 uint64_t reserved_12_63:52; 7609 uint64_t nmi:12; 7610 #else 7611 uint64_t nmi:12; 7612 uint64_t reserved_12_63:52; 7613 #endif 7614 } cn56xx; 7615 struct cvmx_ciu_nmi_cn56xx cn56xxp1; 7616 struct cvmx_ciu_nmi_cn38xx cn58xx; 7617 struct cvmx_ciu_nmi_cn38xx cn58xxp1; 7618 struct cvmx_ciu_nmi_cn52xx cn61xx; 7619 struct cvmx_ciu_nmi_cn63xx { 7620 #ifdef __BIG_ENDIAN_BITFIELD 7621 uint64_t reserved_6_63:58; 7622 uint64_t nmi:6; 7623 #else 7624 uint64_t nmi:6; 7625 uint64_t reserved_6_63:58; 7626 #endif 7627 } cn63xx; 7628 struct cvmx_ciu_nmi_cn63xx cn63xxp1; 7629 struct cvmx_ciu_nmi_cn66xx { 7630 #ifdef __BIG_ENDIAN_BITFIELD 7631 uint64_t reserved_10_63:54; 7632 uint64_t nmi:10; 7633 #else 7634 uint64_t nmi:10; 7635 uint64_t reserved_10_63:54; 7636 #endif 7637 } cn66xx; 7638 struct cvmx_ciu_nmi_s cn68xx; 7639 struct cvmx_ciu_nmi_s cn68xxp1; 7640 struct cvmx_ciu_nmi_cn52xx cnf71xx; 7641 }; 7642 7643 union cvmx_ciu_pci_inta { 7644 uint64_t u64; 7645 struct cvmx_ciu_pci_inta_s { 7646 #ifdef __BIG_ENDIAN_BITFIELD 7647 uint64_t reserved_2_63:62; 7648 uint64_t intr:2; 7649 #else 7650 uint64_t intr:2; 7651 uint64_t reserved_2_63:62; 7652 #endif 7653 } s; 7654 struct cvmx_ciu_pci_inta_s cn30xx; 7655 struct cvmx_ciu_pci_inta_s cn31xx; 7656 struct cvmx_ciu_pci_inta_s cn38xx; 7657 struct cvmx_ciu_pci_inta_s cn38xxp2; 7658 struct cvmx_ciu_pci_inta_s cn50xx; 7659 struct cvmx_ciu_pci_inta_s cn52xx; 7660 struct cvmx_ciu_pci_inta_s cn52xxp1; 7661 struct cvmx_ciu_pci_inta_s cn56xx; 7662 struct cvmx_ciu_pci_inta_s cn56xxp1; 7663 struct cvmx_ciu_pci_inta_s cn58xx; 7664 struct cvmx_ciu_pci_inta_s cn58xxp1; 7665 struct cvmx_ciu_pci_inta_s cn61xx; 7666 struct cvmx_ciu_pci_inta_s cn63xx; 7667 struct cvmx_ciu_pci_inta_s cn63xxp1; 7668 struct cvmx_ciu_pci_inta_s cn66xx; 7669 struct cvmx_ciu_pci_inta_s cn68xx; 7670 struct cvmx_ciu_pci_inta_s cn68xxp1; 7671 struct cvmx_ciu_pci_inta_s cnf71xx; 7672 }; 7673 7674 union cvmx_ciu_pp_bist_stat { 7675 uint64_t u64; 7676 struct cvmx_ciu_pp_bist_stat_s { 7677 #ifdef __BIG_ENDIAN_BITFIELD 7678 uint64_t reserved_32_63:32; 7679 uint64_t pp_bist:32; 7680 #else 7681 uint64_t pp_bist:32; 7682 uint64_t reserved_32_63:32; 7683 #endif 7684 } s; 7685 struct cvmx_ciu_pp_bist_stat_s cn68xx; 7686 struct cvmx_ciu_pp_bist_stat_s cn68xxp1; 7687 }; 7688 7689 union cvmx_ciu_pp_dbg { 7690 uint64_t u64; 7691 struct cvmx_ciu_pp_dbg_s { 7692 #ifdef __BIG_ENDIAN_BITFIELD 7693 uint64_t reserved_32_63:32; 7694 uint64_t ppdbg:32; 7695 #else 7696 uint64_t ppdbg:32; 7697 uint64_t reserved_32_63:32; 7698 #endif 7699 } s; 7700 struct cvmx_ciu_pp_dbg_cn30xx { 7701 #ifdef __BIG_ENDIAN_BITFIELD 7702 uint64_t reserved_1_63:63; 7703 uint64_t ppdbg:1; 7704 #else 7705 uint64_t ppdbg:1; 7706 uint64_t reserved_1_63:63; 7707 #endif 7708 } cn30xx; 7709 struct cvmx_ciu_pp_dbg_cn31xx { 7710 #ifdef __BIG_ENDIAN_BITFIELD 7711 uint64_t reserved_2_63:62; 7712 uint64_t ppdbg:2; 7713 #else 7714 uint64_t ppdbg:2; 7715 uint64_t reserved_2_63:62; 7716 #endif 7717 } cn31xx; 7718 struct cvmx_ciu_pp_dbg_cn38xx { 7719 #ifdef __BIG_ENDIAN_BITFIELD 7720 uint64_t reserved_16_63:48; 7721 uint64_t ppdbg:16; 7722 #else 7723 uint64_t ppdbg:16; 7724 uint64_t reserved_16_63:48; 7725 #endif 7726 } cn38xx; 7727 struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2; 7728 struct cvmx_ciu_pp_dbg_cn31xx cn50xx; 7729 struct cvmx_ciu_pp_dbg_cn52xx { 7730 #ifdef __BIG_ENDIAN_BITFIELD 7731 uint64_t reserved_4_63:60; 7732 uint64_t ppdbg:4; 7733 #else 7734 uint64_t ppdbg:4; 7735 uint64_t reserved_4_63:60; 7736 #endif 7737 } cn52xx; 7738 struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; 7739 struct cvmx_ciu_pp_dbg_cn56xx { 7740 #ifdef __BIG_ENDIAN_BITFIELD 7741 uint64_t reserved_12_63:52; 7742 uint64_t ppdbg:12; 7743 #else 7744 uint64_t ppdbg:12; 7745 uint64_t reserved_12_63:52; 7746 #endif 7747 } cn56xx; 7748 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; 7749 struct cvmx_ciu_pp_dbg_cn38xx cn58xx; 7750 struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1; 7751 struct cvmx_ciu_pp_dbg_cn52xx cn61xx; 7752 struct cvmx_ciu_pp_dbg_cn63xx { 7753 #ifdef __BIG_ENDIAN_BITFIELD 7754 uint64_t reserved_6_63:58; 7755 uint64_t ppdbg:6; 7756 #else 7757 uint64_t ppdbg:6; 7758 uint64_t reserved_6_63:58; 7759 #endif 7760 } cn63xx; 7761 struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1; 7762 struct cvmx_ciu_pp_dbg_cn66xx { 7763 #ifdef __BIG_ENDIAN_BITFIELD 7764 uint64_t reserved_10_63:54; 7765 uint64_t ppdbg:10; 7766 #else 7767 uint64_t ppdbg:10; 7768 uint64_t reserved_10_63:54; 7769 #endif 7770 } cn66xx; 7771 struct cvmx_ciu_pp_dbg_s cn68xx; 7772 struct cvmx_ciu_pp_dbg_s cn68xxp1; 7773 struct cvmx_ciu_pp_dbg_cn52xx cnf71xx; 7774 }; 7775 7776 union cvmx_ciu_pp_pokex { 7777 uint64_t u64; 7778 struct cvmx_ciu_pp_pokex_s { 7779 #ifdef __BIG_ENDIAN_BITFIELD 7780 uint64_t poke:64; 7781 #else 7782 uint64_t poke:64; 7783 #endif 7784 } s; 7785 struct cvmx_ciu_pp_pokex_s cn30xx; 7786 struct cvmx_ciu_pp_pokex_s cn31xx; 7787 struct cvmx_ciu_pp_pokex_s cn38xx; 7788 struct cvmx_ciu_pp_pokex_s cn38xxp2; 7789 struct cvmx_ciu_pp_pokex_s cn50xx; 7790 struct cvmx_ciu_pp_pokex_s cn52xx; 7791 struct cvmx_ciu_pp_pokex_s cn52xxp1; 7792 struct cvmx_ciu_pp_pokex_s cn56xx; 7793 struct cvmx_ciu_pp_pokex_s cn56xxp1; 7794 struct cvmx_ciu_pp_pokex_s cn58xx; 7795 struct cvmx_ciu_pp_pokex_s cn58xxp1; 7796 struct cvmx_ciu_pp_pokex_s cn61xx; 7797 struct cvmx_ciu_pp_pokex_s cn63xx; 7798 struct cvmx_ciu_pp_pokex_s cn63xxp1; 7799 struct cvmx_ciu_pp_pokex_s cn66xx; 7800 struct cvmx_ciu_pp_pokex_s cn68xx; 7801 struct cvmx_ciu_pp_pokex_s cn68xxp1; 7802 struct cvmx_ciu_pp_pokex_s cnf71xx; 7803 }; 7804 7805 union cvmx_ciu_pp_rst { 7806 uint64_t u64; 7807 struct cvmx_ciu_pp_rst_s { 7808 #ifdef __BIG_ENDIAN_BITFIELD 7809 uint64_t reserved_32_63:32; 7810 uint64_t rst:31; 7811 uint64_t rst0:1; 7812 #else 7813 uint64_t rst0:1; 7814 uint64_t rst:31; 7815 uint64_t reserved_32_63:32; 7816 #endif 7817 } s; 7818 struct cvmx_ciu_pp_rst_cn30xx { 7819 #ifdef __BIG_ENDIAN_BITFIELD 7820 uint64_t reserved_1_63:63; 7821 uint64_t rst0:1; 7822 #else 7823 uint64_t rst0:1; 7824 uint64_t reserved_1_63:63; 7825 #endif 7826 } cn30xx; 7827 struct cvmx_ciu_pp_rst_cn31xx { 7828 #ifdef __BIG_ENDIAN_BITFIELD 7829 uint64_t reserved_2_63:62; 7830 uint64_t rst:1; 7831 uint64_t rst0:1; 7832 #else 7833 uint64_t rst0:1; 7834 uint64_t rst:1; 7835 uint64_t reserved_2_63:62; 7836 #endif 7837 } cn31xx; 7838 struct cvmx_ciu_pp_rst_cn38xx { 7839 #ifdef __BIG_ENDIAN_BITFIELD 7840 uint64_t reserved_16_63:48; 7841 uint64_t rst:15; 7842 uint64_t rst0:1; 7843 #else 7844 uint64_t rst0:1; 7845 uint64_t rst:15; 7846 uint64_t reserved_16_63:48; 7847 #endif 7848 } cn38xx; 7849 struct cvmx_ciu_pp_rst_cn38xx cn38xxp2; 7850 struct cvmx_ciu_pp_rst_cn31xx cn50xx; 7851 struct cvmx_ciu_pp_rst_cn52xx { 7852 #ifdef __BIG_ENDIAN_BITFIELD 7853 uint64_t reserved_4_63:60; 7854 uint64_t rst:3; 7855 uint64_t rst0:1; 7856 #else 7857 uint64_t rst0:1; 7858 uint64_t rst:3; 7859 uint64_t reserved_4_63:60; 7860 #endif 7861 } cn52xx; 7862 struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; 7863 struct cvmx_ciu_pp_rst_cn56xx { 7864 #ifdef __BIG_ENDIAN_BITFIELD 7865 uint64_t reserved_12_63:52; 7866 uint64_t rst:11; 7867 uint64_t rst0:1; 7868 #else 7869 uint64_t rst0:1; 7870 uint64_t rst:11; 7871 uint64_t reserved_12_63:52; 7872 #endif 7873 } cn56xx; 7874 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; 7875 struct cvmx_ciu_pp_rst_cn38xx cn58xx; 7876 struct cvmx_ciu_pp_rst_cn38xx cn58xxp1; 7877 struct cvmx_ciu_pp_rst_cn52xx cn61xx; 7878 struct cvmx_ciu_pp_rst_cn63xx { 7879 #ifdef __BIG_ENDIAN_BITFIELD 7880 uint64_t reserved_6_63:58; 7881 uint64_t rst:5; 7882 uint64_t rst0:1; 7883 #else 7884 uint64_t rst0:1; 7885 uint64_t rst:5; 7886 uint64_t reserved_6_63:58; 7887 #endif 7888 } cn63xx; 7889 struct cvmx_ciu_pp_rst_cn63xx cn63xxp1; 7890 struct cvmx_ciu_pp_rst_cn66xx { 7891 #ifdef __BIG_ENDIAN_BITFIELD 7892 uint64_t reserved_10_63:54; 7893 uint64_t rst:9; 7894 uint64_t rst0:1; 7895 #else 7896 uint64_t rst0:1; 7897 uint64_t rst:9; 7898 uint64_t reserved_10_63:54; 7899 #endif 7900 } cn66xx; 7901 struct cvmx_ciu_pp_rst_s cn68xx; 7902 struct cvmx_ciu_pp_rst_s cn68xxp1; 7903 struct cvmx_ciu_pp_rst_cn52xx cnf71xx; 7904 }; 7905 7906 union cvmx_ciu_qlm0 { 7907 uint64_t u64; 7908 struct cvmx_ciu_qlm0_s { 7909 #ifdef __BIG_ENDIAN_BITFIELD 7910 uint64_t g2bypass:1; 7911 uint64_t reserved_53_62:10; 7912 uint64_t g2deemph:5; 7913 uint64_t reserved_45_47:3; 7914 uint64_t g2margin:5; 7915 uint64_t reserved_32_39:8; 7916 uint64_t txbypass:1; 7917 uint64_t reserved_21_30:10; 7918 uint64_t txdeemph:5; 7919 uint64_t reserved_13_15:3; 7920 uint64_t txmargin:5; 7921 uint64_t reserved_4_7:4; 7922 uint64_t lane_en:4; 7923 #else 7924 uint64_t lane_en:4; 7925 uint64_t reserved_4_7:4; 7926 uint64_t txmargin:5; 7927 uint64_t reserved_13_15:3; 7928 uint64_t txdeemph:5; 7929 uint64_t reserved_21_30:10; 7930 uint64_t txbypass:1; 7931 uint64_t reserved_32_39:8; 7932 uint64_t g2margin:5; 7933 uint64_t reserved_45_47:3; 7934 uint64_t g2deemph:5; 7935 uint64_t reserved_53_62:10; 7936 uint64_t g2bypass:1; 7937 #endif 7938 } s; 7939 struct cvmx_ciu_qlm0_s cn61xx; 7940 struct cvmx_ciu_qlm0_s cn63xx; 7941 struct cvmx_ciu_qlm0_cn63xxp1 { 7942 #ifdef __BIG_ENDIAN_BITFIELD 7943 uint64_t reserved_32_63:32; 7944 uint64_t txbypass:1; 7945 uint64_t reserved_20_30:11; 7946 uint64_t txdeemph:4; 7947 uint64_t reserved_13_15:3; 7948 uint64_t txmargin:5; 7949 uint64_t reserved_4_7:4; 7950 uint64_t lane_en:4; 7951 #else 7952 uint64_t lane_en:4; 7953 uint64_t reserved_4_7:4; 7954 uint64_t txmargin:5; 7955 uint64_t reserved_13_15:3; 7956 uint64_t txdeemph:4; 7957 uint64_t reserved_20_30:11; 7958 uint64_t txbypass:1; 7959 uint64_t reserved_32_63:32; 7960 #endif 7961 } cn63xxp1; 7962 struct cvmx_ciu_qlm0_s cn66xx; 7963 struct cvmx_ciu_qlm0_cn68xx { 7964 #ifdef __BIG_ENDIAN_BITFIELD 7965 uint64_t reserved_32_63:32; 7966 uint64_t txbypass:1; 7967 uint64_t reserved_21_30:10; 7968 uint64_t txdeemph:5; 7969 uint64_t reserved_13_15:3; 7970 uint64_t txmargin:5; 7971 uint64_t reserved_4_7:4; 7972 uint64_t lane_en:4; 7973 #else 7974 uint64_t lane_en:4; 7975 uint64_t reserved_4_7:4; 7976 uint64_t txmargin:5; 7977 uint64_t reserved_13_15:3; 7978 uint64_t txdeemph:5; 7979 uint64_t reserved_21_30:10; 7980 uint64_t txbypass:1; 7981 uint64_t reserved_32_63:32; 7982 #endif 7983 } cn68xx; 7984 struct cvmx_ciu_qlm0_cn68xx cn68xxp1; 7985 struct cvmx_ciu_qlm0_s cnf71xx; 7986 }; 7987 7988 union cvmx_ciu_qlm1 { 7989 uint64_t u64; 7990 struct cvmx_ciu_qlm1_s { 7991 #ifdef __BIG_ENDIAN_BITFIELD 7992 uint64_t g2bypass:1; 7993 uint64_t reserved_53_62:10; 7994 uint64_t g2deemph:5; 7995 uint64_t reserved_45_47:3; 7996 uint64_t g2margin:5; 7997 uint64_t reserved_32_39:8; 7998 uint64_t txbypass:1; 7999 uint64_t reserved_21_30:10; 8000 uint64_t txdeemph:5; 8001 uint64_t reserved_13_15:3; 8002 uint64_t txmargin:5; 8003 uint64_t reserved_4_7:4; 8004 uint64_t lane_en:4; 8005 #else 8006 uint64_t lane_en:4; 8007 uint64_t reserved_4_7:4; 8008 uint64_t txmargin:5; 8009 uint64_t reserved_13_15:3; 8010 uint64_t txdeemph:5; 8011 uint64_t reserved_21_30:10; 8012 uint64_t txbypass:1; 8013 uint64_t reserved_32_39:8; 8014 uint64_t g2margin:5; 8015 uint64_t reserved_45_47:3; 8016 uint64_t g2deemph:5; 8017 uint64_t reserved_53_62:10; 8018 uint64_t g2bypass:1; 8019 #endif 8020 } s; 8021 struct cvmx_ciu_qlm1_s cn61xx; 8022 struct cvmx_ciu_qlm1_s cn63xx; 8023 struct cvmx_ciu_qlm1_cn63xxp1 { 8024 #ifdef __BIG_ENDIAN_BITFIELD 8025 uint64_t reserved_32_63:32; 8026 uint64_t txbypass:1; 8027 uint64_t reserved_20_30:11; 8028 uint64_t txdeemph:4; 8029 uint64_t reserved_13_15:3; 8030 uint64_t txmargin:5; 8031 uint64_t reserved_4_7:4; 8032 uint64_t lane_en:4; 8033 #else 8034 uint64_t lane_en:4; 8035 uint64_t reserved_4_7:4; 8036 uint64_t txmargin:5; 8037 uint64_t reserved_13_15:3; 8038 uint64_t txdeemph:4; 8039 uint64_t reserved_20_30:11; 8040 uint64_t txbypass:1; 8041 uint64_t reserved_32_63:32; 8042 #endif 8043 } cn63xxp1; 8044 struct cvmx_ciu_qlm1_s cn66xx; 8045 struct cvmx_ciu_qlm1_s cn68xx; 8046 struct cvmx_ciu_qlm1_s cn68xxp1; 8047 struct cvmx_ciu_qlm1_s cnf71xx; 8048 }; 8049 8050 union cvmx_ciu_qlm2 { 8051 uint64_t u64; 8052 struct cvmx_ciu_qlm2_s { 8053 #ifdef __BIG_ENDIAN_BITFIELD 8054 uint64_t g2bypass:1; 8055 uint64_t reserved_53_62:10; 8056 uint64_t g2deemph:5; 8057 uint64_t reserved_45_47:3; 8058 uint64_t g2margin:5; 8059 uint64_t reserved_32_39:8; 8060 uint64_t txbypass:1; 8061 uint64_t reserved_21_30:10; 8062 uint64_t txdeemph:5; 8063 uint64_t reserved_13_15:3; 8064 uint64_t txmargin:5; 8065 uint64_t reserved_4_7:4; 8066 uint64_t lane_en:4; 8067 #else 8068 uint64_t lane_en:4; 8069 uint64_t reserved_4_7:4; 8070 uint64_t txmargin:5; 8071 uint64_t reserved_13_15:3; 8072 uint64_t txdeemph:5; 8073 uint64_t reserved_21_30:10; 8074 uint64_t txbypass:1; 8075 uint64_t reserved_32_39:8; 8076 uint64_t g2margin:5; 8077 uint64_t reserved_45_47:3; 8078 uint64_t g2deemph:5; 8079 uint64_t reserved_53_62:10; 8080 uint64_t g2bypass:1; 8081 #endif 8082 } s; 8083 struct cvmx_ciu_qlm2_cn61xx { 8084 #ifdef __BIG_ENDIAN_BITFIELD 8085 uint64_t reserved_32_63:32; 8086 uint64_t txbypass:1; 8087 uint64_t reserved_21_30:10; 8088 uint64_t txdeemph:5; 8089 uint64_t reserved_13_15:3; 8090 uint64_t txmargin:5; 8091 uint64_t reserved_4_7:4; 8092 uint64_t lane_en:4; 8093 #else 8094 uint64_t lane_en:4; 8095 uint64_t reserved_4_7:4; 8096 uint64_t txmargin:5; 8097 uint64_t reserved_13_15:3; 8098 uint64_t txdeemph:5; 8099 uint64_t reserved_21_30:10; 8100 uint64_t txbypass:1; 8101 uint64_t reserved_32_63:32; 8102 #endif 8103 } cn61xx; 8104 struct cvmx_ciu_qlm2_cn61xx cn63xx; 8105 struct cvmx_ciu_qlm2_cn63xxp1 { 8106 #ifdef __BIG_ENDIAN_BITFIELD 8107 uint64_t reserved_32_63:32; 8108 uint64_t txbypass:1; 8109 uint64_t reserved_20_30:11; 8110 uint64_t txdeemph:4; 8111 uint64_t reserved_13_15:3; 8112 uint64_t txmargin:5; 8113 uint64_t reserved_4_7:4; 8114 uint64_t lane_en:4; 8115 #else 8116 uint64_t lane_en:4; 8117 uint64_t reserved_4_7:4; 8118 uint64_t txmargin:5; 8119 uint64_t reserved_13_15:3; 8120 uint64_t txdeemph:4; 8121 uint64_t reserved_20_30:11; 8122 uint64_t txbypass:1; 8123 uint64_t reserved_32_63:32; 8124 #endif 8125 } cn63xxp1; 8126 struct cvmx_ciu_qlm2_cn61xx cn66xx; 8127 struct cvmx_ciu_qlm2_s cn68xx; 8128 struct cvmx_ciu_qlm2_s cn68xxp1; 8129 struct cvmx_ciu_qlm2_cn61xx cnf71xx; 8130 }; 8131 8132 union cvmx_ciu_qlm3 { 8133 uint64_t u64; 8134 struct cvmx_ciu_qlm3_s { 8135 #ifdef __BIG_ENDIAN_BITFIELD 8136 uint64_t g2bypass:1; 8137 uint64_t reserved_53_62:10; 8138 uint64_t g2deemph:5; 8139 uint64_t reserved_45_47:3; 8140 uint64_t g2margin:5; 8141 uint64_t reserved_32_39:8; 8142 uint64_t txbypass:1; 8143 uint64_t reserved_21_30:10; 8144 uint64_t txdeemph:5; 8145 uint64_t reserved_13_15:3; 8146 uint64_t txmargin:5; 8147 uint64_t reserved_4_7:4; 8148 uint64_t lane_en:4; 8149 #else 8150 uint64_t lane_en:4; 8151 uint64_t reserved_4_7:4; 8152 uint64_t txmargin:5; 8153 uint64_t reserved_13_15:3; 8154 uint64_t txdeemph:5; 8155 uint64_t reserved_21_30:10; 8156 uint64_t txbypass:1; 8157 uint64_t reserved_32_39:8; 8158 uint64_t g2margin:5; 8159 uint64_t reserved_45_47:3; 8160 uint64_t g2deemph:5; 8161 uint64_t reserved_53_62:10; 8162 uint64_t g2bypass:1; 8163 #endif 8164 } s; 8165 struct cvmx_ciu_qlm3_s cn68xx; 8166 struct cvmx_ciu_qlm3_s cn68xxp1; 8167 }; 8168 8169 union cvmx_ciu_qlm4 { 8170 uint64_t u64; 8171 struct cvmx_ciu_qlm4_s { 8172 #ifdef __BIG_ENDIAN_BITFIELD 8173 uint64_t g2bypass:1; 8174 uint64_t reserved_53_62:10; 8175 uint64_t g2deemph:5; 8176 uint64_t reserved_45_47:3; 8177 uint64_t g2margin:5; 8178 uint64_t reserved_32_39:8; 8179 uint64_t txbypass:1; 8180 uint64_t reserved_21_30:10; 8181 uint64_t txdeemph:5; 8182 uint64_t reserved_13_15:3; 8183 uint64_t txmargin:5; 8184 uint64_t reserved_4_7:4; 8185 uint64_t lane_en:4; 8186 #else 8187 uint64_t lane_en:4; 8188 uint64_t reserved_4_7:4; 8189 uint64_t txmargin:5; 8190 uint64_t reserved_13_15:3; 8191 uint64_t txdeemph:5; 8192 uint64_t reserved_21_30:10; 8193 uint64_t txbypass:1; 8194 uint64_t reserved_32_39:8; 8195 uint64_t g2margin:5; 8196 uint64_t reserved_45_47:3; 8197 uint64_t g2deemph:5; 8198 uint64_t reserved_53_62:10; 8199 uint64_t g2bypass:1; 8200 #endif 8201 } s; 8202 struct cvmx_ciu_qlm4_s cn68xx; 8203 struct cvmx_ciu_qlm4_s cn68xxp1; 8204 }; 8205 8206 union cvmx_ciu_qlm_dcok { 8207 uint64_t u64; 8208 struct cvmx_ciu_qlm_dcok_s { 8209 #ifdef __BIG_ENDIAN_BITFIELD 8210 uint64_t reserved_4_63:60; 8211 uint64_t qlm_dcok:4; 8212 #else 8213 uint64_t qlm_dcok:4; 8214 uint64_t reserved_4_63:60; 8215 #endif 8216 } s; 8217 struct cvmx_ciu_qlm_dcok_cn52xx { 8218 #ifdef __BIG_ENDIAN_BITFIELD 8219 uint64_t reserved_2_63:62; 8220 uint64_t qlm_dcok:2; 8221 #else 8222 uint64_t qlm_dcok:2; 8223 uint64_t reserved_2_63:62; 8224 #endif 8225 } cn52xx; 8226 struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; 8227 struct cvmx_ciu_qlm_dcok_s cn56xx; 8228 struct cvmx_ciu_qlm_dcok_s cn56xxp1; 8229 }; 8230 8231 union cvmx_ciu_qlm_jtgc { 8232 uint64_t u64; 8233 struct cvmx_ciu_qlm_jtgc_s { 8234 #ifdef __BIG_ENDIAN_BITFIELD 8235 uint64_t reserved_17_63:47; 8236 uint64_t bypass_ext:1; 8237 uint64_t reserved_11_15:5; 8238 uint64_t clk_div:3; 8239 uint64_t reserved_7_7:1; 8240 uint64_t mux_sel:3; 8241 uint64_t bypass:4; 8242 #else 8243 uint64_t bypass:4; 8244 uint64_t mux_sel:3; 8245 uint64_t reserved_7_7:1; 8246 uint64_t clk_div:3; 8247 uint64_t reserved_11_15:5; 8248 uint64_t bypass_ext:1; 8249 uint64_t reserved_17_63:47; 8250 #endif 8251 } s; 8252 struct cvmx_ciu_qlm_jtgc_cn52xx { 8253 #ifdef __BIG_ENDIAN_BITFIELD 8254 uint64_t reserved_11_63:53; 8255 uint64_t clk_div:3; 8256 uint64_t reserved_5_7:3; 8257 uint64_t mux_sel:1; 8258 uint64_t reserved_2_3:2; 8259 uint64_t bypass:2; 8260 #else 8261 uint64_t bypass:2; 8262 uint64_t reserved_2_3:2; 8263 uint64_t mux_sel:1; 8264 uint64_t reserved_5_7:3; 8265 uint64_t clk_div:3; 8266 uint64_t reserved_11_63:53; 8267 #endif 8268 } cn52xx; 8269 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; 8270 struct cvmx_ciu_qlm_jtgc_cn56xx { 8271 #ifdef __BIG_ENDIAN_BITFIELD 8272 uint64_t reserved_11_63:53; 8273 uint64_t clk_div:3; 8274 uint64_t reserved_6_7:2; 8275 uint64_t mux_sel:2; 8276 uint64_t bypass:4; 8277 #else 8278 uint64_t bypass:4; 8279 uint64_t mux_sel:2; 8280 uint64_t reserved_6_7:2; 8281 uint64_t clk_div:3; 8282 uint64_t reserved_11_63:53; 8283 #endif 8284 } cn56xx; 8285 struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1; 8286 struct cvmx_ciu_qlm_jtgc_cn61xx { 8287 #ifdef __BIG_ENDIAN_BITFIELD 8288 uint64_t reserved_11_63:53; 8289 uint64_t clk_div:3; 8290 uint64_t reserved_6_7:2; 8291 uint64_t mux_sel:2; 8292 uint64_t reserved_3_3:1; 8293 uint64_t bypass:3; 8294 #else 8295 uint64_t bypass:3; 8296 uint64_t reserved_3_3:1; 8297 uint64_t mux_sel:2; 8298 uint64_t reserved_6_7:2; 8299 uint64_t clk_div:3; 8300 uint64_t reserved_11_63:53; 8301 #endif 8302 } cn61xx; 8303 struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx; 8304 struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1; 8305 struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx; 8306 struct cvmx_ciu_qlm_jtgc_s cn68xx; 8307 struct cvmx_ciu_qlm_jtgc_s cn68xxp1; 8308 struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx; 8309 }; 8310 8311 union cvmx_ciu_qlm_jtgd { 8312 uint64_t u64; 8313 struct cvmx_ciu_qlm_jtgd_s { 8314 #ifdef __BIG_ENDIAN_BITFIELD 8315 uint64_t capture:1; 8316 uint64_t shift:1; 8317 uint64_t update:1; 8318 uint64_t reserved_45_60:16; 8319 uint64_t select:5; 8320 uint64_t reserved_37_39:3; 8321 uint64_t shft_cnt:5; 8322 uint64_t shft_reg:32; 8323 #else 8324 uint64_t shft_reg:32; 8325 uint64_t shft_cnt:5; 8326 uint64_t reserved_37_39:3; 8327 uint64_t select:5; 8328 uint64_t reserved_45_60:16; 8329 uint64_t update:1; 8330 uint64_t shift:1; 8331 uint64_t capture:1; 8332 #endif 8333 } s; 8334 struct cvmx_ciu_qlm_jtgd_cn52xx { 8335 #ifdef __BIG_ENDIAN_BITFIELD 8336 uint64_t capture:1; 8337 uint64_t shift:1; 8338 uint64_t update:1; 8339 uint64_t reserved_42_60:19; 8340 uint64_t select:2; 8341 uint64_t reserved_37_39:3; 8342 uint64_t shft_cnt:5; 8343 uint64_t shft_reg:32; 8344 #else 8345 uint64_t shft_reg:32; 8346 uint64_t shft_cnt:5; 8347 uint64_t reserved_37_39:3; 8348 uint64_t select:2; 8349 uint64_t reserved_42_60:19; 8350 uint64_t update:1; 8351 uint64_t shift:1; 8352 uint64_t capture:1; 8353 #endif 8354 } cn52xx; 8355 struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; 8356 struct cvmx_ciu_qlm_jtgd_cn56xx { 8357 #ifdef __BIG_ENDIAN_BITFIELD 8358 uint64_t capture:1; 8359 uint64_t shift:1; 8360 uint64_t update:1; 8361 uint64_t reserved_44_60:17; 8362 uint64_t select:4; 8363 uint64_t reserved_37_39:3; 8364 uint64_t shft_cnt:5; 8365 uint64_t shft_reg:32; 8366 #else 8367 uint64_t shft_reg:32; 8368 uint64_t shft_cnt:5; 8369 uint64_t reserved_37_39:3; 8370 uint64_t select:4; 8371 uint64_t reserved_44_60:17; 8372 uint64_t update:1; 8373 uint64_t shift:1; 8374 uint64_t capture:1; 8375 #endif 8376 } cn56xx; 8377 struct cvmx_ciu_qlm_jtgd_cn56xxp1 { 8378 #ifdef __BIG_ENDIAN_BITFIELD 8379 uint64_t capture:1; 8380 uint64_t shift:1; 8381 uint64_t update:1; 8382 uint64_t reserved_37_60:24; 8383 uint64_t shft_cnt:5; 8384 uint64_t shft_reg:32; 8385 #else 8386 uint64_t shft_reg:32; 8387 uint64_t shft_cnt:5; 8388 uint64_t reserved_37_60:24; 8389 uint64_t update:1; 8390 uint64_t shift:1; 8391 uint64_t capture:1; 8392 #endif 8393 } cn56xxp1; 8394 struct cvmx_ciu_qlm_jtgd_cn61xx { 8395 #ifdef __BIG_ENDIAN_BITFIELD 8396 uint64_t capture:1; 8397 uint64_t shift:1; 8398 uint64_t update:1; 8399 uint64_t reserved_43_60:18; 8400 uint64_t select:3; 8401 uint64_t reserved_37_39:3; 8402 uint64_t shft_cnt:5; 8403 uint64_t shft_reg:32; 8404 #else 8405 uint64_t shft_reg:32; 8406 uint64_t shft_cnt:5; 8407 uint64_t reserved_37_39:3; 8408 uint64_t select:3; 8409 uint64_t reserved_43_60:18; 8410 uint64_t update:1; 8411 uint64_t shift:1; 8412 uint64_t capture:1; 8413 #endif 8414 } cn61xx; 8415 struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx; 8416 struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1; 8417 struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx; 8418 struct cvmx_ciu_qlm_jtgd_s cn68xx; 8419 struct cvmx_ciu_qlm_jtgd_s cn68xxp1; 8420 struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx; 8421 }; 8422 8423 union cvmx_ciu_soft_bist { 8424 uint64_t u64; 8425 struct cvmx_ciu_soft_bist_s { 8426 #ifdef __BIG_ENDIAN_BITFIELD 8427 uint64_t reserved_1_63:63; 8428 uint64_t soft_bist:1; 8429 #else 8430 uint64_t soft_bist:1; 8431 uint64_t reserved_1_63:63; 8432 #endif 8433 } s; 8434 struct cvmx_ciu_soft_bist_s cn30xx; 8435 struct cvmx_ciu_soft_bist_s cn31xx; 8436 struct cvmx_ciu_soft_bist_s cn38xx; 8437 struct cvmx_ciu_soft_bist_s cn38xxp2; 8438 struct cvmx_ciu_soft_bist_s cn50xx; 8439 struct cvmx_ciu_soft_bist_s cn52xx; 8440 struct cvmx_ciu_soft_bist_s cn52xxp1; 8441 struct cvmx_ciu_soft_bist_s cn56xx; 8442 struct cvmx_ciu_soft_bist_s cn56xxp1; 8443 struct cvmx_ciu_soft_bist_s cn58xx; 8444 struct cvmx_ciu_soft_bist_s cn58xxp1; 8445 struct cvmx_ciu_soft_bist_s cn61xx; 8446 struct cvmx_ciu_soft_bist_s cn63xx; 8447 struct cvmx_ciu_soft_bist_s cn63xxp1; 8448 struct cvmx_ciu_soft_bist_s cn66xx; 8449 struct cvmx_ciu_soft_bist_s cn68xx; 8450 struct cvmx_ciu_soft_bist_s cn68xxp1; 8451 struct cvmx_ciu_soft_bist_s cnf71xx; 8452 }; 8453 8454 union cvmx_ciu_soft_prst { 8455 uint64_t u64; 8456 struct cvmx_ciu_soft_prst_s { 8457 #ifdef __BIG_ENDIAN_BITFIELD 8458 uint64_t reserved_3_63:61; 8459 uint64_t host64:1; 8460 uint64_t npi:1; 8461 uint64_t soft_prst:1; 8462 #else 8463 uint64_t soft_prst:1; 8464 uint64_t npi:1; 8465 uint64_t host64:1; 8466 uint64_t reserved_3_63:61; 8467 #endif 8468 } s; 8469 struct cvmx_ciu_soft_prst_s cn30xx; 8470 struct cvmx_ciu_soft_prst_s cn31xx; 8471 struct cvmx_ciu_soft_prst_s cn38xx; 8472 struct cvmx_ciu_soft_prst_s cn38xxp2; 8473 struct cvmx_ciu_soft_prst_s cn50xx; 8474 struct cvmx_ciu_soft_prst_cn52xx { 8475 #ifdef __BIG_ENDIAN_BITFIELD 8476 uint64_t reserved_1_63:63; 8477 uint64_t soft_prst:1; 8478 #else 8479 uint64_t soft_prst:1; 8480 uint64_t reserved_1_63:63; 8481 #endif 8482 } cn52xx; 8483 struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; 8484 struct cvmx_ciu_soft_prst_cn52xx cn56xx; 8485 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; 8486 struct cvmx_ciu_soft_prst_s cn58xx; 8487 struct cvmx_ciu_soft_prst_s cn58xxp1; 8488 struct cvmx_ciu_soft_prst_cn52xx cn61xx; 8489 struct cvmx_ciu_soft_prst_cn52xx cn63xx; 8490 struct cvmx_ciu_soft_prst_cn52xx cn63xxp1; 8491 struct cvmx_ciu_soft_prst_cn52xx cn66xx; 8492 struct cvmx_ciu_soft_prst_cn52xx cn68xx; 8493 struct cvmx_ciu_soft_prst_cn52xx cn68xxp1; 8494 struct cvmx_ciu_soft_prst_cn52xx cnf71xx; 8495 }; 8496 8497 union cvmx_ciu_soft_prst1 { 8498 uint64_t u64; 8499 struct cvmx_ciu_soft_prst1_s { 8500 #ifdef __BIG_ENDIAN_BITFIELD 8501 uint64_t reserved_1_63:63; 8502 uint64_t soft_prst:1; 8503 #else 8504 uint64_t soft_prst:1; 8505 uint64_t reserved_1_63:63; 8506 #endif 8507 } s; 8508 struct cvmx_ciu_soft_prst1_s cn52xx; 8509 struct cvmx_ciu_soft_prst1_s cn52xxp1; 8510 struct cvmx_ciu_soft_prst1_s cn56xx; 8511 struct cvmx_ciu_soft_prst1_s cn56xxp1; 8512 struct cvmx_ciu_soft_prst1_s cn61xx; 8513 struct cvmx_ciu_soft_prst1_s cn63xx; 8514 struct cvmx_ciu_soft_prst1_s cn63xxp1; 8515 struct cvmx_ciu_soft_prst1_s cn66xx; 8516 struct cvmx_ciu_soft_prst1_s cn68xx; 8517 struct cvmx_ciu_soft_prst1_s cn68xxp1; 8518 struct cvmx_ciu_soft_prst1_s cnf71xx; 8519 }; 8520 8521 union cvmx_ciu_soft_prst2 { 8522 uint64_t u64; 8523 struct cvmx_ciu_soft_prst2_s { 8524 #ifdef __BIG_ENDIAN_BITFIELD 8525 uint64_t reserved_1_63:63; 8526 uint64_t soft_prst:1; 8527 #else 8528 uint64_t soft_prst:1; 8529 uint64_t reserved_1_63:63; 8530 #endif 8531 } s; 8532 struct cvmx_ciu_soft_prst2_s cn66xx; 8533 }; 8534 8535 union cvmx_ciu_soft_prst3 { 8536 uint64_t u64; 8537 struct cvmx_ciu_soft_prst3_s { 8538 #ifdef __BIG_ENDIAN_BITFIELD 8539 uint64_t reserved_1_63:63; 8540 uint64_t soft_prst:1; 8541 #else 8542 uint64_t soft_prst:1; 8543 uint64_t reserved_1_63:63; 8544 #endif 8545 } s; 8546 struct cvmx_ciu_soft_prst3_s cn66xx; 8547 }; 8548 8549 union cvmx_ciu_soft_rst { 8550 uint64_t u64; 8551 struct cvmx_ciu_soft_rst_s { 8552 #ifdef __BIG_ENDIAN_BITFIELD 8553 uint64_t reserved_1_63:63; 8554 uint64_t soft_rst:1; 8555 #else 8556 uint64_t soft_rst:1; 8557 uint64_t reserved_1_63:63; 8558 #endif 8559 } s; 8560 struct cvmx_ciu_soft_rst_s cn30xx; 8561 struct cvmx_ciu_soft_rst_s cn31xx; 8562 struct cvmx_ciu_soft_rst_s cn38xx; 8563 struct cvmx_ciu_soft_rst_s cn38xxp2; 8564 struct cvmx_ciu_soft_rst_s cn50xx; 8565 struct cvmx_ciu_soft_rst_s cn52xx; 8566 struct cvmx_ciu_soft_rst_s cn52xxp1; 8567 struct cvmx_ciu_soft_rst_s cn56xx; 8568 struct cvmx_ciu_soft_rst_s cn56xxp1; 8569 struct cvmx_ciu_soft_rst_s cn58xx; 8570 struct cvmx_ciu_soft_rst_s cn58xxp1; 8571 struct cvmx_ciu_soft_rst_s cn61xx; 8572 struct cvmx_ciu_soft_rst_s cn63xx; 8573 struct cvmx_ciu_soft_rst_s cn63xxp1; 8574 struct cvmx_ciu_soft_rst_s cn66xx; 8575 struct cvmx_ciu_soft_rst_s cn68xx; 8576 struct cvmx_ciu_soft_rst_s cn68xxp1; 8577 struct cvmx_ciu_soft_rst_s cnf71xx; 8578 }; 8579 8580 union cvmx_ciu_sum1_iox_int { 8581 uint64_t u64; 8582 struct cvmx_ciu_sum1_iox_int_s { 8583 #ifdef __BIG_ENDIAN_BITFIELD 8584 uint64_t rst:1; 8585 uint64_t reserved_62_62:1; 8586 uint64_t srio3:1; 8587 uint64_t srio2:1; 8588 uint64_t reserved_57_59:3; 8589 uint64_t dfm:1; 8590 uint64_t reserved_53_55:3; 8591 uint64_t lmc0:1; 8592 uint64_t reserved_51_51:1; 8593 uint64_t srio0:1; 8594 uint64_t pem1:1; 8595 uint64_t pem0:1; 8596 uint64_t ptp:1; 8597 uint64_t agl:1; 8598 uint64_t reserved_41_45:5; 8599 uint64_t dpi_dma:1; 8600 uint64_t reserved_38_39:2; 8601 uint64_t agx1:1; 8602 uint64_t agx0:1; 8603 uint64_t dpi:1; 8604 uint64_t sli:1; 8605 uint64_t usb:1; 8606 uint64_t dfa:1; 8607 uint64_t key:1; 8608 uint64_t rad:1; 8609 uint64_t tim:1; 8610 uint64_t zip:1; 8611 uint64_t pko:1; 8612 uint64_t pip:1; 8613 uint64_t ipd:1; 8614 uint64_t l2c:1; 8615 uint64_t pow:1; 8616 uint64_t fpa:1; 8617 uint64_t iob:1; 8618 uint64_t mio:1; 8619 uint64_t nand:1; 8620 uint64_t mii1:1; 8621 uint64_t reserved_10_17:8; 8622 uint64_t wdog:10; 8623 #else 8624 uint64_t wdog:10; 8625 uint64_t reserved_10_17:8; 8626 uint64_t mii1:1; 8627 uint64_t nand:1; 8628 uint64_t mio:1; 8629 uint64_t iob:1; 8630 uint64_t fpa:1; 8631 uint64_t pow:1; 8632 uint64_t l2c:1; 8633 uint64_t ipd:1; 8634 uint64_t pip:1; 8635 uint64_t pko:1; 8636 uint64_t zip:1; 8637 uint64_t tim:1; 8638 uint64_t rad:1; 8639 uint64_t key:1; 8640 uint64_t dfa:1; 8641 uint64_t usb:1; 8642 uint64_t sli:1; 8643 uint64_t dpi:1; 8644 uint64_t agx0:1; 8645 uint64_t agx1:1; 8646 uint64_t reserved_38_39:2; 8647 uint64_t dpi_dma:1; 8648 uint64_t reserved_41_45:5; 8649 uint64_t agl:1; 8650 uint64_t ptp:1; 8651 uint64_t pem0:1; 8652 uint64_t pem1:1; 8653 uint64_t srio0:1; 8654 uint64_t reserved_51_51:1; 8655 uint64_t lmc0:1; 8656 uint64_t reserved_53_55:3; 8657 uint64_t dfm:1; 8658 uint64_t reserved_57_59:3; 8659 uint64_t srio2:1; 8660 uint64_t srio3:1; 8661 uint64_t reserved_62_62:1; 8662 uint64_t rst:1; 8663 #endif 8664 } s; 8665 struct cvmx_ciu_sum1_iox_int_cn61xx { 8666 #ifdef __BIG_ENDIAN_BITFIELD 8667 uint64_t rst:1; 8668 uint64_t reserved_53_62:10; 8669 uint64_t lmc0:1; 8670 uint64_t reserved_50_51:2; 8671 uint64_t pem1:1; 8672 uint64_t pem0:1; 8673 uint64_t ptp:1; 8674 uint64_t agl:1; 8675 uint64_t reserved_41_45:5; 8676 uint64_t dpi_dma:1; 8677 uint64_t reserved_38_39:2; 8678 uint64_t agx1:1; 8679 uint64_t agx0:1; 8680 uint64_t dpi:1; 8681 uint64_t sli:1; 8682 uint64_t usb:1; 8683 uint64_t dfa:1; 8684 uint64_t key:1; 8685 uint64_t rad:1; 8686 uint64_t tim:1; 8687 uint64_t zip:1; 8688 uint64_t pko:1; 8689 uint64_t pip:1; 8690 uint64_t ipd:1; 8691 uint64_t l2c:1; 8692 uint64_t pow:1; 8693 uint64_t fpa:1; 8694 uint64_t iob:1; 8695 uint64_t mio:1; 8696 uint64_t nand:1; 8697 uint64_t mii1:1; 8698 uint64_t reserved_4_17:14; 8699 uint64_t wdog:4; 8700 #else 8701 uint64_t wdog:4; 8702 uint64_t reserved_4_17:14; 8703 uint64_t mii1:1; 8704 uint64_t nand:1; 8705 uint64_t mio:1; 8706 uint64_t iob:1; 8707 uint64_t fpa:1; 8708 uint64_t pow:1; 8709 uint64_t l2c:1; 8710 uint64_t ipd:1; 8711 uint64_t pip:1; 8712 uint64_t pko:1; 8713 uint64_t zip:1; 8714 uint64_t tim:1; 8715 uint64_t rad:1; 8716 uint64_t key:1; 8717 uint64_t dfa:1; 8718 uint64_t usb:1; 8719 uint64_t sli:1; 8720 uint64_t dpi:1; 8721 uint64_t agx0:1; 8722 uint64_t agx1:1; 8723 uint64_t reserved_38_39:2; 8724 uint64_t dpi_dma:1; 8725 uint64_t reserved_41_45:5; 8726 uint64_t agl:1; 8727 uint64_t ptp:1; 8728 uint64_t pem0:1; 8729 uint64_t pem1:1; 8730 uint64_t reserved_50_51:2; 8731 uint64_t lmc0:1; 8732 uint64_t reserved_53_62:10; 8733 uint64_t rst:1; 8734 #endif 8735 } cn61xx; 8736 struct cvmx_ciu_sum1_iox_int_cn66xx { 8737 #ifdef __BIG_ENDIAN_BITFIELD 8738 uint64_t rst:1; 8739 uint64_t reserved_62_62:1; 8740 uint64_t srio3:1; 8741 uint64_t srio2:1; 8742 uint64_t reserved_57_59:3; 8743 uint64_t dfm:1; 8744 uint64_t reserved_53_55:3; 8745 uint64_t lmc0:1; 8746 uint64_t reserved_51_51:1; 8747 uint64_t srio0:1; 8748 uint64_t pem1:1; 8749 uint64_t pem0:1; 8750 uint64_t ptp:1; 8751 uint64_t agl:1; 8752 uint64_t reserved_38_45:8; 8753 uint64_t agx1:1; 8754 uint64_t agx0:1; 8755 uint64_t dpi:1; 8756 uint64_t sli:1; 8757 uint64_t usb:1; 8758 uint64_t dfa:1; 8759 uint64_t key:1; 8760 uint64_t rad:1; 8761 uint64_t tim:1; 8762 uint64_t zip:1; 8763 uint64_t pko:1; 8764 uint64_t pip:1; 8765 uint64_t ipd:1; 8766 uint64_t l2c:1; 8767 uint64_t pow:1; 8768 uint64_t fpa:1; 8769 uint64_t iob:1; 8770 uint64_t mio:1; 8771 uint64_t nand:1; 8772 uint64_t mii1:1; 8773 uint64_t reserved_10_17:8; 8774 uint64_t wdog:10; 8775 #else 8776 uint64_t wdog:10; 8777 uint64_t reserved_10_17:8; 8778 uint64_t mii1:1; 8779 uint64_t nand:1; 8780 uint64_t mio:1; 8781 uint64_t iob:1; 8782 uint64_t fpa:1; 8783 uint64_t pow:1; 8784 uint64_t l2c:1; 8785 uint64_t ipd:1; 8786 uint64_t pip:1; 8787 uint64_t pko:1; 8788 uint64_t zip:1; 8789 uint64_t tim:1; 8790 uint64_t rad:1; 8791 uint64_t key:1; 8792 uint64_t dfa:1; 8793 uint64_t usb:1; 8794 uint64_t sli:1; 8795 uint64_t dpi:1; 8796 uint64_t agx0:1; 8797 uint64_t agx1:1; 8798 uint64_t reserved_38_45:8; 8799 uint64_t agl:1; 8800 uint64_t ptp:1; 8801 uint64_t pem0:1; 8802 uint64_t pem1:1; 8803 uint64_t srio0:1; 8804 uint64_t reserved_51_51:1; 8805 uint64_t lmc0:1; 8806 uint64_t reserved_53_55:3; 8807 uint64_t dfm:1; 8808 uint64_t reserved_57_59:3; 8809 uint64_t srio2:1; 8810 uint64_t srio3:1; 8811 uint64_t reserved_62_62:1; 8812 uint64_t rst:1; 8813 #endif 8814 } cn66xx; 8815 struct cvmx_ciu_sum1_iox_int_cnf71xx { 8816 #ifdef __BIG_ENDIAN_BITFIELD 8817 uint64_t rst:1; 8818 uint64_t reserved_53_62:10; 8819 uint64_t lmc0:1; 8820 uint64_t reserved_50_51:2; 8821 uint64_t pem1:1; 8822 uint64_t pem0:1; 8823 uint64_t ptp:1; 8824 uint64_t reserved_41_46:6; 8825 uint64_t dpi_dma:1; 8826 uint64_t reserved_37_39:3; 8827 uint64_t agx0:1; 8828 uint64_t dpi:1; 8829 uint64_t sli:1; 8830 uint64_t usb:1; 8831 uint64_t reserved_32_32:1; 8832 uint64_t key:1; 8833 uint64_t rad:1; 8834 uint64_t tim:1; 8835 uint64_t reserved_28_28:1; 8836 uint64_t pko:1; 8837 uint64_t pip:1; 8838 uint64_t ipd:1; 8839 uint64_t l2c:1; 8840 uint64_t pow:1; 8841 uint64_t fpa:1; 8842 uint64_t iob:1; 8843 uint64_t mio:1; 8844 uint64_t nand:1; 8845 uint64_t reserved_4_18:15; 8846 uint64_t wdog:4; 8847 #else 8848 uint64_t wdog:4; 8849 uint64_t reserved_4_18:15; 8850 uint64_t nand:1; 8851 uint64_t mio:1; 8852 uint64_t iob:1; 8853 uint64_t fpa:1; 8854 uint64_t pow:1; 8855 uint64_t l2c:1; 8856 uint64_t ipd:1; 8857 uint64_t pip:1; 8858 uint64_t pko:1; 8859 uint64_t reserved_28_28:1; 8860 uint64_t tim:1; 8861 uint64_t rad:1; 8862 uint64_t key:1; 8863 uint64_t reserved_32_32:1; 8864 uint64_t usb:1; 8865 uint64_t sli:1; 8866 uint64_t dpi:1; 8867 uint64_t agx0:1; 8868 uint64_t reserved_37_39:3; 8869 uint64_t dpi_dma:1; 8870 uint64_t reserved_41_46:6; 8871 uint64_t ptp:1; 8872 uint64_t pem0:1; 8873 uint64_t pem1:1; 8874 uint64_t reserved_50_51:2; 8875 uint64_t lmc0:1; 8876 uint64_t reserved_53_62:10; 8877 uint64_t rst:1; 8878 #endif 8879 } cnf71xx; 8880 }; 8881 8882 union cvmx_ciu_sum1_ppx_ip2 { 8883 uint64_t u64; 8884 struct cvmx_ciu_sum1_ppx_ip2_s { 8885 #ifdef __BIG_ENDIAN_BITFIELD 8886 uint64_t rst:1; 8887 uint64_t reserved_62_62:1; 8888 uint64_t srio3:1; 8889 uint64_t srio2:1; 8890 uint64_t reserved_57_59:3; 8891 uint64_t dfm:1; 8892 uint64_t reserved_53_55:3; 8893 uint64_t lmc0:1; 8894 uint64_t reserved_51_51:1; 8895 uint64_t srio0:1; 8896 uint64_t pem1:1; 8897 uint64_t pem0:1; 8898 uint64_t ptp:1; 8899 uint64_t agl:1; 8900 uint64_t reserved_41_45:5; 8901 uint64_t dpi_dma:1; 8902 uint64_t reserved_38_39:2; 8903 uint64_t agx1:1; 8904 uint64_t agx0:1; 8905 uint64_t dpi:1; 8906 uint64_t sli:1; 8907 uint64_t usb:1; 8908 uint64_t dfa:1; 8909 uint64_t key:1; 8910 uint64_t rad:1; 8911 uint64_t tim:1; 8912 uint64_t zip:1; 8913 uint64_t pko:1; 8914 uint64_t pip:1; 8915 uint64_t ipd:1; 8916 uint64_t l2c:1; 8917 uint64_t pow:1; 8918 uint64_t fpa:1; 8919 uint64_t iob:1; 8920 uint64_t mio:1; 8921 uint64_t nand:1; 8922 uint64_t mii1:1; 8923 uint64_t reserved_10_17:8; 8924 uint64_t wdog:10; 8925 #else 8926 uint64_t wdog:10; 8927 uint64_t reserved_10_17:8; 8928 uint64_t mii1:1; 8929 uint64_t nand:1; 8930 uint64_t mio:1; 8931 uint64_t iob:1; 8932 uint64_t fpa:1; 8933 uint64_t pow:1; 8934 uint64_t l2c:1; 8935 uint64_t ipd:1; 8936 uint64_t pip:1; 8937 uint64_t pko:1; 8938 uint64_t zip:1; 8939 uint64_t tim:1; 8940 uint64_t rad:1; 8941 uint64_t key:1; 8942 uint64_t dfa:1; 8943 uint64_t usb:1; 8944 uint64_t sli:1; 8945 uint64_t dpi:1; 8946 uint64_t agx0:1; 8947 uint64_t agx1:1; 8948 uint64_t reserved_38_39:2; 8949 uint64_t dpi_dma:1; 8950 uint64_t reserved_41_45:5; 8951 uint64_t agl:1; 8952 uint64_t ptp:1; 8953 uint64_t pem0:1; 8954 uint64_t pem1:1; 8955 uint64_t srio0:1; 8956 uint64_t reserved_51_51:1; 8957 uint64_t lmc0:1; 8958 uint64_t reserved_53_55:3; 8959 uint64_t dfm:1; 8960 uint64_t reserved_57_59:3; 8961 uint64_t srio2:1; 8962 uint64_t srio3:1; 8963 uint64_t reserved_62_62:1; 8964 uint64_t rst:1; 8965 #endif 8966 } s; 8967 struct cvmx_ciu_sum1_ppx_ip2_cn61xx { 8968 #ifdef __BIG_ENDIAN_BITFIELD 8969 uint64_t rst:1; 8970 uint64_t reserved_53_62:10; 8971 uint64_t lmc0:1; 8972 uint64_t reserved_50_51:2; 8973 uint64_t pem1:1; 8974 uint64_t pem0:1; 8975 uint64_t ptp:1; 8976 uint64_t agl:1; 8977 uint64_t reserved_41_45:5; 8978 uint64_t dpi_dma:1; 8979 uint64_t reserved_38_39:2; 8980 uint64_t agx1:1; 8981 uint64_t agx0:1; 8982 uint64_t dpi:1; 8983 uint64_t sli:1; 8984 uint64_t usb:1; 8985 uint64_t dfa:1; 8986 uint64_t key:1; 8987 uint64_t rad:1; 8988 uint64_t tim:1; 8989 uint64_t zip:1; 8990 uint64_t pko:1; 8991 uint64_t pip:1; 8992 uint64_t ipd:1; 8993 uint64_t l2c:1; 8994 uint64_t pow:1; 8995 uint64_t fpa:1; 8996 uint64_t iob:1; 8997 uint64_t mio:1; 8998 uint64_t nand:1; 8999 uint64_t mii1:1; 9000 uint64_t reserved_4_17:14; 9001 uint64_t wdog:4; 9002 #else 9003 uint64_t wdog:4; 9004 uint64_t reserved_4_17:14; 9005 uint64_t mii1:1; 9006 uint64_t nand:1; 9007 uint64_t mio:1; 9008 uint64_t iob:1; 9009 uint64_t fpa:1; 9010 uint64_t pow:1; 9011 uint64_t l2c:1; 9012 uint64_t ipd:1; 9013 uint64_t pip:1; 9014 uint64_t pko:1; 9015 uint64_t zip:1; 9016 uint64_t tim:1; 9017 uint64_t rad:1; 9018 uint64_t key:1; 9019 uint64_t dfa:1; 9020 uint64_t usb:1; 9021 uint64_t sli:1; 9022 uint64_t dpi:1; 9023 uint64_t agx0:1; 9024 uint64_t agx1:1; 9025 uint64_t reserved_38_39:2; 9026 uint64_t dpi_dma:1; 9027 uint64_t reserved_41_45:5; 9028 uint64_t agl:1; 9029 uint64_t ptp:1; 9030 uint64_t pem0:1; 9031 uint64_t pem1:1; 9032 uint64_t reserved_50_51:2; 9033 uint64_t lmc0:1; 9034 uint64_t reserved_53_62:10; 9035 uint64_t rst:1; 9036 #endif 9037 } cn61xx; 9038 struct cvmx_ciu_sum1_ppx_ip2_cn66xx { 9039 #ifdef __BIG_ENDIAN_BITFIELD 9040 uint64_t rst:1; 9041 uint64_t reserved_62_62:1; 9042 uint64_t srio3:1; 9043 uint64_t srio2:1; 9044 uint64_t reserved_57_59:3; 9045 uint64_t dfm:1; 9046 uint64_t reserved_53_55:3; 9047 uint64_t lmc0:1; 9048 uint64_t reserved_51_51:1; 9049 uint64_t srio0:1; 9050 uint64_t pem1:1; 9051 uint64_t pem0:1; 9052 uint64_t ptp:1; 9053 uint64_t agl:1; 9054 uint64_t reserved_38_45:8; 9055 uint64_t agx1:1; 9056 uint64_t agx0:1; 9057 uint64_t dpi:1; 9058 uint64_t sli:1; 9059 uint64_t usb:1; 9060 uint64_t dfa:1; 9061 uint64_t key:1; 9062 uint64_t rad:1; 9063 uint64_t tim:1; 9064 uint64_t zip:1; 9065 uint64_t pko:1; 9066 uint64_t pip:1; 9067 uint64_t ipd:1; 9068 uint64_t l2c:1; 9069 uint64_t pow:1; 9070 uint64_t fpa:1; 9071 uint64_t iob:1; 9072 uint64_t mio:1; 9073 uint64_t nand:1; 9074 uint64_t mii1:1; 9075 uint64_t reserved_10_17:8; 9076 uint64_t wdog:10; 9077 #else 9078 uint64_t wdog:10; 9079 uint64_t reserved_10_17:8; 9080 uint64_t mii1:1; 9081 uint64_t nand:1; 9082 uint64_t mio:1; 9083 uint64_t iob:1; 9084 uint64_t fpa:1; 9085 uint64_t pow:1; 9086 uint64_t l2c:1; 9087 uint64_t ipd:1; 9088 uint64_t pip:1; 9089 uint64_t pko:1; 9090 uint64_t zip:1; 9091 uint64_t tim:1; 9092 uint64_t rad:1; 9093 uint64_t key:1; 9094 uint64_t dfa:1; 9095 uint64_t usb:1; 9096 uint64_t sli:1; 9097 uint64_t dpi:1; 9098 uint64_t agx0:1; 9099 uint64_t agx1:1; 9100 uint64_t reserved_38_45:8; 9101 uint64_t agl:1; 9102 uint64_t ptp:1; 9103 uint64_t pem0:1; 9104 uint64_t pem1:1; 9105 uint64_t srio0:1; 9106 uint64_t reserved_51_51:1; 9107 uint64_t lmc0:1; 9108 uint64_t reserved_53_55:3; 9109 uint64_t dfm:1; 9110 uint64_t reserved_57_59:3; 9111 uint64_t srio2:1; 9112 uint64_t srio3:1; 9113 uint64_t reserved_62_62:1; 9114 uint64_t rst:1; 9115 #endif 9116 } cn66xx; 9117 struct cvmx_ciu_sum1_ppx_ip2_cnf71xx { 9118 #ifdef __BIG_ENDIAN_BITFIELD 9119 uint64_t rst:1; 9120 uint64_t reserved_53_62:10; 9121 uint64_t lmc0:1; 9122 uint64_t reserved_50_51:2; 9123 uint64_t pem1:1; 9124 uint64_t pem0:1; 9125 uint64_t ptp:1; 9126 uint64_t reserved_41_46:6; 9127 uint64_t dpi_dma:1; 9128 uint64_t reserved_37_39:3; 9129 uint64_t agx0:1; 9130 uint64_t dpi:1; 9131 uint64_t sli:1; 9132 uint64_t usb:1; 9133 uint64_t reserved_32_32:1; 9134 uint64_t key:1; 9135 uint64_t rad:1; 9136 uint64_t tim:1; 9137 uint64_t reserved_28_28:1; 9138 uint64_t pko:1; 9139 uint64_t pip:1; 9140 uint64_t ipd:1; 9141 uint64_t l2c:1; 9142 uint64_t pow:1; 9143 uint64_t fpa:1; 9144 uint64_t iob:1; 9145 uint64_t mio:1; 9146 uint64_t nand:1; 9147 uint64_t reserved_4_18:15; 9148 uint64_t wdog:4; 9149 #else 9150 uint64_t wdog:4; 9151 uint64_t reserved_4_18:15; 9152 uint64_t nand:1; 9153 uint64_t mio:1; 9154 uint64_t iob:1; 9155 uint64_t fpa:1; 9156 uint64_t pow:1; 9157 uint64_t l2c:1; 9158 uint64_t ipd:1; 9159 uint64_t pip:1; 9160 uint64_t pko:1; 9161 uint64_t reserved_28_28:1; 9162 uint64_t tim:1; 9163 uint64_t rad:1; 9164 uint64_t key:1; 9165 uint64_t reserved_32_32:1; 9166 uint64_t usb:1; 9167 uint64_t sli:1; 9168 uint64_t dpi:1; 9169 uint64_t agx0:1; 9170 uint64_t reserved_37_39:3; 9171 uint64_t dpi_dma:1; 9172 uint64_t reserved_41_46:6; 9173 uint64_t ptp:1; 9174 uint64_t pem0:1; 9175 uint64_t pem1:1; 9176 uint64_t reserved_50_51:2; 9177 uint64_t lmc0:1; 9178 uint64_t reserved_53_62:10; 9179 uint64_t rst:1; 9180 #endif 9181 } cnf71xx; 9182 }; 9183 9184 union cvmx_ciu_sum1_ppx_ip3 { 9185 uint64_t u64; 9186 struct cvmx_ciu_sum1_ppx_ip3_s { 9187 #ifdef __BIG_ENDIAN_BITFIELD 9188 uint64_t rst:1; 9189 uint64_t reserved_62_62:1; 9190 uint64_t srio3:1; 9191 uint64_t srio2:1; 9192 uint64_t reserved_57_59:3; 9193 uint64_t dfm:1; 9194 uint64_t reserved_53_55:3; 9195 uint64_t lmc0:1; 9196 uint64_t reserved_51_51:1; 9197 uint64_t srio0:1; 9198 uint64_t pem1:1; 9199 uint64_t pem0:1; 9200 uint64_t ptp:1; 9201 uint64_t agl:1; 9202 uint64_t reserved_41_45:5; 9203 uint64_t dpi_dma:1; 9204 uint64_t reserved_38_39:2; 9205 uint64_t agx1:1; 9206 uint64_t agx0:1; 9207 uint64_t dpi:1; 9208 uint64_t sli:1; 9209 uint64_t usb:1; 9210 uint64_t dfa:1; 9211 uint64_t key:1; 9212 uint64_t rad:1; 9213 uint64_t tim:1; 9214 uint64_t zip:1; 9215 uint64_t pko:1; 9216 uint64_t pip:1; 9217 uint64_t ipd:1; 9218 uint64_t l2c:1; 9219 uint64_t pow:1; 9220 uint64_t fpa:1; 9221 uint64_t iob:1; 9222 uint64_t mio:1; 9223 uint64_t nand:1; 9224 uint64_t mii1:1; 9225 uint64_t reserved_10_17:8; 9226 uint64_t wdog:10; 9227 #else 9228 uint64_t wdog:10; 9229 uint64_t reserved_10_17:8; 9230 uint64_t mii1:1; 9231 uint64_t nand:1; 9232 uint64_t mio:1; 9233 uint64_t iob:1; 9234 uint64_t fpa:1; 9235 uint64_t pow:1; 9236 uint64_t l2c:1; 9237 uint64_t ipd:1; 9238 uint64_t pip:1; 9239 uint64_t pko:1; 9240 uint64_t zip:1; 9241 uint64_t tim:1; 9242 uint64_t rad:1; 9243 uint64_t key:1; 9244 uint64_t dfa:1; 9245 uint64_t usb:1; 9246 uint64_t sli:1; 9247 uint64_t dpi:1; 9248 uint64_t agx0:1; 9249 uint64_t agx1:1; 9250 uint64_t reserved_38_39:2; 9251 uint64_t dpi_dma:1; 9252 uint64_t reserved_41_45:5; 9253 uint64_t agl:1; 9254 uint64_t ptp:1; 9255 uint64_t pem0:1; 9256 uint64_t pem1:1; 9257 uint64_t srio0:1; 9258 uint64_t reserved_51_51:1; 9259 uint64_t lmc0:1; 9260 uint64_t reserved_53_55:3; 9261 uint64_t dfm:1; 9262 uint64_t reserved_57_59:3; 9263 uint64_t srio2:1; 9264 uint64_t srio3:1; 9265 uint64_t reserved_62_62:1; 9266 uint64_t rst:1; 9267 #endif 9268 } s; 9269 struct cvmx_ciu_sum1_ppx_ip3_cn61xx { 9270 #ifdef __BIG_ENDIAN_BITFIELD 9271 uint64_t rst:1; 9272 uint64_t reserved_53_62:10; 9273 uint64_t lmc0:1; 9274 uint64_t reserved_50_51:2; 9275 uint64_t pem1:1; 9276 uint64_t pem0:1; 9277 uint64_t ptp:1; 9278 uint64_t agl:1; 9279 uint64_t reserved_41_45:5; 9280 uint64_t dpi_dma:1; 9281 uint64_t reserved_38_39:2; 9282 uint64_t agx1:1; 9283 uint64_t agx0:1; 9284 uint64_t dpi:1; 9285 uint64_t sli:1; 9286 uint64_t usb:1; 9287 uint64_t dfa:1; 9288 uint64_t key:1; 9289 uint64_t rad:1; 9290 uint64_t tim:1; 9291 uint64_t zip:1; 9292 uint64_t pko:1; 9293 uint64_t pip:1; 9294 uint64_t ipd:1; 9295 uint64_t l2c:1; 9296 uint64_t pow:1; 9297 uint64_t fpa:1; 9298 uint64_t iob:1; 9299 uint64_t mio:1; 9300 uint64_t nand:1; 9301 uint64_t mii1:1; 9302 uint64_t reserved_4_17:14; 9303 uint64_t wdog:4; 9304 #else 9305 uint64_t wdog:4; 9306 uint64_t reserved_4_17:14; 9307 uint64_t mii1:1; 9308 uint64_t nand:1; 9309 uint64_t mio:1; 9310 uint64_t iob:1; 9311 uint64_t fpa:1; 9312 uint64_t pow:1; 9313 uint64_t l2c:1; 9314 uint64_t ipd:1; 9315 uint64_t pip:1; 9316 uint64_t pko:1; 9317 uint64_t zip:1; 9318 uint64_t tim:1; 9319 uint64_t rad:1; 9320 uint64_t key:1; 9321 uint64_t dfa:1; 9322 uint64_t usb:1; 9323 uint64_t sli:1; 9324 uint64_t dpi:1; 9325 uint64_t agx0:1; 9326 uint64_t agx1:1; 9327 uint64_t reserved_38_39:2; 9328 uint64_t dpi_dma:1; 9329 uint64_t reserved_41_45:5; 9330 uint64_t agl:1; 9331 uint64_t ptp:1; 9332 uint64_t pem0:1; 9333 uint64_t pem1:1; 9334 uint64_t reserved_50_51:2; 9335 uint64_t lmc0:1; 9336 uint64_t reserved_53_62:10; 9337 uint64_t rst:1; 9338 #endif 9339 } cn61xx; 9340 struct cvmx_ciu_sum1_ppx_ip3_cn66xx { 9341 #ifdef __BIG_ENDIAN_BITFIELD 9342 uint64_t rst:1; 9343 uint64_t reserved_62_62:1; 9344 uint64_t srio3:1; 9345 uint64_t srio2:1; 9346 uint64_t reserved_57_59:3; 9347 uint64_t dfm:1; 9348 uint64_t reserved_53_55:3; 9349 uint64_t lmc0:1; 9350 uint64_t reserved_51_51:1; 9351 uint64_t srio0:1; 9352 uint64_t pem1:1; 9353 uint64_t pem0:1; 9354 uint64_t ptp:1; 9355 uint64_t agl:1; 9356 uint64_t reserved_38_45:8; 9357 uint64_t agx1:1; 9358 uint64_t agx0:1; 9359 uint64_t dpi:1; 9360 uint64_t sli:1; 9361 uint64_t usb:1; 9362 uint64_t dfa:1; 9363 uint64_t key:1; 9364 uint64_t rad:1; 9365 uint64_t tim:1; 9366 uint64_t zip:1; 9367 uint64_t pko:1; 9368 uint64_t pip:1; 9369 uint64_t ipd:1; 9370 uint64_t l2c:1; 9371 uint64_t pow:1; 9372 uint64_t fpa:1; 9373 uint64_t iob:1; 9374 uint64_t mio:1; 9375 uint64_t nand:1; 9376 uint64_t mii1:1; 9377 uint64_t reserved_10_17:8; 9378 uint64_t wdog:10; 9379 #else 9380 uint64_t wdog:10; 9381 uint64_t reserved_10_17:8; 9382 uint64_t mii1:1; 9383 uint64_t nand:1; 9384 uint64_t mio:1; 9385 uint64_t iob:1; 9386 uint64_t fpa:1; 9387 uint64_t pow:1; 9388 uint64_t l2c:1; 9389 uint64_t ipd:1; 9390 uint64_t pip:1; 9391 uint64_t pko:1; 9392 uint64_t zip:1; 9393 uint64_t tim:1; 9394 uint64_t rad:1; 9395 uint64_t key:1; 9396 uint64_t dfa:1; 9397 uint64_t usb:1; 9398 uint64_t sli:1; 9399 uint64_t dpi:1; 9400 uint64_t agx0:1; 9401 uint64_t agx1:1; 9402 uint64_t reserved_38_45:8; 9403 uint64_t agl:1; 9404 uint64_t ptp:1; 9405 uint64_t pem0:1; 9406 uint64_t pem1:1; 9407 uint64_t srio0:1; 9408 uint64_t reserved_51_51:1; 9409 uint64_t lmc0:1; 9410 uint64_t reserved_53_55:3; 9411 uint64_t dfm:1; 9412 uint64_t reserved_57_59:3; 9413 uint64_t srio2:1; 9414 uint64_t srio3:1; 9415 uint64_t reserved_62_62:1; 9416 uint64_t rst:1; 9417 #endif 9418 } cn66xx; 9419 struct cvmx_ciu_sum1_ppx_ip3_cnf71xx { 9420 #ifdef __BIG_ENDIAN_BITFIELD 9421 uint64_t rst:1; 9422 uint64_t reserved_53_62:10; 9423 uint64_t lmc0:1; 9424 uint64_t reserved_50_51:2; 9425 uint64_t pem1:1; 9426 uint64_t pem0:1; 9427 uint64_t ptp:1; 9428 uint64_t reserved_41_46:6; 9429 uint64_t dpi_dma:1; 9430 uint64_t reserved_37_39:3; 9431 uint64_t agx0:1; 9432 uint64_t dpi:1; 9433 uint64_t sli:1; 9434 uint64_t usb:1; 9435 uint64_t reserved_32_32:1; 9436 uint64_t key:1; 9437 uint64_t rad:1; 9438 uint64_t tim:1; 9439 uint64_t reserved_28_28:1; 9440 uint64_t pko:1; 9441 uint64_t pip:1; 9442 uint64_t ipd:1; 9443 uint64_t l2c:1; 9444 uint64_t pow:1; 9445 uint64_t fpa:1; 9446 uint64_t iob:1; 9447 uint64_t mio:1; 9448 uint64_t nand:1; 9449 uint64_t reserved_4_18:15; 9450 uint64_t wdog:4; 9451 #else 9452 uint64_t wdog:4; 9453 uint64_t reserved_4_18:15; 9454 uint64_t nand:1; 9455 uint64_t mio:1; 9456 uint64_t iob:1; 9457 uint64_t fpa:1; 9458 uint64_t pow:1; 9459 uint64_t l2c:1; 9460 uint64_t ipd:1; 9461 uint64_t pip:1; 9462 uint64_t pko:1; 9463 uint64_t reserved_28_28:1; 9464 uint64_t tim:1; 9465 uint64_t rad:1; 9466 uint64_t key:1; 9467 uint64_t reserved_32_32:1; 9468 uint64_t usb:1; 9469 uint64_t sli:1; 9470 uint64_t dpi:1; 9471 uint64_t agx0:1; 9472 uint64_t reserved_37_39:3; 9473 uint64_t dpi_dma:1; 9474 uint64_t reserved_41_46:6; 9475 uint64_t ptp:1; 9476 uint64_t pem0:1; 9477 uint64_t pem1:1; 9478 uint64_t reserved_50_51:2; 9479 uint64_t lmc0:1; 9480 uint64_t reserved_53_62:10; 9481 uint64_t rst:1; 9482 #endif 9483 } cnf71xx; 9484 }; 9485 9486 union cvmx_ciu_sum1_ppx_ip4 { 9487 uint64_t u64; 9488 struct cvmx_ciu_sum1_ppx_ip4_s { 9489 #ifdef __BIG_ENDIAN_BITFIELD 9490 uint64_t rst:1; 9491 uint64_t reserved_62_62:1; 9492 uint64_t srio3:1; 9493 uint64_t srio2:1; 9494 uint64_t reserved_57_59:3; 9495 uint64_t dfm:1; 9496 uint64_t reserved_53_55:3; 9497 uint64_t lmc0:1; 9498 uint64_t reserved_51_51:1; 9499 uint64_t srio0:1; 9500 uint64_t pem1:1; 9501 uint64_t pem0:1; 9502 uint64_t ptp:1; 9503 uint64_t agl:1; 9504 uint64_t reserved_41_45:5; 9505 uint64_t dpi_dma:1; 9506 uint64_t reserved_38_39:2; 9507 uint64_t agx1:1; 9508 uint64_t agx0:1; 9509 uint64_t dpi:1; 9510 uint64_t sli:1; 9511 uint64_t usb:1; 9512 uint64_t dfa:1; 9513 uint64_t key:1; 9514 uint64_t rad:1; 9515 uint64_t tim:1; 9516 uint64_t zip:1; 9517 uint64_t pko:1; 9518 uint64_t pip:1; 9519 uint64_t ipd:1; 9520 uint64_t l2c:1; 9521 uint64_t pow:1; 9522 uint64_t fpa:1; 9523 uint64_t iob:1; 9524 uint64_t mio:1; 9525 uint64_t nand:1; 9526 uint64_t mii1:1; 9527 uint64_t reserved_10_17:8; 9528 uint64_t wdog:10; 9529 #else 9530 uint64_t wdog:10; 9531 uint64_t reserved_10_17:8; 9532 uint64_t mii1:1; 9533 uint64_t nand:1; 9534 uint64_t mio:1; 9535 uint64_t iob:1; 9536 uint64_t fpa:1; 9537 uint64_t pow:1; 9538 uint64_t l2c:1; 9539 uint64_t ipd:1; 9540 uint64_t pip:1; 9541 uint64_t pko:1; 9542 uint64_t zip:1; 9543 uint64_t tim:1; 9544 uint64_t rad:1; 9545 uint64_t key:1; 9546 uint64_t dfa:1; 9547 uint64_t usb:1; 9548 uint64_t sli:1; 9549 uint64_t dpi:1; 9550 uint64_t agx0:1; 9551 uint64_t agx1:1; 9552 uint64_t reserved_38_39:2; 9553 uint64_t dpi_dma:1; 9554 uint64_t reserved_41_45:5; 9555 uint64_t agl:1; 9556 uint64_t ptp:1; 9557 uint64_t pem0:1; 9558 uint64_t pem1:1; 9559 uint64_t srio0:1; 9560 uint64_t reserved_51_51:1; 9561 uint64_t lmc0:1; 9562 uint64_t reserved_53_55:3; 9563 uint64_t dfm:1; 9564 uint64_t reserved_57_59:3; 9565 uint64_t srio2:1; 9566 uint64_t srio3:1; 9567 uint64_t reserved_62_62:1; 9568 uint64_t rst:1; 9569 #endif 9570 } s; 9571 struct cvmx_ciu_sum1_ppx_ip4_cn61xx { 9572 #ifdef __BIG_ENDIAN_BITFIELD 9573 uint64_t rst:1; 9574 uint64_t reserved_53_62:10; 9575 uint64_t lmc0:1; 9576 uint64_t reserved_50_51:2; 9577 uint64_t pem1:1; 9578 uint64_t pem0:1; 9579 uint64_t ptp:1; 9580 uint64_t agl:1; 9581 uint64_t reserved_41_45:5; 9582 uint64_t dpi_dma:1; 9583 uint64_t reserved_38_39:2; 9584 uint64_t agx1:1; 9585 uint64_t agx0:1; 9586 uint64_t dpi:1; 9587 uint64_t sli:1; 9588 uint64_t usb:1; 9589 uint64_t dfa:1; 9590 uint64_t key:1; 9591 uint64_t rad:1; 9592 uint64_t tim:1; 9593 uint64_t zip:1; 9594 uint64_t pko:1; 9595 uint64_t pip:1; 9596 uint64_t ipd:1; 9597 uint64_t l2c:1; 9598 uint64_t pow:1; 9599 uint64_t fpa:1; 9600 uint64_t iob:1; 9601 uint64_t mio:1; 9602 uint64_t nand:1; 9603 uint64_t mii1:1; 9604 uint64_t reserved_4_17:14; 9605 uint64_t wdog:4; 9606 #else 9607 uint64_t wdog:4; 9608 uint64_t reserved_4_17:14; 9609 uint64_t mii1:1; 9610 uint64_t nand:1; 9611 uint64_t mio:1; 9612 uint64_t iob:1; 9613 uint64_t fpa:1; 9614 uint64_t pow:1; 9615 uint64_t l2c:1; 9616 uint64_t ipd:1; 9617 uint64_t pip:1; 9618 uint64_t pko:1; 9619 uint64_t zip:1; 9620 uint64_t tim:1; 9621 uint64_t rad:1; 9622 uint64_t key:1; 9623 uint64_t dfa:1; 9624 uint64_t usb:1; 9625 uint64_t sli:1; 9626 uint64_t dpi:1; 9627 uint64_t agx0:1; 9628 uint64_t agx1:1; 9629 uint64_t reserved_38_39:2; 9630 uint64_t dpi_dma:1; 9631 uint64_t reserved_41_45:5; 9632 uint64_t agl:1; 9633 uint64_t ptp:1; 9634 uint64_t pem0:1; 9635 uint64_t pem1:1; 9636 uint64_t reserved_50_51:2; 9637 uint64_t lmc0:1; 9638 uint64_t reserved_53_62:10; 9639 uint64_t rst:1; 9640 #endif 9641 } cn61xx; 9642 struct cvmx_ciu_sum1_ppx_ip4_cn66xx { 9643 #ifdef __BIG_ENDIAN_BITFIELD 9644 uint64_t rst:1; 9645 uint64_t reserved_62_62:1; 9646 uint64_t srio3:1; 9647 uint64_t srio2:1; 9648 uint64_t reserved_57_59:3; 9649 uint64_t dfm:1; 9650 uint64_t reserved_53_55:3; 9651 uint64_t lmc0:1; 9652 uint64_t reserved_51_51:1; 9653 uint64_t srio0:1; 9654 uint64_t pem1:1; 9655 uint64_t pem0:1; 9656 uint64_t ptp:1; 9657 uint64_t agl:1; 9658 uint64_t reserved_38_45:8; 9659 uint64_t agx1:1; 9660 uint64_t agx0:1; 9661 uint64_t dpi:1; 9662 uint64_t sli:1; 9663 uint64_t usb:1; 9664 uint64_t dfa:1; 9665 uint64_t key:1; 9666 uint64_t rad:1; 9667 uint64_t tim:1; 9668 uint64_t zip:1; 9669 uint64_t pko:1; 9670 uint64_t pip:1; 9671 uint64_t ipd:1; 9672 uint64_t l2c:1; 9673 uint64_t pow:1; 9674 uint64_t fpa:1; 9675 uint64_t iob:1; 9676 uint64_t mio:1; 9677 uint64_t nand:1; 9678 uint64_t mii1:1; 9679 uint64_t reserved_10_17:8; 9680 uint64_t wdog:10; 9681 #else 9682 uint64_t wdog:10; 9683 uint64_t reserved_10_17:8; 9684 uint64_t mii1:1; 9685 uint64_t nand:1; 9686 uint64_t mio:1; 9687 uint64_t iob:1; 9688 uint64_t fpa:1; 9689 uint64_t pow:1; 9690 uint64_t l2c:1; 9691 uint64_t ipd:1; 9692 uint64_t pip:1; 9693 uint64_t pko:1; 9694 uint64_t zip:1; 9695 uint64_t tim:1; 9696 uint64_t rad:1; 9697 uint64_t key:1; 9698 uint64_t dfa:1; 9699 uint64_t usb:1; 9700 uint64_t sli:1; 9701 uint64_t dpi:1; 9702 uint64_t agx0:1; 9703 uint64_t agx1:1; 9704 uint64_t reserved_38_45:8; 9705 uint64_t agl:1; 9706 uint64_t ptp:1; 9707 uint64_t pem0:1; 9708 uint64_t pem1:1; 9709 uint64_t srio0:1; 9710 uint64_t reserved_51_51:1; 9711 uint64_t lmc0:1; 9712 uint64_t reserved_53_55:3; 9713 uint64_t dfm:1; 9714 uint64_t reserved_57_59:3; 9715 uint64_t srio2:1; 9716 uint64_t srio3:1; 9717 uint64_t reserved_62_62:1; 9718 uint64_t rst:1; 9719 #endif 9720 } cn66xx; 9721 struct cvmx_ciu_sum1_ppx_ip4_cnf71xx { 9722 #ifdef __BIG_ENDIAN_BITFIELD 9723 uint64_t rst:1; 9724 uint64_t reserved_53_62:10; 9725 uint64_t lmc0:1; 9726 uint64_t reserved_50_51:2; 9727 uint64_t pem1:1; 9728 uint64_t pem0:1; 9729 uint64_t ptp:1; 9730 uint64_t reserved_41_46:6; 9731 uint64_t dpi_dma:1; 9732 uint64_t reserved_37_39:3; 9733 uint64_t agx0:1; 9734 uint64_t dpi:1; 9735 uint64_t sli:1; 9736 uint64_t usb:1; 9737 uint64_t reserved_32_32:1; 9738 uint64_t key:1; 9739 uint64_t rad:1; 9740 uint64_t tim:1; 9741 uint64_t reserved_28_28:1; 9742 uint64_t pko:1; 9743 uint64_t pip:1; 9744 uint64_t ipd:1; 9745 uint64_t l2c:1; 9746 uint64_t pow:1; 9747 uint64_t fpa:1; 9748 uint64_t iob:1; 9749 uint64_t mio:1; 9750 uint64_t nand:1; 9751 uint64_t reserved_4_18:15; 9752 uint64_t wdog:4; 9753 #else 9754 uint64_t wdog:4; 9755 uint64_t reserved_4_18:15; 9756 uint64_t nand:1; 9757 uint64_t mio:1; 9758 uint64_t iob:1; 9759 uint64_t fpa:1; 9760 uint64_t pow:1; 9761 uint64_t l2c:1; 9762 uint64_t ipd:1; 9763 uint64_t pip:1; 9764 uint64_t pko:1; 9765 uint64_t reserved_28_28:1; 9766 uint64_t tim:1; 9767 uint64_t rad:1; 9768 uint64_t key:1; 9769 uint64_t reserved_32_32:1; 9770 uint64_t usb:1; 9771 uint64_t sli:1; 9772 uint64_t dpi:1; 9773 uint64_t agx0:1; 9774 uint64_t reserved_37_39:3; 9775 uint64_t dpi_dma:1; 9776 uint64_t reserved_41_46:6; 9777 uint64_t ptp:1; 9778 uint64_t pem0:1; 9779 uint64_t pem1:1; 9780 uint64_t reserved_50_51:2; 9781 uint64_t lmc0:1; 9782 uint64_t reserved_53_62:10; 9783 uint64_t rst:1; 9784 #endif 9785 } cnf71xx; 9786 }; 9787 9788 union cvmx_ciu_sum2_iox_int { 9789 uint64_t u64; 9790 struct cvmx_ciu_sum2_iox_int_s { 9791 #ifdef __BIG_ENDIAN_BITFIELD 9792 uint64_t reserved_15_63:49; 9793 uint64_t endor:2; 9794 uint64_t eoi:1; 9795 uint64_t reserved_10_11:2; 9796 uint64_t timer:6; 9797 uint64_t reserved_0_3:4; 9798 #else 9799 uint64_t reserved_0_3:4; 9800 uint64_t timer:6; 9801 uint64_t reserved_10_11:2; 9802 uint64_t eoi:1; 9803 uint64_t endor:2; 9804 uint64_t reserved_15_63:49; 9805 #endif 9806 } s; 9807 struct cvmx_ciu_sum2_iox_int_cn61xx { 9808 #ifdef __BIG_ENDIAN_BITFIELD 9809 uint64_t reserved_10_63:54; 9810 uint64_t timer:6; 9811 uint64_t reserved_0_3:4; 9812 #else 9813 uint64_t reserved_0_3:4; 9814 uint64_t timer:6; 9815 uint64_t reserved_10_63:54; 9816 #endif 9817 } cn61xx; 9818 struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx; 9819 struct cvmx_ciu_sum2_iox_int_s cnf71xx; 9820 }; 9821 9822 union cvmx_ciu_sum2_ppx_ip2 { 9823 uint64_t u64; 9824 struct cvmx_ciu_sum2_ppx_ip2_s { 9825 #ifdef __BIG_ENDIAN_BITFIELD 9826 uint64_t reserved_15_63:49; 9827 uint64_t endor:2; 9828 uint64_t eoi:1; 9829 uint64_t reserved_10_11:2; 9830 uint64_t timer:6; 9831 uint64_t reserved_0_3:4; 9832 #else 9833 uint64_t reserved_0_3:4; 9834 uint64_t timer:6; 9835 uint64_t reserved_10_11:2; 9836 uint64_t eoi:1; 9837 uint64_t endor:2; 9838 uint64_t reserved_15_63:49; 9839 #endif 9840 } s; 9841 struct cvmx_ciu_sum2_ppx_ip2_cn61xx { 9842 #ifdef __BIG_ENDIAN_BITFIELD 9843 uint64_t reserved_10_63:54; 9844 uint64_t timer:6; 9845 uint64_t reserved_0_3:4; 9846 #else 9847 uint64_t reserved_0_3:4; 9848 uint64_t timer:6; 9849 uint64_t reserved_10_63:54; 9850 #endif 9851 } cn61xx; 9852 struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx; 9853 struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx; 9854 }; 9855 9856 union cvmx_ciu_sum2_ppx_ip3 { 9857 uint64_t u64; 9858 struct cvmx_ciu_sum2_ppx_ip3_s { 9859 #ifdef __BIG_ENDIAN_BITFIELD 9860 uint64_t reserved_15_63:49; 9861 uint64_t endor:2; 9862 uint64_t eoi:1; 9863 uint64_t reserved_10_11:2; 9864 uint64_t timer:6; 9865 uint64_t reserved_0_3:4; 9866 #else 9867 uint64_t reserved_0_3:4; 9868 uint64_t timer:6; 9869 uint64_t reserved_10_11:2; 9870 uint64_t eoi:1; 9871 uint64_t endor:2; 9872 uint64_t reserved_15_63:49; 9873 #endif 9874 } s; 9875 struct cvmx_ciu_sum2_ppx_ip3_cn61xx { 9876 #ifdef __BIG_ENDIAN_BITFIELD 9877 uint64_t reserved_10_63:54; 9878 uint64_t timer:6; 9879 uint64_t reserved_0_3:4; 9880 #else 9881 uint64_t reserved_0_3:4; 9882 uint64_t timer:6; 9883 uint64_t reserved_10_63:54; 9884 #endif 9885 } cn61xx; 9886 struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx; 9887 struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx; 9888 }; 9889 9890 union cvmx_ciu_sum2_ppx_ip4 { 9891 uint64_t u64; 9892 struct cvmx_ciu_sum2_ppx_ip4_s { 9893 #ifdef __BIG_ENDIAN_BITFIELD 9894 uint64_t reserved_15_63:49; 9895 uint64_t endor:2; 9896 uint64_t eoi:1; 9897 uint64_t reserved_10_11:2; 9898 uint64_t timer:6; 9899 uint64_t reserved_0_3:4; 9900 #else 9901 uint64_t reserved_0_3:4; 9902 uint64_t timer:6; 9903 uint64_t reserved_10_11:2; 9904 uint64_t eoi:1; 9905 uint64_t endor:2; 9906 uint64_t reserved_15_63:49; 9907 #endif 9908 } s; 9909 struct cvmx_ciu_sum2_ppx_ip4_cn61xx { 9910 #ifdef __BIG_ENDIAN_BITFIELD 9911 uint64_t reserved_10_63:54; 9912 uint64_t timer:6; 9913 uint64_t reserved_0_3:4; 9914 #else 9915 uint64_t reserved_0_3:4; 9916 uint64_t timer:6; 9917 uint64_t reserved_10_63:54; 9918 #endif 9919 } cn61xx; 9920 struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx; 9921 struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx; 9922 }; 9923 9924 union cvmx_ciu_timx { 9925 uint64_t u64; 9926 struct cvmx_ciu_timx_s { 9927 #ifdef __BIG_ENDIAN_BITFIELD 9928 uint64_t reserved_37_63:27; 9929 uint64_t one_shot:1; 9930 uint64_t len:36; 9931 #else 9932 uint64_t len:36; 9933 uint64_t one_shot:1; 9934 uint64_t reserved_37_63:27; 9935 #endif 9936 } s; 9937 struct cvmx_ciu_timx_s cn30xx; 9938 struct cvmx_ciu_timx_s cn31xx; 9939 struct cvmx_ciu_timx_s cn38xx; 9940 struct cvmx_ciu_timx_s cn38xxp2; 9941 struct cvmx_ciu_timx_s cn50xx; 9942 struct cvmx_ciu_timx_s cn52xx; 9943 struct cvmx_ciu_timx_s cn52xxp1; 9944 struct cvmx_ciu_timx_s cn56xx; 9945 struct cvmx_ciu_timx_s cn56xxp1; 9946 struct cvmx_ciu_timx_s cn58xx; 9947 struct cvmx_ciu_timx_s cn58xxp1; 9948 struct cvmx_ciu_timx_s cn61xx; 9949 struct cvmx_ciu_timx_s cn63xx; 9950 struct cvmx_ciu_timx_s cn63xxp1; 9951 struct cvmx_ciu_timx_s cn66xx; 9952 struct cvmx_ciu_timx_s cn68xx; 9953 struct cvmx_ciu_timx_s cn68xxp1; 9954 struct cvmx_ciu_timx_s cnf71xx; 9955 }; 9956 9957 union cvmx_ciu_tim_multi_cast { 9958 uint64_t u64; 9959 struct cvmx_ciu_tim_multi_cast_s { 9960 #ifdef __BIG_ENDIAN_BITFIELD 9961 uint64_t reserved_1_63:63; 9962 uint64_t en:1; 9963 #else 9964 uint64_t en:1; 9965 uint64_t reserved_1_63:63; 9966 #endif 9967 } s; 9968 struct cvmx_ciu_tim_multi_cast_s cn61xx; 9969 struct cvmx_ciu_tim_multi_cast_s cn66xx; 9970 struct cvmx_ciu_tim_multi_cast_s cnf71xx; 9971 }; 9972 9973 union cvmx_ciu_wdogx { 9974 uint64_t u64; 9975 struct cvmx_ciu_wdogx_s { 9976 #ifdef __BIG_ENDIAN_BITFIELD 9977 uint64_t reserved_46_63:18; 9978 uint64_t gstopen:1; 9979 uint64_t dstop:1; 9980 uint64_t cnt:24; 9981 uint64_t len:16; 9982 uint64_t state:2; 9983 uint64_t mode:2; 9984 #else 9985 uint64_t mode:2; 9986 uint64_t state:2; 9987 uint64_t len:16; 9988 uint64_t cnt:24; 9989 uint64_t dstop:1; 9990 uint64_t gstopen:1; 9991 uint64_t reserved_46_63:18; 9992 #endif 9993 } s; 9994 struct cvmx_ciu_wdogx_s cn30xx; 9995 struct cvmx_ciu_wdogx_s cn31xx; 9996 struct cvmx_ciu_wdogx_s cn38xx; 9997 struct cvmx_ciu_wdogx_s cn38xxp2; 9998 struct cvmx_ciu_wdogx_s cn50xx; 9999 struct cvmx_ciu_wdogx_s cn52xx; 10000 struct cvmx_ciu_wdogx_s cn52xxp1; 10001 struct cvmx_ciu_wdogx_s cn56xx; 10002 struct cvmx_ciu_wdogx_s cn56xxp1; 10003 struct cvmx_ciu_wdogx_s cn58xx; 10004 struct cvmx_ciu_wdogx_s cn58xxp1; 10005 struct cvmx_ciu_wdogx_s cn61xx; 10006 struct cvmx_ciu_wdogx_s cn63xx; 10007 struct cvmx_ciu_wdogx_s cn63xxp1; 10008 struct cvmx_ciu_wdogx_s cn66xx; 10009 struct cvmx_ciu_wdogx_s cn68xx; 10010 struct cvmx_ciu_wdogx_s cn68xxp1; 10011 struct cvmx_ciu_wdogx_s cnf71xx; 10012 }; 10013 10014 #endif 10015