1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * PCI Register definitions for the MIPS System Controller. 3384740dcSRalf Baechle * 4384740dcSRalf Baechle * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved. 5384740dcSRalf Baechle * 6384740dcSRalf Baechle * This file is subject to the terms and conditions of the GNU General Public 7384740dcSRalf Baechle * License. See the file "COPYING" in the main directory of this archive 8384740dcSRalf Baechle * for more details. 9384740dcSRalf Baechle */ 10384740dcSRalf Baechle 11384740dcSRalf Baechle #ifndef __ASM_MIPS_BOARDS_MSC01_IC_H 12384740dcSRalf Baechle #define __ASM_MIPS_BOARDS_MSC01_IC_H 13384740dcSRalf Baechle 14384740dcSRalf Baechle /***************************************************************************** 15384740dcSRalf Baechle * Register offset addresses 16384740dcSRalf Baechle *****************************************************************************/ 17384740dcSRalf Baechle 18384740dcSRalf Baechle #define MSC01_IC_RST_OFS 0x00008 /* Software reset */ 19384740dcSRalf Baechle #define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */ 20384740dcSRalf Baechle #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */ 21384740dcSRalf Baechle #define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */ 22384740dcSRalf Baechle #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */ 23384740dcSRalf Baechle #define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */ 24384740dcSRalf Baechle #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */ 25384740dcSRalf Baechle #define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */ 26384740dcSRalf Baechle #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */ 27384740dcSRalf Baechle #define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */ 28384740dcSRalf Baechle #define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */ 29384740dcSRalf Baechle #define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */ 30384740dcSRalf Baechle #define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */ 31384740dcSRalf Baechle #define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */ 32384740dcSRalf Baechle #define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */ 33384740dcSRalf Baechle #define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */ 34384740dcSRalf Baechle #define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */ 35384740dcSRalf Baechle #define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */ 36384740dcSRalf Baechle #define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */ 37384740dcSRalf Baechle #define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */ 38384740dcSRalf Baechle #define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */ 39384740dcSRalf Baechle #define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */ 40384740dcSRalf Baechle #define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */ 41384740dcSRalf Baechle #define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */ 42384740dcSRalf Baechle #define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */ 43384740dcSRalf Baechle #define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */ 44384740dcSRalf Baechle 45384740dcSRalf Baechle /***************************************************************************** 46384740dcSRalf Baechle * Register field encodings 47384740dcSRalf Baechle *****************************************************************************/ 48384740dcSRalf Baechle 49384740dcSRalf Baechle #define MSC01_IC_RST_RST_SHF 0 50384740dcSRalf Baechle #define MSC01_IC_RST_RST_MSK 0x00000001 51384740dcSRalf Baechle #define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK 52384740dcSRalf Baechle #define MSC01_IC_LVL_LVL_SHF 0 53384740dcSRalf Baechle #define MSC01_IC_LVL_LVL_MSK 0x000000ff 54384740dcSRalf Baechle #define MSC01_IC_LVL_SPUR_SHF 16 55384740dcSRalf Baechle #define MSC01_IC_LVL_SPUR_MSK 0x00010000 56384740dcSRalf Baechle #define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK 57384740dcSRalf Baechle #define MSC01_IC_RAMW_RIPL_SHF 0 58384740dcSRalf Baechle #define MSC01_IC_RAMW_RIPL_MSK 0x0000003f 59384740dcSRalf Baechle #define MSC01_IC_RAMW_DATA_SHF 6 60384740dcSRalf Baechle #define MSC01_IC_RAMW_DATA_MSK 0x00000fc0 61384740dcSRalf Baechle #define MSC01_IC_RAMW_ADDR_SHF 25 62384740dcSRalf Baechle #define MSC01_IC_RAMW_ADDR_MSK 0x7e000000 63384740dcSRalf Baechle #define MSC01_IC_RAMW_READ_SHF 31 64384740dcSRalf Baechle #define MSC01_IC_RAMW_READ_MSK 0x80000000 65384740dcSRalf Baechle #define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK 66384740dcSRalf Baechle #define MSC01_IC_OSB_OSB_SHF 0 67384740dcSRalf Baechle #define MSC01_IC_OSB_OSB_MSK 0x000000ff 68384740dcSRalf Baechle #define MSC01_IC_OSA_OSA_SHF 0 69384740dcSRalf Baechle #define MSC01_IC_OSA_OSA_MSK 0x000000ff 70384740dcSRalf Baechle #define MSC01_IC_GENA_GENA_SHF 0 71384740dcSRalf Baechle #define MSC01_IC_GENA_GENA_MSK 0x00000001 72384740dcSRalf Baechle #define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK 73384740dcSRalf Baechle #define MSC01_IC_CFG_DIS_SHF 0 74384740dcSRalf Baechle #define MSC01_IC_CFG_DIS_MSK 0x00000001 75384740dcSRalf Baechle #define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK 76384740dcSRalf Baechle #define MSC01_IC_CFG_SHFT_SHF 8 77384740dcSRalf Baechle #define MSC01_IC_CFG_SHFT_MSK 0x00000f00 78384740dcSRalf Baechle #define MSC01_IC_TCFG_ENA_SHF 0 79384740dcSRalf Baechle #define MSC01_IC_TCFG_ENA_MSK 0x00000001 80384740dcSRalf Baechle #define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK 81384740dcSRalf Baechle #define MSC01_IC_TCFG_INT_SHF 8 82384740dcSRalf Baechle #define MSC01_IC_TCFG_INT_MSK 0x00000100 83384740dcSRalf Baechle #define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK 84384740dcSRalf Baechle #define MSC01_IC_TCFG_EDGE_SHF 16 85384740dcSRalf Baechle #define MSC01_IC_TCFG_EDGE_MSK 0x00010000 86384740dcSRalf Baechle #define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK 87384740dcSRalf Baechle #define MSC01_IC_SUP_PRI_SHF 0 88384740dcSRalf Baechle #define MSC01_IC_SUP_PRI_MSK 0x00000007 89384740dcSRalf Baechle #define MSC01_IC_SUP_EDGE_SHF 8 90384740dcSRalf Baechle #define MSC01_IC_SUP_EDGE_MSK 0x00000100 91384740dcSRalf Baechle #define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK 92384740dcSRalf Baechle #define MSC01_IC_SUP_STEP 8 93384740dcSRalf Baechle 94384740dcSRalf Baechle /* 95384740dcSRalf Baechle * MIPS System controller interrupt register base. 96384740dcSRalf Baechle * 97384740dcSRalf Baechle */ 98384740dcSRalf Baechle 99384740dcSRalf Baechle /***************************************************************************** 100384740dcSRalf Baechle * Absolute register addresses 101384740dcSRalf Baechle *****************************************************************************/ 102384740dcSRalf Baechle 103384740dcSRalf Baechle #define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS) 104384740dcSRalf Baechle #define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS) 105384740dcSRalf Baechle #define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS) 106384740dcSRalf Baechle #define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS) 107384740dcSRalf Baechle #define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS) 108384740dcSRalf Baechle #define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS) 109384740dcSRalf Baechle #define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS) 110384740dcSRalf Baechle #define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS) 111384740dcSRalf Baechle #define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS) 112384740dcSRalf Baechle #define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS) 113384740dcSRalf Baechle #define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS) 114384740dcSRalf Baechle #define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS) 115384740dcSRalf Baechle #define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS) 116384740dcSRalf Baechle #define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS) 117384740dcSRalf Baechle #define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS) 118384740dcSRalf Baechle #define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS) 119384740dcSRalf Baechle #define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS) 120384740dcSRalf Baechle #define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS) 121384740dcSRalf Baechle #define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS) 122384740dcSRalf Baechle #define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS) 123384740dcSRalf Baechle #define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS) 124384740dcSRalf Baechle #define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS) 125384740dcSRalf Baechle #define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS) 126384740dcSRalf Baechle #define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS) 127384740dcSRalf Baechle #define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS) 128384740dcSRalf Baechle #define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS) 129384740dcSRalf Baechle 130384740dcSRalf Baechle /* 131384740dcSRalf Baechle * Soc-it interrupts are configurable. 132384740dcSRalf Baechle * Every board describes its IRQ mapping with this table. 133384740dcSRalf Baechle */ 134384740dcSRalf Baechle typedef struct msc_irqmap { 135384740dcSRalf Baechle int im_irq; 136384740dcSRalf Baechle int im_type; 137384740dcSRalf Baechle int im_lvl; 138384740dcSRalf Baechle } msc_irqmap_t; 139384740dcSRalf Baechle 140384740dcSRalf Baechle /* im_type */ 141384740dcSRalf Baechle #define MSC01_IRQ_LEVEL 0 142384740dcSRalf Baechle #define MSC01_IRQ_EDGE 1 143384740dcSRalf Baechle 144384740dcSRalf Baechle extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq); 145384740dcSRalf Baechle extern void ll_msc_irq(void); 146384740dcSRalf Baechle 147384740dcSRalf Baechle #endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ 148384740dcSRalf Baechle 149