1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #ifdef CONFIG_MIPS_MT_SMTC 22 #include <asm/mipsmtregs.h> 23 #include <asm/smtc.h> 24 #endif /* SMTC */ 25 #include <asm-generic/mm_hooks.h> 26 27 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 28 29 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 30 do { \ 31 void (*tlbmiss_handler_setup_pgd)(unsigned long); \ 32 extern u32 tlbmiss_handler_setup_pgd_array[16]; \ 33 \ 34 tlbmiss_handler_setup_pgd = \ 35 (__typeof__(tlbmiss_handler_setup_pgd)) tlbmiss_handler_setup_pgd_array; \ 36 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 37 } while (0) 38 39 #define TLBMISS_HANDLER_SETUP() \ 40 do { \ 41 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 42 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ 43 } while (0) 44 45 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 46 47 /* 48 * For the fast tlb miss handlers, we keep a per cpu array of pointers 49 * to the current pgd for each processor. Also, the proc. id is stuffed 50 * into the context register. 51 */ 52 extern unsigned long pgd_current[]; 53 54 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 55 pgd_current[smp_processor_id()] = (unsigned long)(pgd) 56 57 #ifdef CONFIG_32BIT 58 #define TLBMISS_HANDLER_SETUP() \ 59 write_c0_context((unsigned long) smp_processor_id() << 25); \ 60 back_to_back_c0_hazard(); \ 61 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 62 #endif 63 #ifdef CONFIG_64BIT 64 #define TLBMISS_HANDLER_SETUP() \ 65 write_c0_context((unsigned long) smp_processor_id() << 26); \ 66 back_to_back_c0_hazard(); \ 67 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 68 #endif 69 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 70 71 #define ASID_INC(asid) \ 72 ({ \ 73 unsigned long __asid = asid; \ 74 __asm__("1:\taddiu\t%0,1\t\t\t\t# patched\n\t" \ 75 ".section\t__asid_inc,\"a\"\n\t" \ 76 ".word\t1b\n\t" \ 77 ".previous" \ 78 :"=r" (__asid) \ 79 :"0" (__asid)); \ 80 __asid; \ 81 }) 82 #define ASID_MASK(asid) \ 83 ({ \ 84 unsigned long __asid = asid; \ 85 __asm__("1:\tandi\t%0,%1,0xfc0\t\t\t# patched\n\t" \ 86 ".section\t__asid_mask,\"a\"\n\t" \ 87 ".word\t1b\n\t" \ 88 ".previous" \ 89 :"=r" (__asid) \ 90 :"r" (__asid)); \ 91 __asid; \ 92 }) 93 #define ASID_VERSION_MASK \ 94 ({ \ 95 unsigned long __asid; \ 96 __asm__("1:\taddiu\t%0,$0,0xff00\t\t\t\t# patched\n\t" \ 97 ".section\t__asid_version_mask,\"a\"\n\t" \ 98 ".word\t1b\n\t" \ 99 ".previous" \ 100 :"=r" (__asid)); \ 101 __asid; \ 102 }) 103 #define ASID_FIRST_VERSION \ 104 ({ \ 105 unsigned long __asid = asid; \ 106 __asm__("1:\tli\t%0,0x100\t\t\t\t# patched\n\t" \ 107 ".section\t__asid_first_version,\"a\"\n\t" \ 108 ".word\t1b\n\t" \ 109 ".previous" \ 110 :"=r" (__asid)); \ 111 __asid; \ 112 }) 113 114 #define ASID_FIRST_VERSION_R3000 0x1000 115 #define ASID_FIRST_VERSION_R4000 0x100 116 #define ASID_FIRST_VERSION_R8000 0x1000 117 #define ASID_FIRST_VERSION_RM9000 0x1000 118 119 #ifdef CONFIG_MIPS_MT_SMTC 120 #define SMTC_HW_ASID_MASK 0xff 121 extern unsigned int smtc_asid_mask; 122 #endif 123 124 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 125 #define cpu_asid(cpu, mm) ASID_MASK(cpu_context((cpu), (mm))) 126 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 127 128 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 129 { 130 } 131 132 #ifndef CONFIG_MIPS_MT_SMTC 133 /* Normal, classic MIPS get_new_mmu_context */ 134 static inline void 135 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 136 { 137 extern void kvm_local_flush_tlb_all(void); 138 unsigned long asid = asid_cache(cpu); 139 140 if (!ASID_MASK((asid = ASID_INC(asid)))) { 141 if (cpu_has_vtag_icache) 142 flush_icache_all(); 143 #ifdef CONFIG_VIRTUALIZATION 144 kvm_local_flush_tlb_all(); /* start new asid cycle */ 145 #else 146 local_flush_tlb_all(); /* start new asid cycle */ 147 #endif 148 if (!asid) /* fix version if needed */ 149 asid = ASID_FIRST_VERSION; 150 } 151 152 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 153 } 154 155 #else /* CONFIG_MIPS_MT_SMTC */ 156 157 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) 158 159 #endif /* CONFIG_MIPS_MT_SMTC */ 160 161 /* 162 * Initialize the context related info for a new mm_struct 163 * instance. 164 */ 165 static inline int 166 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 167 { 168 int i; 169 170 for_each_possible_cpu(i) 171 cpu_context(i, mm) = 0; 172 173 return 0; 174 } 175 176 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 177 struct task_struct *tsk) 178 { 179 unsigned int cpu = smp_processor_id(); 180 unsigned long flags; 181 #ifdef CONFIG_MIPS_MT_SMTC 182 unsigned long oldasid; 183 unsigned long mtflags; 184 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 185 local_irq_save(flags); 186 mtflags = dvpe(); 187 #else /* Not SMTC */ 188 local_irq_save(flags); 189 #endif /* CONFIG_MIPS_MT_SMTC */ 190 191 /* Check if our ASID is of an older version and thus invalid */ 192 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 193 get_new_mmu_context(next, cpu); 194 #ifdef CONFIG_MIPS_MT_SMTC 195 /* 196 * If the EntryHi ASID being replaced happens to be 197 * the value flagged at ASID recycling time as having 198 * an extended life, clear the bit showing it being 199 * in use by this "CPU", and if that's the last bit, 200 * free up the ASID value for use and flush any old 201 * instances of it from the TLB. 202 */ 203 oldasid = ASID_MASK(read_c0_entryhi()); 204 if(smtc_live_asid[mytlb][oldasid]) { 205 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 206 if(smtc_live_asid[mytlb][oldasid] == 0) 207 smtc_flush_tlb_asid(oldasid); 208 } 209 /* 210 * Tread softly on EntryHi, and so long as we support 211 * having ASID_MASK smaller than the hardware maximum, 212 * make sure no "soft" bits become "hard"... 213 */ 214 write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) | 215 cpu_asid(cpu, next)); 216 ehb(); /* Make sure it propagates to TCStatus */ 217 evpe(mtflags); 218 #else 219 write_c0_entryhi(cpu_asid(cpu, next)); 220 #endif /* CONFIG_MIPS_MT_SMTC */ 221 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 222 223 /* 224 * Mark current->active_mm as not "active" anymore. 225 * We don't want to mislead possible IPI tlb flush routines. 226 */ 227 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 228 cpumask_set_cpu(cpu, mm_cpumask(next)); 229 230 local_irq_restore(flags); 231 } 232 233 /* 234 * Destroy context related info for an mm_struct that is about 235 * to be put to rest. 236 */ 237 static inline void destroy_context(struct mm_struct *mm) 238 { 239 } 240 241 #define deactivate_mm(tsk, mm) do { } while (0) 242 243 /* 244 * After we have set current->mm to a new value, this activates 245 * the context for the new mm so we see the new mappings. 246 */ 247 static inline void 248 activate_mm(struct mm_struct *prev, struct mm_struct *next) 249 { 250 unsigned long flags; 251 unsigned int cpu = smp_processor_id(); 252 253 #ifdef CONFIG_MIPS_MT_SMTC 254 unsigned long oldasid; 255 unsigned long mtflags; 256 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 257 #endif /* CONFIG_MIPS_MT_SMTC */ 258 259 local_irq_save(flags); 260 261 /* Unconditionally get a new ASID. */ 262 get_new_mmu_context(next, cpu); 263 264 #ifdef CONFIG_MIPS_MT_SMTC 265 /* See comments for similar code above */ 266 mtflags = dvpe(); 267 oldasid = ASID_MASK(read_c0_entryhi()); 268 if(smtc_live_asid[mytlb][oldasid]) { 269 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 270 if(smtc_live_asid[mytlb][oldasid] == 0) 271 smtc_flush_tlb_asid(oldasid); 272 } 273 /* See comments for similar code above */ 274 write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) | 275 cpu_asid(cpu, next)); 276 ehb(); /* Make sure it propagates to TCStatus */ 277 evpe(mtflags); 278 #else 279 write_c0_entryhi(cpu_asid(cpu, next)); 280 #endif /* CONFIG_MIPS_MT_SMTC */ 281 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 282 283 /* mark mmu ownership change */ 284 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 285 cpumask_set_cpu(cpu, mm_cpumask(next)); 286 287 local_irq_restore(flags); 288 } 289 290 /* 291 * If mm is currently active_mm, we can't really drop it. Instead, 292 * we will get a new one for it. 293 */ 294 static inline void 295 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 296 { 297 unsigned long flags; 298 #ifdef CONFIG_MIPS_MT_SMTC 299 unsigned long oldasid; 300 /* Can't use spinlock because called from TLB flush within DVPE */ 301 unsigned int prevvpe; 302 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 303 #endif /* CONFIG_MIPS_MT_SMTC */ 304 305 local_irq_save(flags); 306 307 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 308 get_new_mmu_context(mm, cpu); 309 #ifdef CONFIG_MIPS_MT_SMTC 310 /* See comments for similar code above */ 311 prevvpe = dvpe(); 312 oldasid = ASID_MASK(read_c0_entryhi()); 313 if (smtc_live_asid[mytlb][oldasid]) { 314 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 315 if(smtc_live_asid[mytlb][oldasid] == 0) 316 smtc_flush_tlb_asid(oldasid); 317 } 318 /* See comments for similar code above */ 319 write_c0_entryhi((read_c0_entryhi() & ~SMTC_HW_ASID_MASK) 320 | cpu_asid(cpu, mm)); 321 ehb(); /* Make sure it propagates to TCStatus */ 322 evpe(prevvpe); 323 #else /* not CONFIG_MIPS_MT_SMTC */ 324 write_c0_entryhi(cpu_asid(cpu, mm)); 325 #endif /* CONFIG_MIPS_MT_SMTC */ 326 } else { 327 /* will get a new context next time */ 328 #ifndef CONFIG_MIPS_MT_SMTC 329 cpu_context(cpu, mm) = 0; 330 #else /* SMTC */ 331 int i; 332 333 /* SMTC shares the TLB (and ASIDs) across VPEs */ 334 for_each_online_cpu(i) { 335 if((smtc_status & SMTC_TLB_SHARED) 336 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 337 cpu_context(i, mm) = 0; 338 } 339 #endif /* CONFIG_MIPS_MT_SMTC */ 340 } 341 local_irq_restore(flags); 342 } 343 344 #endif /* _ASM_MMU_CONTEXT_H */ 345