1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #include <asm-generic/mm_hooks.h> 22 23 #define htw_set_pwbase(pgd) \ 24 do { \ 25 if (cpu_has_htw) { \ 26 write_c0_pwbase(pgd); \ 27 back_to_back_c0_hazard(); \ 28 htw_reset(); \ 29 } \ 30 } while (0) 31 32 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 33 do { \ 34 extern void tlbmiss_handler_setup_pgd(unsigned long); \ 35 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 36 htw_set_pwbase((unsigned long)pgd); \ 37 } while (0) 38 39 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 40 41 #define TLBMISS_HANDLER_RESTORE() \ 42 write_c0_xcontext((unsigned long) smp_processor_id() << \ 43 SMP_CPUID_REGSHIFT) 44 45 #define TLBMISS_HANDLER_SETUP() \ 46 do { \ 47 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 48 TLBMISS_HANDLER_RESTORE(); \ 49 } while (0) 50 51 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 52 53 /* 54 * For the fast tlb miss handlers, we keep a per cpu array of pointers 55 * to the current pgd for each processor. Also, the proc. id is stuffed 56 * into the context register. 57 */ 58 extern unsigned long pgd_current[]; 59 60 #define TLBMISS_HANDLER_RESTORE() \ 61 write_c0_context((unsigned long) smp_processor_id() << \ 62 SMP_CPUID_REGSHIFT) 63 64 #define TLBMISS_HANDLER_SETUP() \ 65 TLBMISS_HANDLER_RESTORE(); \ 66 back_to_back_c0_hazard(); \ 67 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 68 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 69 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 70 71 #define ASID_INC 0x40 72 #define ASID_MASK 0xfc0 73 74 #elif defined(CONFIG_CPU_R8000) 75 76 #define ASID_INC 0x10 77 #define ASID_MASK 0xff0 78 79 #else /* FIXME: not correct for R6000 */ 80 81 #define ASID_INC 0x1 82 #define ASID_MASK 0xff 83 84 #endif 85 86 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 87 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 88 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 89 90 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 91 { 92 } 93 94 /* 95 * All unused by hardware upper bits will be considered 96 * as a software asid extension. 97 */ 98 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) 99 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) 100 101 /* Normal, classic MIPS get_new_mmu_context */ 102 static inline void 103 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 104 { 105 extern void kvm_local_flush_tlb_all(void); 106 unsigned long asid = asid_cache(cpu); 107 108 if (! ((asid += ASID_INC) & ASID_MASK) ) { 109 if (cpu_has_vtag_icache) 110 flush_icache_all(); 111 #ifdef CONFIG_KVM 112 kvm_local_flush_tlb_all(); /* start new asid cycle */ 113 #else 114 local_flush_tlb_all(); /* start new asid cycle */ 115 #endif 116 if (!asid) /* fix version if needed */ 117 asid = ASID_FIRST_VERSION; 118 } 119 120 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 121 } 122 123 /* 124 * Initialize the context related info for a new mm_struct 125 * instance. 126 */ 127 static inline int 128 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 129 { 130 int i; 131 132 for_each_possible_cpu(i) 133 cpu_context(i, mm) = 0; 134 135 return 0; 136 } 137 138 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 139 struct task_struct *tsk) 140 { 141 unsigned int cpu = smp_processor_id(); 142 unsigned long flags; 143 local_irq_save(flags); 144 145 /* Check if our ASID is of an older version and thus invalid */ 146 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 147 get_new_mmu_context(next, cpu); 148 write_c0_entryhi(cpu_asid(cpu, next)); 149 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 150 151 /* 152 * Mark current->active_mm as not "active" anymore. 153 * We don't want to mislead possible IPI tlb flush routines. 154 */ 155 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 156 cpumask_set_cpu(cpu, mm_cpumask(next)); 157 158 local_irq_restore(flags); 159 } 160 161 /* 162 * Destroy context related info for an mm_struct that is about 163 * to be put to rest. 164 */ 165 static inline void destroy_context(struct mm_struct *mm) 166 { 167 } 168 169 #define deactivate_mm(tsk, mm) do { } while (0) 170 171 /* 172 * After we have set current->mm to a new value, this activates 173 * the context for the new mm so we see the new mappings. 174 */ 175 static inline void 176 activate_mm(struct mm_struct *prev, struct mm_struct *next) 177 { 178 unsigned long flags; 179 unsigned int cpu = smp_processor_id(); 180 181 local_irq_save(flags); 182 183 /* Unconditionally get a new ASID. */ 184 get_new_mmu_context(next, cpu); 185 186 write_c0_entryhi(cpu_asid(cpu, next)); 187 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 188 189 /* mark mmu ownership change */ 190 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 191 cpumask_set_cpu(cpu, mm_cpumask(next)); 192 193 local_irq_restore(flags); 194 } 195 196 /* 197 * If mm is currently active_mm, we can't really drop it. Instead, 198 * we will get a new one for it. 199 */ 200 static inline void 201 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 202 { 203 unsigned long flags; 204 205 local_irq_save(flags); 206 207 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 208 get_new_mmu_context(mm, cpu); 209 write_c0_entryhi(cpu_asid(cpu, mm)); 210 } else { 211 /* will get a new context next time */ 212 cpu_context(cpu, mm) = 0; 213 } 214 local_irq_restore(flags); 215 } 216 217 #endif /* _ASM_MMU_CONTEXT_H */ 218