1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #ifdef CONFIG_MIPS_MT_SMTC 22 #include <asm/mipsmtregs.h> 23 #include <asm/smtc.h> 24 #endif /* SMTC */ 25 #include <asm-generic/mm_hooks.h> 26 27 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 28 29 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 30 do { \ 31 extern void tlbmiss_handler_setup_pgd(unsigned long); \ 32 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 33 } while (0) 34 35 #define TLBMISS_HANDLER_SETUP() \ 36 do { \ 37 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 38 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ 39 } while (0) 40 41 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 42 43 /* 44 * For the fast tlb miss handlers, we keep a per cpu array of pointers 45 * to the current pgd for each processor. Also, the proc. id is stuffed 46 * into the context register. 47 */ 48 extern unsigned long pgd_current[]; 49 50 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 51 pgd_current[smp_processor_id()] = (unsigned long)(pgd) 52 53 #ifdef CONFIG_32BIT 54 #define TLBMISS_HANDLER_SETUP() \ 55 write_c0_context((unsigned long) smp_processor_id() << 25); \ 56 back_to_back_c0_hazard(); \ 57 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 58 #endif 59 #ifdef CONFIG_64BIT 60 #define TLBMISS_HANDLER_SETUP() \ 61 write_c0_context((unsigned long) smp_processor_id() << 26); \ 62 back_to_back_c0_hazard(); \ 63 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 64 #endif 65 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 66 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 67 68 #define ASID_INC 0x40 69 #define ASID_MASK 0xfc0 70 71 #elif defined(CONFIG_CPU_R8000) 72 73 #define ASID_INC 0x10 74 #define ASID_MASK 0xff0 75 76 #elif defined(CONFIG_MIPS_MT_SMTC) 77 78 #define ASID_INC 0x1 79 extern unsigned long smtc_asid_mask; 80 #define ASID_MASK (smtc_asid_mask) 81 #define HW_ASID_MASK 0xff 82 /* End SMTC/34K debug hack */ 83 #else /* FIXME: not correct for R6000 */ 84 85 #define ASID_INC 0x1 86 #define ASID_MASK 0xff 87 88 #endif 89 90 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 91 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 92 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 93 94 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 95 { 96 } 97 98 /* 99 * All unused by hardware upper bits will be considered 100 * as a software asid extension. 101 */ 102 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) 103 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) 104 105 #ifndef CONFIG_MIPS_MT_SMTC 106 /* Normal, classic MIPS get_new_mmu_context */ 107 static inline void 108 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 109 { 110 extern void kvm_local_flush_tlb_all(void); 111 unsigned long asid = asid_cache(cpu); 112 113 if (! ((asid += ASID_INC) & ASID_MASK) ) { 114 if (cpu_has_vtag_icache) 115 flush_icache_all(); 116 #ifdef CONFIG_KVM 117 kvm_local_flush_tlb_all(); /* start new asid cycle */ 118 #else 119 local_flush_tlb_all(); /* start new asid cycle */ 120 #endif 121 if (!asid) /* fix version if needed */ 122 asid = ASID_FIRST_VERSION; 123 } 124 125 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 126 } 127 128 #else /* CONFIG_MIPS_MT_SMTC */ 129 130 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) 131 132 #endif /* CONFIG_MIPS_MT_SMTC */ 133 134 /* 135 * Initialize the context related info for a new mm_struct 136 * instance. 137 */ 138 static inline int 139 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 140 { 141 int i; 142 143 for_each_possible_cpu(i) 144 cpu_context(i, mm) = 0; 145 146 return 0; 147 } 148 149 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 150 struct task_struct *tsk) 151 { 152 unsigned int cpu = smp_processor_id(); 153 unsigned long flags; 154 #ifdef CONFIG_MIPS_MT_SMTC 155 unsigned long oldasid; 156 unsigned long mtflags; 157 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 158 local_irq_save(flags); 159 mtflags = dvpe(); 160 #else /* Not SMTC */ 161 local_irq_save(flags); 162 #endif /* CONFIG_MIPS_MT_SMTC */ 163 164 /* Check if our ASID is of an older version and thus invalid */ 165 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 166 get_new_mmu_context(next, cpu); 167 #ifdef CONFIG_MIPS_MT_SMTC 168 /* 169 * If the EntryHi ASID being replaced happens to be 170 * the value flagged at ASID recycling time as having 171 * an extended life, clear the bit showing it being 172 * in use by this "CPU", and if that's the last bit, 173 * free up the ASID value for use and flush any old 174 * instances of it from the TLB. 175 */ 176 oldasid = (read_c0_entryhi() & ASID_MASK); 177 if(smtc_live_asid[mytlb][oldasid]) { 178 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 179 if(smtc_live_asid[mytlb][oldasid] == 0) 180 smtc_flush_tlb_asid(oldasid); 181 } 182 /* 183 * Tread softly on EntryHi, and so long as we support 184 * having ASID_MASK smaller than the hardware maximum, 185 * make sure no "soft" bits become "hard"... 186 */ 187 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 188 cpu_asid(cpu, next)); 189 ehb(); /* Make sure it propagates to TCStatus */ 190 evpe(mtflags); 191 #else 192 write_c0_entryhi(cpu_asid(cpu, next)); 193 #endif /* CONFIG_MIPS_MT_SMTC */ 194 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 195 196 /* 197 * Mark current->active_mm as not "active" anymore. 198 * We don't want to mislead possible IPI tlb flush routines. 199 */ 200 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 201 cpumask_set_cpu(cpu, mm_cpumask(next)); 202 203 local_irq_restore(flags); 204 } 205 206 /* 207 * Destroy context related info for an mm_struct that is about 208 * to be put to rest. 209 */ 210 static inline void destroy_context(struct mm_struct *mm) 211 { 212 } 213 214 #define deactivate_mm(tsk, mm) do { } while (0) 215 216 /* 217 * After we have set current->mm to a new value, this activates 218 * the context for the new mm so we see the new mappings. 219 */ 220 static inline void 221 activate_mm(struct mm_struct *prev, struct mm_struct *next) 222 { 223 unsigned long flags; 224 unsigned int cpu = smp_processor_id(); 225 226 #ifdef CONFIG_MIPS_MT_SMTC 227 unsigned long oldasid; 228 unsigned long mtflags; 229 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 230 #endif /* CONFIG_MIPS_MT_SMTC */ 231 232 local_irq_save(flags); 233 234 /* Unconditionally get a new ASID. */ 235 get_new_mmu_context(next, cpu); 236 237 #ifdef CONFIG_MIPS_MT_SMTC 238 /* See comments for similar code above */ 239 mtflags = dvpe(); 240 oldasid = read_c0_entryhi() & ASID_MASK; 241 if(smtc_live_asid[mytlb][oldasid]) { 242 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 243 if(smtc_live_asid[mytlb][oldasid] == 0) 244 smtc_flush_tlb_asid(oldasid); 245 } 246 /* See comments for similar code above */ 247 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 248 cpu_asid(cpu, next)); 249 ehb(); /* Make sure it propagates to TCStatus */ 250 evpe(mtflags); 251 #else 252 write_c0_entryhi(cpu_asid(cpu, next)); 253 #endif /* CONFIG_MIPS_MT_SMTC */ 254 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 255 256 /* mark mmu ownership change */ 257 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 258 cpumask_set_cpu(cpu, mm_cpumask(next)); 259 260 local_irq_restore(flags); 261 } 262 263 /* 264 * If mm is currently active_mm, we can't really drop it. Instead, 265 * we will get a new one for it. 266 */ 267 static inline void 268 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 269 { 270 unsigned long flags; 271 #ifdef CONFIG_MIPS_MT_SMTC 272 unsigned long oldasid; 273 /* Can't use spinlock because called from TLB flush within DVPE */ 274 unsigned int prevvpe; 275 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 276 #endif /* CONFIG_MIPS_MT_SMTC */ 277 278 local_irq_save(flags); 279 280 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 281 get_new_mmu_context(mm, cpu); 282 #ifdef CONFIG_MIPS_MT_SMTC 283 /* See comments for similar code above */ 284 prevvpe = dvpe(); 285 oldasid = (read_c0_entryhi() & ASID_MASK); 286 if (smtc_live_asid[mytlb][oldasid]) { 287 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 288 if(smtc_live_asid[mytlb][oldasid] == 0) 289 smtc_flush_tlb_asid(oldasid); 290 } 291 /* See comments for similar code above */ 292 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 293 | cpu_asid(cpu, mm)); 294 ehb(); /* Make sure it propagates to TCStatus */ 295 evpe(prevvpe); 296 #else /* not CONFIG_MIPS_MT_SMTC */ 297 write_c0_entryhi(cpu_asid(cpu, mm)); 298 #endif /* CONFIG_MIPS_MT_SMTC */ 299 } else { 300 /* will get a new context next time */ 301 #ifndef CONFIG_MIPS_MT_SMTC 302 cpu_context(cpu, mm) = 0; 303 #else /* SMTC */ 304 int i; 305 306 /* SMTC shares the TLB (and ASIDs) across VPEs */ 307 for_each_online_cpu(i) { 308 if((smtc_status & SMTC_TLB_SHARED) 309 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 310 cpu_context(i, mm) = 0; 311 } 312 #endif /* CONFIG_MIPS_MT_SMTC */ 313 } 314 local_irq_restore(flags); 315 } 316 317 #endif /* _ASM_MMU_CONTEXT_H */ 318