1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #ifdef CONFIG_MIPS_MT_SMTC 22 #include <asm/mipsmtregs.h> 23 #include <asm/smtc.h> 24 #endif /* SMTC */ 25 #include <asm-generic/mm_hooks.h> 26 27 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 28 29 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)) 31 32 extern void tlbmiss_handler_setup_pgd(unsigned long pgd); 33 34 #define TLBMISS_HANDLER_SETUP() \ 35 do { \ 36 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 37 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ 38 } while (0) 39 40 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 41 42 /* 43 * For the fast tlb miss handlers, we keep a per cpu array of pointers 44 * to the current pgd for each processor. Also, the proc. id is stuffed 45 * into the context register. 46 */ 47 extern unsigned long pgd_current[]; 48 49 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 50 pgd_current[smp_processor_id()] = (unsigned long)(pgd) 51 52 #ifdef CONFIG_32BIT 53 #define TLBMISS_HANDLER_SETUP() \ 54 write_c0_context((unsigned long) smp_processor_id() << 25); \ 55 back_to_back_c0_hazard(); \ 56 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 57 #endif 58 #ifdef CONFIG_64BIT 59 #define TLBMISS_HANDLER_SETUP() \ 60 write_c0_context((unsigned long) smp_processor_id() << 26); \ 61 back_to_back_c0_hazard(); \ 62 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 63 #endif 64 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 65 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 66 67 #define ASID_INC 0x40 68 #define ASID_MASK 0xfc0 69 70 #elif defined(CONFIG_CPU_R8000) 71 72 #define ASID_INC 0x10 73 #define ASID_MASK 0xff0 74 75 #elif defined(CONFIG_MIPS_MT_SMTC) 76 77 #define ASID_INC 0x1 78 extern unsigned long smtc_asid_mask; 79 #define ASID_MASK (smtc_asid_mask) 80 #define HW_ASID_MASK 0xff 81 /* End SMTC/34K debug hack */ 82 #else /* FIXME: not correct for R6000 */ 83 84 #define ASID_INC 0x1 85 #define ASID_MASK 0xff 86 87 #endif 88 89 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 90 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 91 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 92 93 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 94 { 95 } 96 97 /* 98 * All unused by hardware upper bits will be considered 99 * as a software asid extension. 100 */ 101 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) 102 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) 103 104 #ifndef CONFIG_MIPS_MT_SMTC 105 /* Normal, classic MIPS get_new_mmu_context */ 106 static inline void 107 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 108 { 109 unsigned long asid = asid_cache(cpu); 110 111 if (! ((asid += ASID_INC) & ASID_MASK) ) { 112 if (cpu_has_vtag_icache) 113 flush_icache_all(); 114 local_flush_tlb_all(); /* start new asid cycle */ 115 if (!asid) /* fix version if needed */ 116 asid = ASID_FIRST_VERSION; 117 } 118 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 119 } 120 121 #else /* CONFIG_MIPS_MT_SMTC */ 122 123 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) 124 125 #endif /* CONFIG_MIPS_MT_SMTC */ 126 127 /* 128 * Initialize the context related info for a new mm_struct 129 * instance. 130 */ 131 static inline int 132 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 133 { 134 int i; 135 136 for_each_online_cpu(i) 137 cpu_context(i, mm) = 0; 138 139 return 0; 140 } 141 142 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 143 struct task_struct *tsk) 144 { 145 unsigned int cpu = smp_processor_id(); 146 unsigned long flags; 147 #ifdef CONFIG_MIPS_MT_SMTC 148 unsigned long oldasid; 149 unsigned long mtflags; 150 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 151 local_irq_save(flags); 152 mtflags = dvpe(); 153 #else /* Not SMTC */ 154 local_irq_save(flags); 155 #endif /* CONFIG_MIPS_MT_SMTC */ 156 157 /* Check if our ASID is of an older version and thus invalid */ 158 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 159 get_new_mmu_context(next, cpu); 160 #ifdef CONFIG_MIPS_MT_SMTC 161 /* 162 * If the EntryHi ASID being replaced happens to be 163 * the value flagged at ASID recycling time as having 164 * an extended life, clear the bit showing it being 165 * in use by this "CPU", and if that's the last bit, 166 * free up the ASID value for use and flush any old 167 * instances of it from the TLB. 168 */ 169 oldasid = (read_c0_entryhi() & ASID_MASK); 170 if(smtc_live_asid[mytlb][oldasid]) { 171 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 172 if(smtc_live_asid[mytlb][oldasid] == 0) 173 smtc_flush_tlb_asid(oldasid); 174 } 175 /* 176 * Tread softly on EntryHi, and so long as we support 177 * having ASID_MASK smaller than the hardware maximum, 178 * make sure no "soft" bits become "hard"... 179 */ 180 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 181 cpu_asid(cpu, next)); 182 ehb(); /* Make sure it propagates to TCStatus */ 183 evpe(mtflags); 184 #else 185 write_c0_entryhi(cpu_asid(cpu, next)); 186 #endif /* CONFIG_MIPS_MT_SMTC */ 187 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 188 189 /* 190 * Mark current->active_mm as not "active" anymore. 191 * We don't want to mislead possible IPI tlb flush routines. 192 */ 193 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 194 cpumask_set_cpu(cpu, mm_cpumask(next)); 195 196 local_irq_restore(flags); 197 } 198 199 /* 200 * Destroy context related info for an mm_struct that is about 201 * to be put to rest. 202 */ 203 static inline void destroy_context(struct mm_struct *mm) 204 { 205 } 206 207 #define deactivate_mm(tsk, mm) do { } while (0) 208 209 /* 210 * After we have set current->mm to a new value, this activates 211 * the context for the new mm so we see the new mappings. 212 */ 213 static inline void 214 activate_mm(struct mm_struct *prev, struct mm_struct *next) 215 { 216 unsigned long flags; 217 unsigned int cpu = smp_processor_id(); 218 219 #ifdef CONFIG_MIPS_MT_SMTC 220 unsigned long oldasid; 221 unsigned long mtflags; 222 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 223 #endif /* CONFIG_MIPS_MT_SMTC */ 224 225 local_irq_save(flags); 226 227 /* Unconditionally get a new ASID. */ 228 get_new_mmu_context(next, cpu); 229 230 #ifdef CONFIG_MIPS_MT_SMTC 231 /* See comments for similar code above */ 232 mtflags = dvpe(); 233 oldasid = read_c0_entryhi() & ASID_MASK; 234 if(smtc_live_asid[mytlb][oldasid]) { 235 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 236 if(smtc_live_asid[mytlb][oldasid] == 0) 237 smtc_flush_tlb_asid(oldasid); 238 } 239 /* See comments for similar code above */ 240 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 241 cpu_asid(cpu, next)); 242 ehb(); /* Make sure it propagates to TCStatus */ 243 evpe(mtflags); 244 #else 245 write_c0_entryhi(cpu_asid(cpu, next)); 246 #endif /* CONFIG_MIPS_MT_SMTC */ 247 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 248 249 /* mark mmu ownership change */ 250 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 251 cpumask_set_cpu(cpu, mm_cpumask(next)); 252 253 local_irq_restore(flags); 254 } 255 256 /* 257 * If mm is currently active_mm, we can't really drop it. Instead, 258 * we will get a new one for it. 259 */ 260 static inline void 261 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 262 { 263 unsigned long flags; 264 #ifdef CONFIG_MIPS_MT_SMTC 265 unsigned long oldasid; 266 /* Can't use spinlock because called from TLB flush within DVPE */ 267 unsigned int prevvpe; 268 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 269 #endif /* CONFIG_MIPS_MT_SMTC */ 270 271 local_irq_save(flags); 272 273 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 274 get_new_mmu_context(mm, cpu); 275 #ifdef CONFIG_MIPS_MT_SMTC 276 /* See comments for similar code above */ 277 prevvpe = dvpe(); 278 oldasid = (read_c0_entryhi() & ASID_MASK); 279 if (smtc_live_asid[mytlb][oldasid]) { 280 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 281 if(smtc_live_asid[mytlb][oldasid] == 0) 282 smtc_flush_tlb_asid(oldasid); 283 } 284 /* See comments for similar code above */ 285 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 286 | cpu_asid(cpu, mm)); 287 ehb(); /* Make sure it propagates to TCStatus */ 288 evpe(prevvpe); 289 #else /* not CONFIG_MIPS_MT_SMTC */ 290 write_c0_entryhi(cpu_asid(cpu, mm)); 291 #endif /* CONFIG_MIPS_MT_SMTC */ 292 } else { 293 /* will get a new context next time */ 294 #ifndef CONFIG_MIPS_MT_SMTC 295 cpu_context(cpu, mm) = 0; 296 #else /* SMTC */ 297 int i; 298 299 /* SMTC shares the TLB (and ASIDs) across VPEs */ 300 for_each_online_cpu(i) { 301 if((smtc_status & SMTC_TLB_SHARED) 302 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 303 cpu_context(i, mm) = 0; 304 } 305 #endif /* CONFIG_MIPS_MT_SMTC */ 306 } 307 local_irq_restore(flags); 308 } 309 310 #endif /* _ASM_MMU_CONTEXT_H */ 311