1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #ifdef CONFIG_MIPS_MT_SMTC 22 #include <asm/mipsmtregs.h> 23 #include <asm/smtc.h> 24 #endif /* SMTC */ 25 #include <asm-generic/mm_hooks.h> 26 27 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 28 29 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)) 31 32 static inline void tlbmiss_handler_setup_pgd(unsigned long pgd) 33 { 34 /* Check for swapper_pg_dir and convert to physical address. */ 35 if ((pgd & CKSEG3) == CKSEG0) 36 pgd = CPHYSADDR(pgd); 37 write_c0_context(pgd << 11); 38 } 39 40 #define TLBMISS_HANDLER_SETUP() \ 41 do { \ 42 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 43 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ 44 } while (0) 45 46 47 static inline unsigned long get_current_pgd(void) 48 { 49 return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL); 50 } 51 52 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 53 54 /* 55 * For the fast tlb miss handlers, we keep a per cpu array of pointers 56 * to the current pgd for each processor. Also, the proc. id is stuffed 57 * into the context register. 58 */ 59 extern unsigned long pgd_current[]; 60 61 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 62 pgd_current[smp_processor_id()] = (unsigned long)(pgd) 63 64 #ifdef CONFIG_32BIT 65 #define TLBMISS_HANDLER_SETUP() \ 66 write_c0_context((unsigned long) smp_processor_id() << 25); \ 67 back_to_back_c0_hazard(); \ 68 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 69 #endif 70 #ifdef CONFIG_64BIT 71 #define TLBMISS_HANDLER_SETUP() \ 72 write_c0_context((unsigned long) smp_processor_id() << 26); \ 73 back_to_back_c0_hazard(); \ 74 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 75 #endif 76 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 77 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 78 79 #define ASID_INC 0x40 80 #define ASID_MASK 0xfc0 81 82 #elif defined(CONFIG_CPU_R8000) 83 84 #define ASID_INC 0x10 85 #define ASID_MASK 0xff0 86 87 #elif defined(CONFIG_CPU_RM9000) 88 89 #define ASID_INC 0x1 90 #define ASID_MASK 0xfff 91 92 /* SMTC/34K debug hack - but maybe we'll keep it */ 93 #elif defined(CONFIG_MIPS_MT_SMTC) 94 95 #define ASID_INC 0x1 96 extern unsigned long smtc_asid_mask; 97 #define ASID_MASK (smtc_asid_mask) 98 #define HW_ASID_MASK 0xff 99 /* End SMTC/34K debug hack */ 100 #else /* FIXME: not correct for R6000 */ 101 102 #define ASID_INC 0x1 103 #define ASID_MASK 0xff 104 105 #endif 106 107 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 108 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 109 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 110 111 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 112 { 113 } 114 115 /* 116 * All unused by hardware upper bits will be considered 117 * as a software asid extension. 118 */ 119 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) 120 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) 121 122 #ifndef CONFIG_MIPS_MT_SMTC 123 /* Normal, classic MIPS get_new_mmu_context */ 124 static inline void 125 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 126 { 127 unsigned long asid = asid_cache(cpu); 128 129 if (! ((asid += ASID_INC) & ASID_MASK) ) { 130 if (cpu_has_vtag_icache) 131 flush_icache_all(); 132 local_flush_tlb_all(); /* start new asid cycle */ 133 if (!asid) /* fix version if needed */ 134 asid = ASID_FIRST_VERSION; 135 } 136 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 137 } 138 139 #else /* CONFIG_MIPS_MT_SMTC */ 140 141 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) 142 143 #endif /* CONFIG_MIPS_MT_SMTC */ 144 145 /* 146 * Initialize the context related info for a new mm_struct 147 * instance. 148 */ 149 static inline int 150 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 151 { 152 int i; 153 154 for_each_online_cpu(i) 155 cpu_context(i, mm) = 0; 156 157 return 0; 158 } 159 160 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 161 struct task_struct *tsk) 162 { 163 unsigned int cpu = smp_processor_id(); 164 unsigned long flags; 165 #ifdef CONFIG_MIPS_MT_SMTC 166 unsigned long oldasid; 167 unsigned long mtflags; 168 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 169 local_irq_save(flags); 170 mtflags = dvpe(); 171 #else /* Not SMTC */ 172 local_irq_save(flags); 173 #endif /* CONFIG_MIPS_MT_SMTC */ 174 175 /* Check if our ASID is of an older version and thus invalid */ 176 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 177 get_new_mmu_context(next, cpu); 178 #ifdef CONFIG_MIPS_MT_SMTC 179 /* 180 * If the EntryHi ASID being replaced happens to be 181 * the value flagged at ASID recycling time as having 182 * an extended life, clear the bit showing it being 183 * in use by this "CPU", and if that's the last bit, 184 * free up the ASID value for use and flush any old 185 * instances of it from the TLB. 186 */ 187 oldasid = (read_c0_entryhi() & ASID_MASK); 188 if(smtc_live_asid[mytlb][oldasid]) { 189 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 190 if(smtc_live_asid[mytlb][oldasid] == 0) 191 smtc_flush_tlb_asid(oldasid); 192 } 193 /* 194 * Tread softly on EntryHi, and so long as we support 195 * having ASID_MASK smaller than the hardware maximum, 196 * make sure no "soft" bits become "hard"... 197 */ 198 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 199 cpu_asid(cpu, next)); 200 ehb(); /* Make sure it propagates to TCStatus */ 201 evpe(mtflags); 202 #else 203 write_c0_entryhi(cpu_asid(cpu, next)); 204 #endif /* CONFIG_MIPS_MT_SMTC */ 205 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 206 207 /* 208 * Mark current->active_mm as not "active" anymore. 209 * We don't want to mislead possible IPI tlb flush routines. 210 */ 211 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 212 cpumask_set_cpu(cpu, mm_cpumask(next)); 213 214 local_irq_restore(flags); 215 } 216 217 /* 218 * Destroy context related info for an mm_struct that is about 219 * to be put to rest. 220 */ 221 static inline void destroy_context(struct mm_struct *mm) 222 { 223 } 224 225 #define deactivate_mm(tsk, mm) do { } while (0) 226 227 /* 228 * After we have set current->mm to a new value, this activates 229 * the context for the new mm so we see the new mappings. 230 */ 231 static inline void 232 activate_mm(struct mm_struct *prev, struct mm_struct *next) 233 { 234 unsigned long flags; 235 unsigned int cpu = smp_processor_id(); 236 237 #ifdef CONFIG_MIPS_MT_SMTC 238 unsigned long oldasid; 239 unsigned long mtflags; 240 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 241 #endif /* CONFIG_MIPS_MT_SMTC */ 242 243 local_irq_save(flags); 244 245 /* Unconditionally get a new ASID. */ 246 get_new_mmu_context(next, cpu); 247 248 #ifdef CONFIG_MIPS_MT_SMTC 249 /* See comments for similar code above */ 250 mtflags = dvpe(); 251 oldasid = read_c0_entryhi() & ASID_MASK; 252 if(smtc_live_asid[mytlb][oldasid]) { 253 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 254 if(smtc_live_asid[mytlb][oldasid] == 0) 255 smtc_flush_tlb_asid(oldasid); 256 } 257 /* See comments for similar code above */ 258 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 259 cpu_asid(cpu, next)); 260 ehb(); /* Make sure it propagates to TCStatus */ 261 evpe(mtflags); 262 #else 263 write_c0_entryhi(cpu_asid(cpu, next)); 264 #endif /* CONFIG_MIPS_MT_SMTC */ 265 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 266 267 /* mark mmu ownership change */ 268 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 269 cpumask_set_cpu(cpu, mm_cpumask(next)); 270 271 local_irq_restore(flags); 272 } 273 274 /* 275 * If mm is currently active_mm, we can't really drop it. Instead, 276 * we will get a new one for it. 277 */ 278 static inline void 279 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 280 { 281 unsigned long flags; 282 #ifdef CONFIG_MIPS_MT_SMTC 283 unsigned long oldasid; 284 /* Can't use spinlock because called from TLB flush within DVPE */ 285 unsigned int prevvpe; 286 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 287 #endif /* CONFIG_MIPS_MT_SMTC */ 288 289 local_irq_save(flags); 290 291 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 292 get_new_mmu_context(mm, cpu); 293 #ifdef CONFIG_MIPS_MT_SMTC 294 /* See comments for similar code above */ 295 prevvpe = dvpe(); 296 oldasid = (read_c0_entryhi() & ASID_MASK); 297 if (smtc_live_asid[mytlb][oldasid]) { 298 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 299 if(smtc_live_asid[mytlb][oldasid] == 0) 300 smtc_flush_tlb_asid(oldasid); 301 } 302 /* See comments for similar code above */ 303 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 304 | cpu_asid(cpu, mm)); 305 ehb(); /* Make sure it propagates to TCStatus */ 306 evpe(prevvpe); 307 #else /* not CONFIG_MIPS_MT_SMTC */ 308 write_c0_entryhi(cpu_asid(cpu, mm)); 309 #endif /* CONFIG_MIPS_MT_SMTC */ 310 } else { 311 /* will get a new context next time */ 312 #ifndef CONFIG_MIPS_MT_SMTC 313 cpu_context(cpu, mm) = 0; 314 #else /* SMTC */ 315 int i; 316 317 /* SMTC shares the TLB (and ASIDs) across VPEs */ 318 for_each_online_cpu(i) { 319 if((smtc_status & SMTC_TLB_SHARED) 320 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 321 cpu_context(i, mm) = 0; 322 } 323 #endif /* CONFIG_MIPS_MT_SMTC */ 324 } 325 local_irq_restore(flags); 326 } 327 328 #endif /* _ASM_MMU_CONTEXT_H */ 329