1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/smp.h> 18 #include <linux/slab.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/dsemul.h> 22 #include <asm/hazards.h> 23 #include <asm/tlbflush.h> 24 #include <asm-generic/mm_hooks.h> 25 26 #define htw_set_pwbase(pgd) \ 27 do { \ 28 if (cpu_has_htw) { \ 29 write_c0_pwbase(pgd); \ 30 back_to_back_c0_hazard(); \ 31 } \ 32 } while (0) 33 34 extern void tlbmiss_handler_setup_pgd(unsigned long); 35 extern char tlbmiss_handler_setup_pgd_end[]; 36 37 /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */ 38 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 39 do { \ 40 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 41 htw_set_pwbase((unsigned long)pgd); \ 42 } while (0) 43 44 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 45 46 #define TLBMISS_HANDLER_RESTORE() \ 47 write_c0_xcontext((unsigned long) smp_processor_id() << \ 48 SMP_CPUID_REGSHIFT) 49 50 #define TLBMISS_HANDLER_SETUP() \ 51 do { \ 52 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 53 TLBMISS_HANDLER_RESTORE(); \ 54 } while (0) 55 56 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 57 58 /* 59 * For the fast tlb miss handlers, we keep a per cpu array of pointers 60 * to the current pgd for each processor. Also, the proc. id is stuffed 61 * into the context register. 62 */ 63 extern unsigned long pgd_current[]; 64 65 #define TLBMISS_HANDLER_RESTORE() \ 66 write_c0_context((unsigned long) smp_processor_id() << \ 67 SMP_CPUID_REGSHIFT) 68 69 #define TLBMISS_HANDLER_SETUP() \ 70 TLBMISS_HANDLER_RESTORE(); \ 71 back_to_back_c0_hazard(); \ 72 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 73 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 74 75 /* 76 * All unused by hardware upper bits will be considered 77 * as a software asid extension. 78 */ 79 static inline u64 asid_version_mask(unsigned int cpu) 80 { 81 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]); 82 83 return ~(u64)(asid_mask | (asid_mask - 1)); 84 } 85 86 static inline u64 asid_first_version(unsigned int cpu) 87 { 88 return ~asid_version_mask(cpu) + 1; 89 } 90 91 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 92 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 93 #define cpu_asid(cpu, mm) \ 94 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu])) 95 96 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 97 { 98 } 99 100 101 /* Normal, classic MIPS get_new_mmu_context */ 102 static inline void 103 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 104 { 105 u64 asid = asid_cache(cpu); 106 107 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) { 108 if (cpu_has_vtag_icache) 109 flush_icache_all(); 110 local_flush_tlb_all(); /* start new asid cycle */ 111 } 112 113 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 114 } 115 116 /* 117 * Initialize the context related info for a new mm_struct 118 * instance. 119 */ 120 static inline int 121 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 122 { 123 int i; 124 125 for_each_possible_cpu(i) 126 cpu_context(i, mm) = 0; 127 128 mm->context.bd_emupage_allocmap = NULL; 129 spin_lock_init(&mm->context.bd_emupage_lock); 130 init_waitqueue_head(&mm->context.bd_emupage_queue); 131 132 return 0; 133 } 134 135 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 136 struct task_struct *tsk) 137 { 138 unsigned int cpu = smp_processor_id(); 139 unsigned long flags; 140 local_irq_save(flags); 141 142 htw_stop(); 143 /* Check if our ASID is of an older version and thus invalid */ 144 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu)) 145 get_new_mmu_context(next, cpu); 146 write_c0_entryhi(cpu_asid(cpu, next)); 147 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 148 149 /* 150 * Mark current->active_mm as not "active" anymore. 151 * We don't want to mislead possible IPI tlb flush routines. 152 */ 153 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 154 cpumask_set_cpu(cpu, mm_cpumask(next)); 155 htw_start(); 156 157 local_irq_restore(flags); 158 } 159 160 /* 161 * Destroy context related info for an mm_struct that is about 162 * to be put to rest. 163 */ 164 static inline void destroy_context(struct mm_struct *mm) 165 { 166 dsemul_mm_cleanup(mm); 167 } 168 169 #define deactivate_mm(tsk, mm) do { } while (0) 170 171 /* 172 * After we have set current->mm to a new value, this activates 173 * the context for the new mm so we see the new mappings. 174 */ 175 static inline void 176 activate_mm(struct mm_struct *prev, struct mm_struct *next) 177 { 178 unsigned long flags; 179 unsigned int cpu = smp_processor_id(); 180 181 local_irq_save(flags); 182 183 htw_stop(); 184 /* Unconditionally get a new ASID. */ 185 get_new_mmu_context(next, cpu); 186 187 write_c0_entryhi(cpu_asid(cpu, next)); 188 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 189 190 /* mark mmu ownership change */ 191 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 192 cpumask_set_cpu(cpu, mm_cpumask(next)); 193 htw_start(); 194 195 local_irq_restore(flags); 196 } 197 198 /* 199 * If mm is currently active_mm, we can't really drop it. Instead, 200 * we will get a new one for it. 201 */ 202 static inline void 203 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 204 { 205 unsigned long flags; 206 207 local_irq_save(flags); 208 htw_stop(); 209 210 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 211 get_new_mmu_context(mm, cpu); 212 write_c0_entryhi(cpu_asid(cpu, mm)); 213 } else { 214 /* will get a new context next time */ 215 cpu_context(cpu, mm) = 0; 216 } 217 htw_start(); 218 local_irq_restore(flags); 219 } 220 221 #endif /* _ASM_MMU_CONTEXT_H */ 222