1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/dsemul.h> 20 #include <asm/hazards.h> 21 #include <asm/tlbflush.h> 22 #include <asm-generic/mm_hooks.h> 23 24 #define htw_set_pwbase(pgd) \ 25 do { \ 26 if (cpu_has_htw) { \ 27 write_c0_pwbase(pgd); \ 28 back_to_back_c0_hazard(); \ 29 } \ 30 } while (0) 31 32 extern void tlbmiss_handler_setup_pgd(unsigned long); 33 34 /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */ 35 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 36 do { \ 37 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 38 htw_set_pwbase((unsigned long)pgd); \ 39 } while (0) 40 41 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 42 43 #define TLBMISS_HANDLER_RESTORE() \ 44 write_c0_xcontext((unsigned long) smp_processor_id() << \ 45 SMP_CPUID_REGSHIFT) 46 47 #define TLBMISS_HANDLER_SETUP() \ 48 do { \ 49 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 50 TLBMISS_HANDLER_RESTORE(); \ 51 } while (0) 52 53 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 54 55 /* 56 * For the fast tlb miss handlers, we keep a per cpu array of pointers 57 * to the current pgd for each processor. Also, the proc. id is stuffed 58 * into the context register. 59 */ 60 extern unsigned long pgd_current[]; 61 62 #define TLBMISS_HANDLER_RESTORE() \ 63 write_c0_context((unsigned long) smp_processor_id() << \ 64 SMP_CPUID_REGSHIFT) 65 66 #define TLBMISS_HANDLER_SETUP() \ 67 TLBMISS_HANDLER_RESTORE(); \ 68 back_to_back_c0_hazard(); \ 69 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 70 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 71 72 /* 73 * All unused by hardware upper bits will be considered 74 * as a software asid extension. 75 */ 76 static unsigned long asid_version_mask(unsigned int cpu) 77 { 78 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]); 79 80 return ~(asid_mask | (asid_mask - 1)); 81 } 82 83 static unsigned long asid_first_version(unsigned int cpu) 84 { 85 return ~asid_version_mask(cpu) + 1; 86 } 87 88 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 89 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 90 #define cpu_asid(cpu, mm) \ 91 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu])) 92 93 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 94 { 95 } 96 97 98 /* Normal, classic MIPS get_new_mmu_context */ 99 static inline void 100 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 101 { 102 unsigned long asid = asid_cache(cpu); 103 104 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) { 105 if (cpu_has_vtag_icache) 106 flush_icache_all(); 107 local_flush_tlb_all(); /* start new asid cycle */ 108 if (!asid) /* fix version if needed */ 109 asid = asid_first_version(cpu); 110 } 111 112 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 113 } 114 115 /* 116 * Initialize the context related info for a new mm_struct 117 * instance. 118 */ 119 static inline int 120 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 121 { 122 int i; 123 124 for_each_possible_cpu(i) 125 cpu_context(i, mm) = 0; 126 127 atomic_set(&mm->context.fp_mode_switching, 0); 128 129 mm->context.bd_emupage_allocmap = NULL; 130 spin_lock_init(&mm->context.bd_emupage_lock); 131 init_waitqueue_head(&mm->context.bd_emupage_queue); 132 133 return 0; 134 } 135 136 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 137 struct task_struct *tsk) 138 { 139 unsigned int cpu = smp_processor_id(); 140 unsigned long flags; 141 local_irq_save(flags); 142 143 htw_stop(); 144 /* Check if our ASID is of an older version and thus invalid */ 145 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu)) 146 get_new_mmu_context(next, cpu); 147 write_c0_entryhi(cpu_asid(cpu, next)); 148 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 149 150 /* 151 * Mark current->active_mm as not "active" anymore. 152 * We don't want to mislead possible IPI tlb flush routines. 153 */ 154 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 155 cpumask_set_cpu(cpu, mm_cpumask(next)); 156 htw_start(); 157 158 local_irq_restore(flags); 159 } 160 161 /* 162 * Destroy context related info for an mm_struct that is about 163 * to be put to rest. 164 */ 165 static inline void destroy_context(struct mm_struct *mm) 166 { 167 dsemul_mm_cleanup(mm); 168 } 169 170 #define deactivate_mm(tsk, mm) do { } while (0) 171 172 /* 173 * After we have set current->mm to a new value, this activates 174 * the context for the new mm so we see the new mappings. 175 */ 176 static inline void 177 activate_mm(struct mm_struct *prev, struct mm_struct *next) 178 { 179 unsigned long flags; 180 unsigned int cpu = smp_processor_id(); 181 182 local_irq_save(flags); 183 184 htw_stop(); 185 /* Unconditionally get a new ASID. */ 186 get_new_mmu_context(next, cpu); 187 188 write_c0_entryhi(cpu_asid(cpu, next)); 189 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 190 191 /* mark mmu ownership change */ 192 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 193 cpumask_set_cpu(cpu, mm_cpumask(next)); 194 htw_start(); 195 196 local_irq_restore(flags); 197 } 198 199 /* 200 * If mm is currently active_mm, we can't really drop it. Instead, 201 * we will get a new one for it. 202 */ 203 static inline void 204 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 205 { 206 unsigned long flags; 207 208 local_irq_save(flags); 209 htw_stop(); 210 211 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 212 get_new_mmu_context(mm, cpu); 213 write_c0_entryhi(cpu_asid(cpu, mm)); 214 } else { 215 /* will get a new context next time */ 216 cpu_context(cpu, mm) = 0; 217 } 218 htw_start(); 219 local_irq_restore(flags); 220 } 221 222 #endif /* _ASM_MMU_CONTEXT_H */ 223