1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/smp.h> 18 #include <linux/slab.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/dsemul.h> 22 #include <asm/hazards.h> 23 #include <asm/tlbflush.h> 24 #include <asm-generic/mm_hooks.h> 25 26 #define htw_set_pwbase(pgd) \ 27 do { \ 28 if (cpu_has_htw) { \ 29 write_c0_pwbase(pgd); \ 30 back_to_back_c0_hazard(); \ 31 } \ 32 } while (0) 33 34 extern void tlbmiss_handler_setup_pgd(unsigned long); 35 36 /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */ 37 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 38 do { \ 39 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 40 htw_set_pwbase((unsigned long)pgd); \ 41 } while (0) 42 43 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 44 45 #define TLBMISS_HANDLER_RESTORE() \ 46 write_c0_xcontext((unsigned long) smp_processor_id() << \ 47 SMP_CPUID_REGSHIFT) 48 49 #define TLBMISS_HANDLER_SETUP() \ 50 do { \ 51 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 52 TLBMISS_HANDLER_RESTORE(); \ 53 } while (0) 54 55 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 56 57 /* 58 * For the fast tlb miss handlers, we keep a per cpu array of pointers 59 * to the current pgd for each processor. Also, the proc. id is stuffed 60 * into the context register. 61 */ 62 extern unsigned long pgd_current[]; 63 64 #define TLBMISS_HANDLER_RESTORE() \ 65 write_c0_context((unsigned long) smp_processor_id() << \ 66 SMP_CPUID_REGSHIFT) 67 68 #define TLBMISS_HANDLER_SETUP() \ 69 TLBMISS_HANDLER_RESTORE(); \ 70 back_to_back_c0_hazard(); \ 71 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 72 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 73 74 /* 75 * All unused by hardware upper bits will be considered 76 * as a software asid extension. 77 */ 78 static unsigned long asid_version_mask(unsigned int cpu) 79 { 80 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]); 81 82 return ~(asid_mask | (asid_mask - 1)); 83 } 84 85 static unsigned long asid_first_version(unsigned int cpu) 86 { 87 return ~asid_version_mask(cpu) + 1; 88 } 89 90 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 91 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 92 #define cpu_asid(cpu, mm) \ 93 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu])) 94 95 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 96 { 97 } 98 99 100 /* Normal, classic MIPS get_new_mmu_context */ 101 static inline void 102 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 103 { 104 unsigned long asid = asid_cache(cpu); 105 106 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) { 107 if (cpu_has_vtag_icache) 108 flush_icache_all(); 109 local_flush_tlb_all(); /* start new asid cycle */ 110 if (!asid) /* fix version if needed */ 111 asid = asid_first_version(cpu); 112 } 113 114 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 115 } 116 117 /* 118 * Initialize the context related info for a new mm_struct 119 * instance. 120 */ 121 static inline int 122 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 123 { 124 int i; 125 126 for_each_possible_cpu(i) 127 cpu_context(i, mm) = 0; 128 129 atomic_set(&mm->context.fp_mode_switching, 0); 130 131 mm->context.bd_emupage_allocmap = NULL; 132 spin_lock_init(&mm->context.bd_emupage_lock); 133 init_waitqueue_head(&mm->context.bd_emupage_queue); 134 135 return 0; 136 } 137 138 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 139 struct task_struct *tsk) 140 { 141 unsigned int cpu = smp_processor_id(); 142 unsigned long flags; 143 local_irq_save(flags); 144 145 htw_stop(); 146 /* Check if our ASID is of an older version and thus invalid */ 147 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu)) 148 get_new_mmu_context(next, cpu); 149 write_c0_entryhi(cpu_asid(cpu, next)); 150 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 151 152 /* 153 * Mark current->active_mm as not "active" anymore. 154 * We don't want to mislead possible IPI tlb flush routines. 155 */ 156 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 157 cpumask_set_cpu(cpu, mm_cpumask(next)); 158 htw_start(); 159 160 local_irq_restore(flags); 161 } 162 163 /* 164 * Destroy context related info for an mm_struct that is about 165 * to be put to rest. 166 */ 167 static inline void destroy_context(struct mm_struct *mm) 168 { 169 dsemul_mm_cleanup(mm); 170 } 171 172 #define deactivate_mm(tsk, mm) do { } while (0) 173 174 /* 175 * After we have set current->mm to a new value, this activates 176 * the context for the new mm so we see the new mappings. 177 */ 178 static inline void 179 activate_mm(struct mm_struct *prev, struct mm_struct *next) 180 { 181 unsigned long flags; 182 unsigned int cpu = smp_processor_id(); 183 184 local_irq_save(flags); 185 186 htw_stop(); 187 /* Unconditionally get a new ASID. */ 188 get_new_mmu_context(next, cpu); 189 190 write_c0_entryhi(cpu_asid(cpu, next)); 191 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 192 193 /* mark mmu ownership change */ 194 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 195 cpumask_set_cpu(cpu, mm_cpumask(next)); 196 htw_start(); 197 198 local_irq_restore(flags); 199 } 200 201 /* 202 * If mm is currently active_mm, we can't really drop it. Instead, 203 * we will get a new one for it. 204 */ 205 static inline void 206 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 207 { 208 unsigned long flags; 209 210 local_irq_save(flags); 211 htw_stop(); 212 213 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 214 get_new_mmu_context(mm, cpu); 215 write_c0_entryhi(cpu_asid(cpu, mm)); 216 } else { 217 /* will get a new context next time */ 218 cpu_context(cpu, mm) = 0; 219 } 220 htw_start(); 221 local_irq_restore(flags); 222 } 223 224 #endif /* _ASM_MMU_CONTEXT_H */ 225