1 /*
2  * Switch a MMU context.
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9  * Copyright (C) 1999 Silicon Graphics, Inc.
10  */
11 #ifndef _ASM_MMU_CONTEXT_H
12 #define _ASM_MMU_CONTEXT_H
13 
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
17 #include <linux/slab.h>
18 #include <asm/cacheflush.h>
19 #include <asm/hazards.h>
20 #include <asm/tlbflush.h>
21 #include <asm-generic/mm_hooks.h>
22 
23 #define htw_set_pwbase(pgd)						\
24 do {									\
25 	if (cpu_has_htw) {						\
26 		write_c0_pwbase(pgd);					\
27 		back_to_back_c0_hazard();				\
28 	}								\
29 } while (0)
30 
31 #define TLBMISS_HANDLER_SETUP_PGD(pgd)					\
32 do {									\
33 	extern void tlbmiss_handler_setup_pgd(unsigned long);		\
34 	tlbmiss_handler_setup_pgd((unsigned long)(pgd));		\
35 	htw_set_pwbase((unsigned long)pgd);				\
36 } while (0)
37 
38 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
39 
40 #define TLBMISS_HANDLER_RESTORE()					\
41 	write_c0_xcontext((unsigned long) smp_processor_id() <<		\
42 			  SMP_CPUID_REGSHIFT)
43 
44 #define TLBMISS_HANDLER_SETUP()						\
45 	do {								\
46 		TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);		\
47 		TLBMISS_HANDLER_RESTORE();				\
48 	} while (0)
49 
50 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
51 
52 /*
53  * For the fast tlb miss handlers, we keep a per cpu array of pointers
54  * to the current pgd for each processor. Also, the proc. id is stuffed
55  * into the context register.
56  */
57 extern unsigned long pgd_current[];
58 
59 #define TLBMISS_HANDLER_RESTORE()					\
60 	write_c0_context((unsigned long) smp_processor_id() <<		\
61 			 SMP_CPUID_REGSHIFT)
62 
63 #define TLBMISS_HANDLER_SETUP()						\
64 	TLBMISS_HANDLER_RESTORE();					\
65 	back_to_back_c0_hazard();					\
66 	TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
67 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
68 
69 /*
70  *  All unused by hardware upper bits will be considered
71  *  as a software asid extension.
72  */
73 static unsigned long asid_version_mask(unsigned int cpu)
74 {
75 	unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
76 
77 	return ~(asid_mask | (asid_mask - 1));
78 }
79 
80 static unsigned long asid_first_version(unsigned int cpu)
81 {
82 	return ~asid_version_mask(cpu) + 1;
83 }
84 
85 #define cpu_context(cpu, mm)	((mm)->context.asid[cpu])
86 #define asid_cache(cpu)		(cpu_data[cpu].asid_cache)
87 #define cpu_asid(cpu, mm) \
88 	(cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
89 
90 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
91 {
92 }
93 
94 
95 /* Normal, classic MIPS get_new_mmu_context */
96 static inline void
97 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
98 {
99 	extern void kvm_local_flush_tlb_all(void);
100 	unsigned long asid = asid_cache(cpu);
101 
102 	if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) {
103 		if (cpu_has_vtag_icache)
104 			flush_icache_all();
105 #ifdef CONFIG_KVM
106 		kvm_local_flush_tlb_all();      /* start new asid cycle */
107 #else
108 		local_flush_tlb_all();	/* start new asid cycle */
109 #endif
110 		if (!asid)		/* fix version if needed */
111 			asid = asid_first_version(cpu);
112 	}
113 
114 	cpu_context(cpu, mm) = asid_cache(cpu) = asid;
115 }
116 
117 /*
118  * Initialize the context related info for a new mm_struct
119  * instance.
120  */
121 static inline int
122 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
123 {
124 	int i;
125 
126 	for_each_possible_cpu(i)
127 		cpu_context(i, mm) = 0;
128 
129 	atomic_set(&mm->context.fp_mode_switching, 0);
130 
131 	return 0;
132 }
133 
134 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
135 			     struct task_struct *tsk)
136 {
137 	unsigned int cpu = smp_processor_id();
138 	unsigned long flags;
139 	local_irq_save(flags);
140 
141 	htw_stop();
142 	/* Check if our ASID is of an older version and thus invalid */
143 	if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu))
144 		get_new_mmu_context(next, cpu);
145 	write_c0_entryhi(cpu_asid(cpu, next));
146 	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
147 
148 	/*
149 	 * Mark current->active_mm as not "active" anymore.
150 	 * We don't want to mislead possible IPI tlb flush routines.
151 	 */
152 	cpumask_clear_cpu(cpu, mm_cpumask(prev));
153 	cpumask_set_cpu(cpu, mm_cpumask(next));
154 	htw_start();
155 
156 	local_irq_restore(flags);
157 }
158 
159 /*
160  * Destroy context related info for an mm_struct that is about
161  * to be put to rest.
162  */
163 static inline void destroy_context(struct mm_struct *mm)
164 {
165 }
166 
167 #define deactivate_mm(tsk, mm)	do { } while (0)
168 
169 /*
170  * After we have set current->mm to a new value, this activates
171  * the context for the new mm so we see the new mappings.
172  */
173 static inline void
174 activate_mm(struct mm_struct *prev, struct mm_struct *next)
175 {
176 	unsigned long flags;
177 	unsigned int cpu = smp_processor_id();
178 
179 	local_irq_save(flags);
180 
181 	htw_stop();
182 	/* Unconditionally get a new ASID.  */
183 	get_new_mmu_context(next, cpu);
184 
185 	write_c0_entryhi(cpu_asid(cpu, next));
186 	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
187 
188 	/* mark mmu ownership change */
189 	cpumask_clear_cpu(cpu, mm_cpumask(prev));
190 	cpumask_set_cpu(cpu, mm_cpumask(next));
191 	htw_start();
192 
193 	local_irq_restore(flags);
194 }
195 
196 /*
197  * If mm is currently active_mm, we can't really drop it.  Instead,
198  * we will get a new one for it.
199  */
200 static inline void
201 drop_mmu_context(struct mm_struct *mm, unsigned cpu)
202 {
203 	unsigned long flags;
204 
205 	local_irq_save(flags);
206 	htw_stop();
207 
208 	if (cpumask_test_cpu(cpu, mm_cpumask(mm)))  {
209 		get_new_mmu_context(mm, cpu);
210 		write_c0_entryhi(cpu_asid(cpu, mm));
211 	} else {
212 		/* will get a new context next time */
213 		cpu_context(cpu, mm) = 0;
214 	}
215 	htw_start();
216 	local_irq_restore(flags);
217 }
218 
219 #endif /* _ASM_MMU_CONTEXT_H */
220