1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <linux/types.h> 18 #include <asm/hazards.h> 19 #include <asm/war.h> 20 21 /* 22 * The following macros are especially useful for __asm__ 23 * inline assembler. 24 */ 25 #ifndef __STR 26 #define __STR(x) #x 27 #endif 28 #ifndef STR 29 #define STR(x) __STR(x) 30 #endif 31 32 /* 33 * Configure language 34 */ 35 #ifdef __ASSEMBLY__ 36 #define _ULCAST_ 37 #else 38 #define _ULCAST_ (unsigned long) 39 #endif 40 41 /* 42 * Coprocessor 0 register names 43 */ 44 #define CP0_INDEX $0 45 #define CP0_RANDOM $1 46 #define CP0_ENTRYLO0 $2 47 #define CP0_ENTRYLO1 $3 48 #define CP0_CONF $3 49 #define CP0_CONTEXT $4 50 #define CP0_PAGEMASK $5 51 #define CP0_WIRED $6 52 #define CP0_INFO $7 53 #define CP0_BADVADDR $8 54 #define CP0_COUNT $9 55 #define CP0_ENTRYHI $10 56 #define CP0_COMPARE $11 57 #define CP0_STATUS $12 58 #define CP0_CAUSE $13 59 #define CP0_EPC $14 60 #define CP0_PRID $15 61 #define CP0_CONFIG $16 62 #define CP0_LLADDR $17 63 #define CP0_WATCHLO $18 64 #define CP0_WATCHHI $19 65 #define CP0_XCONTEXT $20 66 #define CP0_FRAMEMASK $21 67 #define CP0_DIAGNOSTIC $22 68 #define CP0_DEBUG $23 69 #define CP0_DEPC $24 70 #define CP0_PERFORMANCE $25 71 #define CP0_ECC $26 72 #define CP0_CACHEERR $27 73 #define CP0_TAGLO $28 74 #define CP0_TAGHI $29 75 #define CP0_ERROREPC $30 76 #define CP0_DESAVE $31 77 78 /* 79 * R4640/R4650 cp0 register names. These registers are listed 80 * here only for completeness; without MMU these CPUs are not useable 81 * by Linux. A future ELKS port might take make Linux run on them 82 * though ... 83 */ 84 #define CP0_IBASE $0 85 #define CP0_IBOUND $1 86 #define CP0_DBASE $2 87 #define CP0_DBOUND $3 88 #define CP0_CALG $17 89 #define CP0_IWATCH $18 90 #define CP0_DWATCH $19 91 92 /* 93 * Coprocessor 0 Set 1 register names 94 */ 95 #define CP0_S1_DERRADDR0 $26 96 #define CP0_S1_DERRADDR1 $27 97 #define CP0_S1_INTCONTROL $20 98 99 /* 100 * Coprocessor 0 Set 2 register names 101 */ 102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 103 104 /* 105 * Coprocessor 0 Set 3 register names 106 */ 107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 108 109 /* 110 * TX39 Series 111 */ 112 #define CP0_TX39_CACHE $7 113 114 /* 115 * Coprocessor 1 (FPU) register names 116 */ 117 #define CP1_REVISION $0 118 #define CP1_STATUS $31 119 120 /* 121 * FPU Status Register Values 122 */ 123 /* 124 * Status Register Values 125 */ 126 127 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 128 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 130 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 131 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 132 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 133 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 134 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 135 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 136 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 137 138 /* 139 * Bits 18 - 20 of the FPU Status Register will be read as 0, 140 * and should be written as zero. 141 */ 142 #define FPU_CSR_RSVD 0x001c0000 143 144 /* 145 * X the exception cause indicator 146 * E the exception enable 147 * S the sticky/flag bit 148 */ 149 #define FPU_CSR_ALL_X 0x0003f000 150 #define FPU_CSR_UNI_X 0x00020000 151 #define FPU_CSR_INV_X 0x00010000 152 #define FPU_CSR_DIV_X 0x00008000 153 #define FPU_CSR_OVF_X 0x00004000 154 #define FPU_CSR_UDF_X 0x00002000 155 #define FPU_CSR_INE_X 0x00001000 156 157 #define FPU_CSR_ALL_E 0x00000f80 158 #define FPU_CSR_INV_E 0x00000800 159 #define FPU_CSR_DIV_E 0x00000400 160 #define FPU_CSR_OVF_E 0x00000200 161 #define FPU_CSR_UDF_E 0x00000100 162 #define FPU_CSR_INE_E 0x00000080 163 164 #define FPU_CSR_ALL_S 0x0000007c 165 #define FPU_CSR_INV_S 0x00000040 166 #define FPU_CSR_DIV_S 0x00000020 167 #define FPU_CSR_OVF_S 0x00000010 168 #define FPU_CSR_UDF_S 0x00000008 169 #define FPU_CSR_INE_S 0x00000004 170 171 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 172 #define FPU_CSR_RM 0x00000003 173 #define FPU_CSR_RN 0x0 /* nearest */ 174 #define FPU_CSR_RZ 0x1 /* towards zero */ 175 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 176 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 177 178 179 /* 180 * Values for PageMask register 181 */ 182 #ifdef CONFIG_CPU_VR41XX 183 184 /* Why doesn't stupidity hurt ... */ 185 186 #define PM_1K 0x00000000 187 #define PM_4K 0x00001800 188 #define PM_16K 0x00007800 189 #define PM_64K 0x0001f800 190 #define PM_256K 0x0007f800 191 192 #else 193 194 #define PM_4K 0x00000000 195 #define PM_8K 0x00002000 196 #define PM_16K 0x00006000 197 #define PM_32K 0x0000e000 198 #define PM_64K 0x0001e000 199 #define PM_128K 0x0003e000 200 #define PM_256K 0x0007e000 201 #define PM_512K 0x000fe000 202 #define PM_1M 0x001fe000 203 #define PM_2M 0x003fe000 204 #define PM_4M 0x007fe000 205 #define PM_8M 0x00ffe000 206 #define PM_16M 0x01ffe000 207 #define PM_32M 0x03ffe000 208 #define PM_64M 0x07ffe000 209 #define PM_256M 0x1fffe000 210 #define PM_1G 0x7fffe000 211 212 #endif 213 214 /* 215 * Default page size for a given kernel configuration 216 */ 217 #ifdef CONFIG_PAGE_SIZE_4KB 218 #define PM_DEFAULT_MASK PM_4K 219 #elif defined(CONFIG_PAGE_SIZE_8KB) 220 #define PM_DEFAULT_MASK PM_8K 221 #elif defined(CONFIG_PAGE_SIZE_16KB) 222 #define PM_DEFAULT_MASK PM_16K 223 #elif defined(CONFIG_PAGE_SIZE_32KB) 224 #define PM_DEFAULT_MASK PM_32K 225 #elif defined(CONFIG_PAGE_SIZE_64KB) 226 #define PM_DEFAULT_MASK PM_64K 227 #else 228 #error Bad page size configuration! 229 #endif 230 231 /* 232 * Default huge tlb size for a given kernel configuration 233 */ 234 #ifdef CONFIG_PAGE_SIZE_4KB 235 #define PM_HUGE_MASK PM_1M 236 #elif defined(CONFIG_PAGE_SIZE_8KB) 237 #define PM_HUGE_MASK PM_4M 238 #elif defined(CONFIG_PAGE_SIZE_16KB) 239 #define PM_HUGE_MASK PM_16M 240 #elif defined(CONFIG_PAGE_SIZE_32KB) 241 #define PM_HUGE_MASK PM_64M 242 #elif defined(CONFIG_PAGE_SIZE_64KB) 243 #define PM_HUGE_MASK PM_256M 244 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 245 #error Bad page size configuration for hugetlbfs! 246 #endif 247 248 /* 249 * Values used for computation of new tlb entries 250 */ 251 #define PL_4K 12 252 #define PL_16K 14 253 #define PL_64K 16 254 #define PL_256K 18 255 #define PL_1M 20 256 #define PL_4M 22 257 #define PL_16M 24 258 #define PL_64M 26 259 #define PL_256M 28 260 261 /* 262 * PageGrain bits 263 */ 264 #define PG_RIE (_ULCAST_(1) << 31) 265 #define PG_XIE (_ULCAST_(1) << 30) 266 #define PG_ELPA (_ULCAST_(1) << 29) 267 #define PG_ESP (_ULCAST_(1) << 28) 268 269 /* 270 * R4x00 interrupt enable / cause bits 271 */ 272 #define IE_SW0 (_ULCAST_(1) << 8) 273 #define IE_SW1 (_ULCAST_(1) << 9) 274 #define IE_IRQ0 (_ULCAST_(1) << 10) 275 #define IE_IRQ1 (_ULCAST_(1) << 11) 276 #define IE_IRQ2 (_ULCAST_(1) << 12) 277 #define IE_IRQ3 (_ULCAST_(1) << 13) 278 #define IE_IRQ4 (_ULCAST_(1) << 14) 279 #define IE_IRQ5 (_ULCAST_(1) << 15) 280 281 /* 282 * R4x00 interrupt cause bits 283 */ 284 #define C_SW0 (_ULCAST_(1) << 8) 285 #define C_SW1 (_ULCAST_(1) << 9) 286 #define C_IRQ0 (_ULCAST_(1) << 10) 287 #define C_IRQ1 (_ULCAST_(1) << 11) 288 #define C_IRQ2 (_ULCAST_(1) << 12) 289 #define C_IRQ3 (_ULCAST_(1) << 13) 290 #define C_IRQ4 (_ULCAST_(1) << 14) 291 #define C_IRQ5 (_ULCAST_(1) << 15) 292 293 /* 294 * Bitfields in the R4xx0 cp0 status register 295 */ 296 #define ST0_IE 0x00000001 297 #define ST0_EXL 0x00000002 298 #define ST0_ERL 0x00000004 299 #define ST0_KSU 0x00000018 300 # define KSU_USER 0x00000010 301 # define KSU_SUPERVISOR 0x00000008 302 # define KSU_KERNEL 0x00000000 303 #define ST0_UX 0x00000020 304 #define ST0_SX 0x00000040 305 #define ST0_KX 0x00000080 306 #define ST0_DE 0x00010000 307 #define ST0_CE 0x00020000 308 309 /* 310 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 311 * cacheops in userspace. This bit exists only on RM7000 and RM9000 312 * processors. 313 */ 314 #define ST0_CO 0x08000000 315 316 /* 317 * Bitfields in the R[23]000 cp0 status register. 318 */ 319 #define ST0_IEC 0x00000001 320 #define ST0_KUC 0x00000002 321 #define ST0_IEP 0x00000004 322 #define ST0_KUP 0x00000008 323 #define ST0_IEO 0x00000010 324 #define ST0_KUO 0x00000020 325 /* bits 6 & 7 are reserved on R[23]000 */ 326 #define ST0_ISC 0x00010000 327 #define ST0_SWC 0x00020000 328 #define ST0_CM 0x00080000 329 330 /* 331 * Bits specific to the R4640/R4650 332 */ 333 #define ST0_UM (_ULCAST_(1) << 4) 334 #define ST0_IL (_ULCAST_(1) << 23) 335 #define ST0_DL (_ULCAST_(1) << 24) 336 337 /* 338 * Enable the MIPS MDMX and DSP ASEs 339 */ 340 #define ST0_MX 0x01000000 341 342 /* 343 * Bitfields in the TX39 family CP0 Configuration Register 3 344 */ 345 #define TX39_CONF_ICS_SHIFT 19 346 #define TX39_CONF_ICS_MASK 0x00380000 347 #define TX39_CONF_ICS_1KB 0x00000000 348 #define TX39_CONF_ICS_2KB 0x00080000 349 #define TX39_CONF_ICS_4KB 0x00100000 350 #define TX39_CONF_ICS_8KB 0x00180000 351 #define TX39_CONF_ICS_16KB 0x00200000 352 353 #define TX39_CONF_DCS_SHIFT 16 354 #define TX39_CONF_DCS_MASK 0x00070000 355 #define TX39_CONF_DCS_1KB 0x00000000 356 #define TX39_CONF_DCS_2KB 0x00010000 357 #define TX39_CONF_DCS_4KB 0x00020000 358 #define TX39_CONF_DCS_8KB 0x00030000 359 #define TX39_CONF_DCS_16KB 0x00040000 360 361 #define TX39_CONF_CWFON 0x00004000 362 #define TX39_CONF_WBON 0x00002000 363 #define TX39_CONF_RF_SHIFT 10 364 #define TX39_CONF_RF_MASK 0x00000c00 365 #define TX39_CONF_DOZE 0x00000200 366 #define TX39_CONF_HALT 0x00000100 367 #define TX39_CONF_LOCK 0x00000080 368 #define TX39_CONF_ICE 0x00000020 369 #define TX39_CONF_DCE 0x00000010 370 #define TX39_CONF_IRSIZE_SHIFT 2 371 #define TX39_CONF_IRSIZE_MASK 0x0000000c 372 #define TX39_CONF_DRSIZE_SHIFT 0 373 #define TX39_CONF_DRSIZE_MASK 0x00000003 374 375 /* 376 * Status register bits available in all MIPS CPUs. 377 */ 378 #define ST0_IM 0x0000ff00 379 #define STATUSB_IP0 8 380 #define STATUSF_IP0 (_ULCAST_(1) << 8) 381 #define STATUSB_IP1 9 382 #define STATUSF_IP1 (_ULCAST_(1) << 9) 383 #define STATUSB_IP2 10 384 #define STATUSF_IP2 (_ULCAST_(1) << 10) 385 #define STATUSB_IP3 11 386 #define STATUSF_IP3 (_ULCAST_(1) << 11) 387 #define STATUSB_IP4 12 388 #define STATUSF_IP4 (_ULCAST_(1) << 12) 389 #define STATUSB_IP5 13 390 #define STATUSF_IP5 (_ULCAST_(1) << 13) 391 #define STATUSB_IP6 14 392 #define STATUSF_IP6 (_ULCAST_(1) << 14) 393 #define STATUSB_IP7 15 394 #define STATUSF_IP7 (_ULCAST_(1) << 15) 395 #define STATUSB_IP8 0 396 #define STATUSF_IP8 (_ULCAST_(1) << 0) 397 #define STATUSB_IP9 1 398 #define STATUSF_IP9 (_ULCAST_(1) << 1) 399 #define STATUSB_IP10 2 400 #define STATUSF_IP10 (_ULCAST_(1) << 2) 401 #define STATUSB_IP11 3 402 #define STATUSF_IP11 (_ULCAST_(1) << 3) 403 #define STATUSB_IP12 4 404 #define STATUSF_IP12 (_ULCAST_(1) << 4) 405 #define STATUSB_IP13 5 406 #define STATUSF_IP13 (_ULCAST_(1) << 5) 407 #define STATUSB_IP14 6 408 #define STATUSF_IP14 (_ULCAST_(1) << 6) 409 #define STATUSB_IP15 7 410 #define STATUSF_IP15 (_ULCAST_(1) << 7) 411 #define ST0_CH 0x00040000 412 #define ST0_NMI 0x00080000 413 #define ST0_SR 0x00100000 414 #define ST0_TS 0x00200000 415 #define ST0_BEV 0x00400000 416 #define ST0_RE 0x02000000 417 #define ST0_FR 0x04000000 418 #define ST0_CU 0xf0000000 419 #define ST0_CU0 0x10000000 420 #define ST0_CU1 0x20000000 421 #define ST0_CU2 0x40000000 422 #define ST0_CU3 0x80000000 423 #define ST0_XX 0x80000000 /* MIPS IV naming */ 424 425 /* 426 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 427 * 428 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 429 */ 430 #define INTCTLB_IPPCI 26 431 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 432 #define INTCTLB_IPTI 29 433 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 434 435 /* 436 * Bitfields and bit numbers in the coprocessor 0 cause register. 437 * 438 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 439 */ 440 #define CAUSEB_EXCCODE 2 441 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 442 #define CAUSEB_IP 8 443 #define CAUSEF_IP (_ULCAST_(255) << 8) 444 #define CAUSEB_IP0 8 445 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 446 #define CAUSEB_IP1 9 447 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 448 #define CAUSEB_IP2 10 449 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 450 #define CAUSEB_IP3 11 451 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 452 #define CAUSEB_IP4 12 453 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 454 #define CAUSEB_IP5 13 455 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 456 #define CAUSEB_IP6 14 457 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 458 #define CAUSEB_IP7 15 459 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 460 #define CAUSEB_IV 23 461 #define CAUSEF_IV (_ULCAST_(1) << 23) 462 #define CAUSEB_PCI 26 463 #define CAUSEF_PCI (_ULCAST_(1) << 26) 464 #define CAUSEB_CE 28 465 #define CAUSEF_CE (_ULCAST_(3) << 28) 466 #define CAUSEB_TI 30 467 #define CAUSEF_TI (_ULCAST_(1) << 30) 468 #define CAUSEB_BD 31 469 #define CAUSEF_BD (_ULCAST_(1) << 31) 470 471 /* 472 * Bits in the coprocessor 0 config register. 473 */ 474 /* Generic bits. */ 475 #define CONF_CM_CACHABLE_NO_WA 0 476 #define CONF_CM_CACHABLE_WA 1 477 #define CONF_CM_UNCACHED 2 478 #define CONF_CM_CACHABLE_NONCOHERENT 3 479 #define CONF_CM_CACHABLE_CE 4 480 #define CONF_CM_CACHABLE_COW 5 481 #define CONF_CM_CACHABLE_CUW 6 482 #define CONF_CM_CACHABLE_ACCELERATED 7 483 #define CONF_CM_CMASK 7 484 #define CONF_BE (_ULCAST_(1) << 15) 485 486 /* Bits common to various processors. */ 487 #define CONF_CU (_ULCAST_(1) << 3) 488 #define CONF_DB (_ULCAST_(1) << 4) 489 #define CONF_IB (_ULCAST_(1) << 5) 490 #define CONF_DC (_ULCAST_(7) << 6) 491 #define CONF_IC (_ULCAST_(7) << 9) 492 #define CONF_EB (_ULCAST_(1) << 13) 493 #define CONF_EM (_ULCAST_(1) << 14) 494 #define CONF_SM (_ULCAST_(1) << 16) 495 #define CONF_SC (_ULCAST_(1) << 17) 496 #define CONF_EW (_ULCAST_(3) << 18) 497 #define CONF_EP (_ULCAST_(15)<< 24) 498 #define CONF_EC (_ULCAST_(7) << 28) 499 #define CONF_CM (_ULCAST_(1) << 31) 500 501 /* Bits specific to the R4xx0. */ 502 #define R4K_CONF_SW (_ULCAST_(1) << 20) 503 #define R4K_CONF_SS (_ULCAST_(1) << 21) 504 #define R4K_CONF_SB (_ULCAST_(3) << 22) 505 506 /* Bits specific to the R5000. */ 507 #define R5K_CONF_SE (_ULCAST_(1) << 12) 508 #define R5K_CONF_SS (_ULCAST_(3) << 20) 509 510 /* Bits specific to the RM7000. */ 511 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 512 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 513 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 514 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 515 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 516 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 517 518 /* Bits specific to the R10000. */ 519 #define R10K_CONF_DN (_ULCAST_(3) << 3) 520 #define R10K_CONF_CT (_ULCAST_(1) << 5) 521 #define R10K_CONF_PE (_ULCAST_(1) << 6) 522 #define R10K_CONF_PM (_ULCAST_(3) << 7) 523 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 524 #define R10K_CONF_SB (_ULCAST_(1) << 13) 525 #define R10K_CONF_SK (_ULCAST_(1) << 14) 526 #define R10K_CONF_SS (_ULCAST_(7) << 16) 527 #define R10K_CONF_SC (_ULCAST_(7) << 19) 528 #define R10K_CONF_DC (_ULCAST_(7) << 26) 529 #define R10K_CONF_IC (_ULCAST_(7) << 29) 530 531 /* Bits specific to the VR41xx. */ 532 #define VR41_CONF_CS (_ULCAST_(1) << 12) 533 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 534 #define VR41_CONF_BP (_ULCAST_(1) << 16) 535 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 536 #define VR41_CONF_AD (_ULCAST_(1) << 23) 537 538 /* Bits specific to the R30xx. */ 539 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 540 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 541 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 542 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 543 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 544 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 545 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 546 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 547 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 548 549 /* Bits specific to the TX49. */ 550 #define TX49_CONF_DC (_ULCAST_(1) << 16) 551 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 552 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 553 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 554 555 /* Bits specific to the MIPS32/64 PRA. */ 556 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 557 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 558 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 559 #define MIPS_CONF_M (_ULCAST_(1) << 31) 560 561 /* 562 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 563 */ 564 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 565 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 566 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 567 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 568 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 569 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 570 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 571 #define MIPS_CONF1_DA_SHF 7 572 #define MIPS_CONF1_DA_SZ 3 573 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 574 #define MIPS_CONF1_DL_SHF 10 575 #define MIPS_CONF1_DL_SZ 3 576 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 577 #define MIPS_CONF1_DS_SHF 13 578 #define MIPS_CONF1_DS_SZ 3 579 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 580 #define MIPS_CONF1_IA_SHF 16 581 #define MIPS_CONF1_IA_SZ 3 582 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 583 #define MIPS_CONF1_IL_SHF 19 584 #define MIPS_CONF1_IL_SZ 3 585 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 586 #define MIPS_CONF1_IS_SHF 22 587 #define MIPS_CONF1_IS_SZ 3 588 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 589 #define MIPS_CONF1_TLBS_SHIFT (25) 590 #define MIPS_CONF1_TLBS_SIZE (6) 591 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) 592 593 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 594 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 595 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 596 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 597 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 598 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 599 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 600 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 601 602 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 603 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 604 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 605 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) 606 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 607 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 608 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 609 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 610 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) 611 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 612 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 613 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 614 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 615 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 616 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 617 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 618 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) 619 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) 620 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) 621 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 622 #define MIPS_CONF3_PW (_ULCAST_(1) << 24) 623 #define MIPS_CONF3_SC (_ULCAST_(1) << 25) 624 #define MIPS_CONF3_BI (_ULCAST_(1) << 26) 625 #define MIPS_CONF3_BP (_ULCAST_(1) << 27) 626 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) 627 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) 628 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) 629 630 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 631 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 632 #define MIPS_CONF4_FTLBSETS_SHIFT (0) 633 #define MIPS_CONF4_FTLBSETS_SHIFT (0) 634 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 635 #define MIPS_CONF4_FTLBWAYS_SHIFT (4) 636 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 637 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) 638 /* bits 10:8 in FTLB-only configurations */ 639 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 640 /* bits 12:8 in VTLB-FTLB only configurations */ 641 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 642 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 643 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 644 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) 645 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) 646 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) 647 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) 648 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) 649 #define MIPS_CONF4_AE (_ULCAST_(1) << 28) 650 #define MIPS_CONF4_IE (_ULCAST_(3) << 29) 651 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) 652 653 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 654 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 655 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 656 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 657 #define MIPS_CONF5_CV (_ULCAST_(1) << 29) 658 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 659 660 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 661 /* proAptiv FTLB on/off bit */ 662 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) 663 664 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 665 666 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 667 668 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 669 #define MIPS_CONF7_AR (_ULCAST_(1) << 16) 670 671 /* EntryHI bit definition */ 672 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 673 674 /* CMGCRBase bit definitions */ 675 #define MIPS_CMGCRB_BASE 11 676 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) 677 678 /* 679 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 680 */ 681 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 682 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 683 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 684 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 685 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 686 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 687 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 688 689 /* 690 * Bits in the MIPS32 Memory Segmentation registers. 691 */ 692 #define MIPS_SEGCFG_PA_SHIFT 9 693 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) 694 #define MIPS_SEGCFG_AM_SHIFT 4 695 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) 696 #define MIPS_SEGCFG_EU_SHIFT 3 697 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) 698 #define MIPS_SEGCFG_C_SHIFT 0 699 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) 700 701 #define MIPS_SEGCFG_UUSK _ULCAST_(7) 702 #define MIPS_SEGCFG_USK _ULCAST_(5) 703 #define MIPS_SEGCFG_MUSUK _ULCAST_(4) 704 #define MIPS_SEGCFG_MUSK _ULCAST_(3) 705 #define MIPS_SEGCFG_MSK _ULCAST_(2) 706 #define MIPS_SEGCFG_MK _ULCAST_(1) 707 #define MIPS_SEGCFG_UK _ULCAST_(0) 708 709 #ifndef __ASSEMBLY__ 710 711 /* 712 * Macros for handling the ISA mode bit for MIPS16 and microMIPS. 713 */ 714 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ 715 defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 716 #define get_isa16_mode(x) ((x) & 0x1) 717 #define msk_isa16_mode(x) ((x) & ~0x1) 718 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) 719 #else 720 #define get_isa16_mode(x) 0 721 #define msk_isa16_mode(x) (x) 722 #define set_isa16_mode(x) do { } while(0) 723 #endif 724 725 /* 726 * microMIPS instructions can be 16-bit or 32-bit in length. This 727 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. 728 */ 729 static inline int mm_insn_16bit(u16 insn) 730 { 731 u16 opcode = (insn >> 10) & 0x7; 732 733 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 734 } 735 736 /* 737 * TLB Invalidate Flush 738 */ 739 static inline void tlbinvf(void) 740 { 741 __asm__ __volatile__( 742 ".set push\n\t" 743 ".set noreorder\n\t" 744 ".word 0x42000004\n\t" /* tlbinvf */ 745 ".set pop"); 746 } 747 748 749 /* 750 * Functions to access the R10000 performance counters. These are basically 751 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 752 * performance counter number encoded into bits 1 ... 5 of the instruction. 753 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 754 * disassembler these will look like an access to sel 0 or 1. 755 */ 756 #define read_r10k_perf_cntr(counter) \ 757 ({ \ 758 unsigned int __res; \ 759 __asm__ __volatile__( \ 760 "mfpc\t%0, %1" \ 761 : "=r" (__res) \ 762 : "i" (counter)); \ 763 \ 764 __res; \ 765 }) 766 767 #define write_r10k_perf_cntr(counter,val) \ 768 do { \ 769 __asm__ __volatile__( \ 770 "mtpc\t%0, %1" \ 771 : \ 772 : "r" (val), "i" (counter)); \ 773 } while (0) 774 775 #define read_r10k_perf_event(counter) \ 776 ({ \ 777 unsigned int __res; \ 778 __asm__ __volatile__( \ 779 "mfps\t%0, %1" \ 780 : "=r" (__res) \ 781 : "i" (counter)); \ 782 \ 783 __res; \ 784 }) 785 786 #define write_r10k_perf_cntl(counter,val) \ 787 do { \ 788 __asm__ __volatile__( \ 789 "mtps\t%0, %1" \ 790 : \ 791 : "r" (val), "i" (counter)); \ 792 } while (0) 793 794 795 /* 796 * Macros to access the system control coprocessor 797 */ 798 799 #define __read_32bit_c0_register(source, sel) \ 800 ({ int __res; \ 801 if (sel == 0) \ 802 __asm__ __volatile__( \ 803 "mfc0\t%0, " #source "\n\t" \ 804 : "=r" (__res)); \ 805 else \ 806 __asm__ __volatile__( \ 807 ".set\tmips32\n\t" \ 808 "mfc0\t%0, " #source ", " #sel "\n\t" \ 809 ".set\tmips0\n\t" \ 810 : "=r" (__res)); \ 811 __res; \ 812 }) 813 814 #define __read_64bit_c0_register(source, sel) \ 815 ({ unsigned long long __res; \ 816 if (sizeof(unsigned long) == 4) \ 817 __res = __read_64bit_c0_split(source, sel); \ 818 else if (sel == 0) \ 819 __asm__ __volatile__( \ 820 ".set\tmips3\n\t" \ 821 "dmfc0\t%0, " #source "\n\t" \ 822 ".set\tmips0" \ 823 : "=r" (__res)); \ 824 else \ 825 __asm__ __volatile__( \ 826 ".set\tmips64\n\t" \ 827 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 828 ".set\tmips0" \ 829 : "=r" (__res)); \ 830 __res; \ 831 }) 832 833 #define __write_32bit_c0_register(register, sel, value) \ 834 do { \ 835 if (sel == 0) \ 836 __asm__ __volatile__( \ 837 "mtc0\t%z0, " #register "\n\t" \ 838 : : "Jr" ((unsigned int)(value))); \ 839 else \ 840 __asm__ __volatile__( \ 841 ".set\tmips32\n\t" \ 842 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 843 ".set\tmips0" \ 844 : : "Jr" ((unsigned int)(value))); \ 845 } while (0) 846 847 #define __write_64bit_c0_register(register, sel, value) \ 848 do { \ 849 if (sizeof(unsigned long) == 4) \ 850 __write_64bit_c0_split(register, sel, value); \ 851 else if (sel == 0) \ 852 __asm__ __volatile__( \ 853 ".set\tmips3\n\t" \ 854 "dmtc0\t%z0, " #register "\n\t" \ 855 ".set\tmips0" \ 856 : : "Jr" (value)); \ 857 else \ 858 __asm__ __volatile__( \ 859 ".set\tmips64\n\t" \ 860 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 861 ".set\tmips0" \ 862 : : "Jr" (value)); \ 863 } while (0) 864 865 #define __read_ulong_c0_register(reg, sel) \ 866 ((sizeof(unsigned long) == 4) ? \ 867 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 868 (unsigned long) __read_64bit_c0_register(reg, sel)) 869 870 #define __write_ulong_c0_register(reg, sel, val) \ 871 do { \ 872 if (sizeof(unsigned long) == 4) \ 873 __write_32bit_c0_register(reg, sel, val); \ 874 else \ 875 __write_64bit_c0_register(reg, sel, val); \ 876 } while (0) 877 878 /* 879 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 880 */ 881 #define __read_32bit_c0_ctrl_register(source) \ 882 ({ int __res; \ 883 __asm__ __volatile__( \ 884 "cfc0\t%0, " #source "\n\t" \ 885 : "=r" (__res)); \ 886 __res; \ 887 }) 888 889 #define __write_32bit_c0_ctrl_register(register, value) \ 890 do { \ 891 __asm__ __volatile__( \ 892 "ctc0\t%z0, " #register "\n\t" \ 893 : : "Jr" ((unsigned int)(value))); \ 894 } while (0) 895 896 /* 897 * These versions are only needed for systems with more than 38 bits of 898 * physical address space running the 32-bit kernel. That's none atm :-) 899 */ 900 #define __read_64bit_c0_split(source, sel) \ 901 ({ \ 902 unsigned long long __val; \ 903 unsigned long __flags; \ 904 \ 905 local_irq_save(__flags); \ 906 if (sel == 0) \ 907 __asm__ __volatile__( \ 908 ".set\tmips64\n\t" \ 909 "dmfc0\t%M0, " #source "\n\t" \ 910 "dsll\t%L0, %M0, 32\n\t" \ 911 "dsra\t%M0, %M0, 32\n\t" \ 912 "dsra\t%L0, %L0, 32\n\t" \ 913 ".set\tmips0" \ 914 : "=r" (__val)); \ 915 else \ 916 __asm__ __volatile__( \ 917 ".set\tmips64\n\t" \ 918 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 919 "dsll\t%L0, %M0, 32\n\t" \ 920 "dsra\t%M0, %M0, 32\n\t" \ 921 "dsra\t%L0, %L0, 32\n\t" \ 922 ".set\tmips0" \ 923 : "=r" (__val)); \ 924 local_irq_restore(__flags); \ 925 \ 926 __val; \ 927 }) 928 929 #define __write_64bit_c0_split(source, sel, val) \ 930 do { \ 931 unsigned long __flags; \ 932 \ 933 local_irq_save(__flags); \ 934 if (sel == 0) \ 935 __asm__ __volatile__( \ 936 ".set\tmips64\n\t" \ 937 "dsll\t%L0, %L0, 32\n\t" \ 938 "dsrl\t%L0, %L0, 32\n\t" \ 939 "dsll\t%M0, %M0, 32\n\t" \ 940 "or\t%L0, %L0, %M0\n\t" \ 941 "dmtc0\t%L0, " #source "\n\t" \ 942 ".set\tmips0" \ 943 : : "r" (val)); \ 944 else \ 945 __asm__ __volatile__( \ 946 ".set\tmips64\n\t" \ 947 "dsll\t%L0, %L0, 32\n\t" \ 948 "dsrl\t%L0, %L0, 32\n\t" \ 949 "dsll\t%M0, %M0, 32\n\t" \ 950 "or\t%L0, %L0, %M0\n\t" \ 951 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 952 ".set\tmips0" \ 953 : : "r" (val)); \ 954 local_irq_restore(__flags); \ 955 } while (0) 956 957 #define read_c0_index() __read_32bit_c0_register($0, 0) 958 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 959 960 #define read_c0_random() __read_32bit_c0_register($1, 0) 961 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 962 963 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 964 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 965 966 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 967 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 968 969 #define read_c0_conf() __read_32bit_c0_register($3, 0) 970 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 971 972 #define read_c0_context() __read_ulong_c0_register($4, 0) 973 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 974 975 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 976 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 977 978 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 979 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 980 981 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 982 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 983 984 #define read_c0_wired() __read_32bit_c0_register($6, 0) 985 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 986 987 #define read_c0_info() __read_32bit_c0_register($7, 0) 988 989 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 990 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 991 992 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 993 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 994 995 #define read_c0_count() __read_32bit_c0_register($9, 0) 996 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 997 998 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 999 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 1000 1001 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 1002 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 1003 1004 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 1005 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 1006 1007 #define read_c0_compare() __read_32bit_c0_register($11, 0) 1008 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 1009 1010 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 1011 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 1012 1013 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 1014 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 1015 1016 #define read_c0_status() __read_32bit_c0_register($12, 0) 1017 1018 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 1019 1020 #define read_c0_cause() __read_32bit_c0_register($13, 0) 1021 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 1022 1023 #define read_c0_epc() __read_ulong_c0_register($14, 0) 1024 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 1025 1026 #define read_c0_prid() __read_32bit_c0_register($15, 0) 1027 1028 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) 1029 1030 #define read_c0_config() __read_32bit_c0_register($16, 0) 1031 #define read_c0_config1() __read_32bit_c0_register($16, 1) 1032 #define read_c0_config2() __read_32bit_c0_register($16, 2) 1033 #define read_c0_config3() __read_32bit_c0_register($16, 3) 1034 #define read_c0_config4() __read_32bit_c0_register($16, 4) 1035 #define read_c0_config5() __read_32bit_c0_register($16, 5) 1036 #define read_c0_config6() __read_32bit_c0_register($16, 6) 1037 #define read_c0_config7() __read_32bit_c0_register($16, 7) 1038 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 1039 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 1040 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 1041 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 1042 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 1043 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 1044 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1045 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1046 1047 /* 1048 * The WatchLo register. There may be up to 8 of them. 1049 */ 1050 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 1051 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 1052 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 1053 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 1054 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 1055 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 1056 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 1057 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 1058 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 1059 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 1060 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 1061 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 1062 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 1063 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 1064 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 1065 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 1066 1067 /* 1068 * The WatchHi register. There may be up to 8 of them. 1069 */ 1070 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 1071 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 1072 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 1073 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 1074 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 1075 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 1076 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 1077 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 1078 1079 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 1080 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 1081 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 1082 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 1083 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 1084 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 1085 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 1086 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 1087 1088 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 1089 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 1090 1091 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 1092 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 1093 1094 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 1095 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 1096 1097 #define read_c0_diag() __read_32bit_c0_register($22, 0) 1098 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 1099 1100 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 1101 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 1102 1103 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 1104 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 1105 1106 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 1107 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1108 1109 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 1110 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1111 1112 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 1113 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1114 1115 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1116 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1117 1118 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1119 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1120 1121 /* 1122 * MIPS32 / MIPS64 performance counters 1123 */ 1124 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1125 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1126 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1127 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1128 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1129 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1130 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1131 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1132 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1133 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1134 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1135 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1136 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1137 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1138 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1139 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1140 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1141 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1142 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1143 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1144 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1145 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1146 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1147 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1148 1149 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1150 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1151 1152 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1153 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1154 1155 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1156 1157 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1158 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1159 1160 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1161 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1162 1163 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1164 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1165 1166 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1167 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1168 1169 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1170 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1171 1172 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1173 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1174 1175 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1176 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1177 1178 /* MIPSR2 */ 1179 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1180 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1181 1182 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1183 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1184 1185 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1186 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1187 1188 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1189 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1190 1191 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1192 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1193 1194 /* MIPSR3 */ 1195 #define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1196 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1197 1198 #define read_c0_segctl1() __read_32bit_c0_register($5, 3) 1199 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) 1200 1201 #define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1202 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1203 1204 /* Cavium OCTEON (cnMIPS) */ 1205 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1206 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1207 1208 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1209 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1210 1211 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1212 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1213 /* 1214 * The cacheerr registers are not standardized. On OCTEON, they are 1215 * 64 bits wide. 1216 */ 1217 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1218 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1219 1220 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1221 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1222 1223 /* BMIPS3300 */ 1224 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1225 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1226 1227 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1228 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1229 1230 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1231 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1232 1233 /* BMIPS43xx */ 1234 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1235 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1236 1237 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1238 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1239 1240 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1241 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1242 1243 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1244 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1245 1246 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1247 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1248 1249 /* BMIPS5000 */ 1250 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1251 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1252 1253 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1254 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1255 1256 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1257 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1258 1259 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1260 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1261 1262 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1263 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1264 1265 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1266 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1267 1268 /* 1269 * Macros to access the floating point coprocessor control registers 1270 */ 1271 #define read_32bit_cp1_register(source) \ 1272 ({ \ 1273 int __res; \ 1274 \ 1275 __asm__ __volatile__( \ 1276 " .set push \n" \ 1277 " .set reorder \n" \ 1278 " # gas fails to assemble cfc1 for some archs, \n" \ 1279 " # like Octeon. \n" \ 1280 " .set mips1 \n" \ 1281 " cfc1 %0,"STR(source)" \n" \ 1282 " .set pop \n" \ 1283 : "=r" (__res)); \ 1284 __res; \ 1285 }) 1286 1287 #ifdef HAVE_AS_DSP 1288 #define rddsp(mask) \ 1289 ({ \ 1290 unsigned int __dspctl; \ 1291 \ 1292 __asm__ __volatile__( \ 1293 " .set push \n" \ 1294 " .set dsp \n" \ 1295 " rddsp %0, %x1 \n" \ 1296 " .set pop \n" \ 1297 : "=r" (__dspctl) \ 1298 : "i" (mask)); \ 1299 __dspctl; \ 1300 }) 1301 1302 #define wrdsp(val, mask) \ 1303 do { \ 1304 __asm__ __volatile__( \ 1305 " .set push \n" \ 1306 " .set dsp \n" \ 1307 " wrdsp %0, %x1 \n" \ 1308 " .set pop \n" \ 1309 : \ 1310 : "r" (val), "i" (mask)); \ 1311 } while (0) 1312 1313 #define mflo0() \ 1314 ({ \ 1315 long mflo0; \ 1316 __asm__( \ 1317 " .set push \n" \ 1318 " .set dsp \n" \ 1319 " mflo %0, $ac0 \n" \ 1320 " .set pop \n" \ 1321 : "=r" (mflo0)); \ 1322 mflo0; \ 1323 }) 1324 1325 #define mflo1() \ 1326 ({ \ 1327 long mflo1; \ 1328 __asm__( \ 1329 " .set push \n" \ 1330 " .set dsp \n" \ 1331 " mflo %0, $ac1 \n" \ 1332 " .set pop \n" \ 1333 : "=r" (mflo1)); \ 1334 mflo1; \ 1335 }) 1336 1337 #define mflo2() \ 1338 ({ \ 1339 long mflo2; \ 1340 __asm__( \ 1341 " .set push \n" \ 1342 " .set dsp \n" \ 1343 " mflo %0, $ac2 \n" \ 1344 " .set pop \n" \ 1345 : "=r" (mflo2)); \ 1346 mflo2; \ 1347 }) 1348 1349 #define mflo3() \ 1350 ({ \ 1351 long mflo3; \ 1352 __asm__( \ 1353 " .set push \n" \ 1354 " .set dsp \n" \ 1355 " mflo %0, $ac3 \n" \ 1356 " .set pop \n" \ 1357 : "=r" (mflo3)); \ 1358 mflo3; \ 1359 }) 1360 1361 #define mfhi0() \ 1362 ({ \ 1363 long mfhi0; \ 1364 __asm__( \ 1365 " .set push \n" \ 1366 " .set dsp \n" \ 1367 " mfhi %0, $ac0 \n" \ 1368 " .set pop \n" \ 1369 : "=r" (mfhi0)); \ 1370 mfhi0; \ 1371 }) 1372 1373 #define mfhi1() \ 1374 ({ \ 1375 long mfhi1; \ 1376 __asm__( \ 1377 " .set push \n" \ 1378 " .set dsp \n" \ 1379 " mfhi %0, $ac1 \n" \ 1380 " .set pop \n" \ 1381 : "=r" (mfhi1)); \ 1382 mfhi1; \ 1383 }) 1384 1385 #define mfhi2() \ 1386 ({ \ 1387 long mfhi2; \ 1388 __asm__( \ 1389 " .set push \n" \ 1390 " .set dsp \n" \ 1391 " mfhi %0, $ac2 \n" \ 1392 " .set pop \n" \ 1393 : "=r" (mfhi2)); \ 1394 mfhi2; \ 1395 }) 1396 1397 #define mfhi3() \ 1398 ({ \ 1399 long mfhi3; \ 1400 __asm__( \ 1401 " .set push \n" \ 1402 " .set dsp \n" \ 1403 " mfhi %0, $ac3 \n" \ 1404 " .set pop \n" \ 1405 : "=r" (mfhi3)); \ 1406 mfhi3; \ 1407 }) 1408 1409 1410 #define mtlo0(x) \ 1411 ({ \ 1412 __asm__( \ 1413 " .set push \n" \ 1414 " .set dsp \n" \ 1415 " mtlo %0, $ac0 \n" \ 1416 " .set pop \n" \ 1417 : \ 1418 : "r" (x)); \ 1419 }) 1420 1421 #define mtlo1(x) \ 1422 ({ \ 1423 __asm__( \ 1424 " .set push \n" \ 1425 " .set dsp \n" \ 1426 " mtlo %0, $ac1 \n" \ 1427 " .set pop \n" \ 1428 : \ 1429 : "r" (x)); \ 1430 }) 1431 1432 #define mtlo2(x) \ 1433 ({ \ 1434 __asm__( \ 1435 " .set push \n" \ 1436 " .set dsp \n" \ 1437 " mtlo %0, $ac2 \n" \ 1438 " .set pop \n" \ 1439 : \ 1440 : "r" (x)); \ 1441 }) 1442 1443 #define mtlo3(x) \ 1444 ({ \ 1445 __asm__( \ 1446 " .set push \n" \ 1447 " .set dsp \n" \ 1448 " mtlo %0, $ac3 \n" \ 1449 " .set pop \n" \ 1450 : \ 1451 : "r" (x)); \ 1452 }) 1453 1454 #define mthi0(x) \ 1455 ({ \ 1456 __asm__( \ 1457 " .set push \n" \ 1458 " .set dsp \n" \ 1459 " mthi %0, $ac0 \n" \ 1460 " .set pop \n" \ 1461 : \ 1462 : "r" (x)); \ 1463 }) 1464 1465 #define mthi1(x) \ 1466 ({ \ 1467 __asm__( \ 1468 " .set push \n" \ 1469 " .set dsp \n" \ 1470 " mthi %0, $ac1 \n" \ 1471 " .set pop \n" \ 1472 : \ 1473 : "r" (x)); \ 1474 }) 1475 1476 #define mthi2(x) \ 1477 ({ \ 1478 __asm__( \ 1479 " .set push \n" \ 1480 " .set dsp \n" \ 1481 " mthi %0, $ac2 \n" \ 1482 " .set pop \n" \ 1483 : \ 1484 : "r" (x)); \ 1485 }) 1486 1487 #define mthi3(x) \ 1488 ({ \ 1489 __asm__( \ 1490 " .set push \n" \ 1491 " .set dsp \n" \ 1492 " mthi %0, $ac3 \n" \ 1493 " .set pop \n" \ 1494 : \ 1495 : "r" (x)); \ 1496 }) 1497 1498 #else 1499 1500 #ifdef CONFIG_CPU_MICROMIPS 1501 #define rddsp(mask) \ 1502 ({ \ 1503 unsigned int __res; \ 1504 \ 1505 __asm__ __volatile__( \ 1506 " .set push \n" \ 1507 " .set noat \n" \ 1508 " # rddsp $1, %x1 \n" \ 1509 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1510 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1511 " move %0, $1 \n" \ 1512 " .set pop \n" \ 1513 : "=r" (__res) \ 1514 : "i" (mask)); \ 1515 __res; \ 1516 }) 1517 1518 #define wrdsp(val, mask) \ 1519 do { \ 1520 __asm__ __volatile__( \ 1521 " .set push \n" \ 1522 " .set noat \n" \ 1523 " move $1, %0 \n" \ 1524 " # wrdsp $1, %x1 \n" \ 1525 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1526 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1527 " .set pop \n" \ 1528 : \ 1529 : "r" (val), "i" (mask)); \ 1530 } while (0) 1531 1532 #define _umips_dsp_mfxxx(ins) \ 1533 ({ \ 1534 unsigned long __treg; \ 1535 \ 1536 __asm__ __volatile__( \ 1537 " .set push \n" \ 1538 " .set noat \n" \ 1539 " .hword 0x0001 \n" \ 1540 " .hword %x1 \n" \ 1541 " move %0, $1 \n" \ 1542 " .set pop \n" \ 1543 : "=r" (__treg) \ 1544 : "i" (ins)); \ 1545 __treg; \ 1546 }) 1547 1548 #define _umips_dsp_mtxxx(val, ins) \ 1549 do { \ 1550 __asm__ __volatile__( \ 1551 " .set push \n" \ 1552 " .set noat \n" \ 1553 " move $1, %0 \n" \ 1554 " .hword 0x0001 \n" \ 1555 " .hword %x1 \n" \ 1556 " .set pop \n" \ 1557 : \ 1558 : "r" (val), "i" (ins)); \ 1559 } while (0) 1560 1561 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1562 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1563 1564 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1565 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1566 1567 #define mflo0() _umips_dsp_mflo(0) 1568 #define mflo1() _umips_dsp_mflo(1) 1569 #define mflo2() _umips_dsp_mflo(2) 1570 #define mflo3() _umips_dsp_mflo(3) 1571 1572 #define mfhi0() _umips_dsp_mfhi(0) 1573 #define mfhi1() _umips_dsp_mfhi(1) 1574 #define mfhi2() _umips_dsp_mfhi(2) 1575 #define mfhi3() _umips_dsp_mfhi(3) 1576 1577 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1578 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1579 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1580 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1581 1582 #define mthi0(x) _umips_dsp_mthi(x, 0) 1583 #define mthi1(x) _umips_dsp_mthi(x, 1) 1584 #define mthi2(x) _umips_dsp_mthi(x, 2) 1585 #define mthi3(x) _umips_dsp_mthi(x, 3) 1586 1587 #else /* !CONFIG_CPU_MICROMIPS */ 1588 #define rddsp(mask) \ 1589 ({ \ 1590 unsigned int __res; \ 1591 \ 1592 __asm__ __volatile__( \ 1593 " .set push \n" \ 1594 " .set noat \n" \ 1595 " # rddsp $1, %x1 \n" \ 1596 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1597 " move %0, $1 \n" \ 1598 " .set pop \n" \ 1599 : "=r" (__res) \ 1600 : "i" (mask)); \ 1601 __res; \ 1602 }) 1603 1604 #define wrdsp(val, mask) \ 1605 do { \ 1606 __asm__ __volatile__( \ 1607 " .set push \n" \ 1608 " .set noat \n" \ 1609 " move $1, %0 \n" \ 1610 " # wrdsp $1, %x1 \n" \ 1611 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1612 " .set pop \n" \ 1613 : \ 1614 : "r" (val), "i" (mask)); \ 1615 } while (0) 1616 1617 #define _dsp_mfxxx(ins) \ 1618 ({ \ 1619 unsigned long __treg; \ 1620 \ 1621 __asm__ __volatile__( \ 1622 " .set push \n" \ 1623 " .set noat \n" \ 1624 " .word (0x00000810 | %1) \n" \ 1625 " move %0, $1 \n" \ 1626 " .set pop \n" \ 1627 : "=r" (__treg) \ 1628 : "i" (ins)); \ 1629 __treg; \ 1630 }) 1631 1632 #define _dsp_mtxxx(val, ins) \ 1633 do { \ 1634 __asm__ __volatile__( \ 1635 " .set push \n" \ 1636 " .set noat \n" \ 1637 " move $1, %0 \n" \ 1638 " .word (0x00200011 | %1) \n" \ 1639 " .set pop \n" \ 1640 : \ 1641 : "r" (val), "i" (ins)); \ 1642 } while (0) 1643 1644 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1645 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1646 1647 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1648 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1649 1650 #define mflo0() _dsp_mflo(0) 1651 #define mflo1() _dsp_mflo(1) 1652 #define mflo2() _dsp_mflo(2) 1653 #define mflo3() _dsp_mflo(3) 1654 1655 #define mfhi0() _dsp_mfhi(0) 1656 #define mfhi1() _dsp_mfhi(1) 1657 #define mfhi2() _dsp_mfhi(2) 1658 #define mfhi3() _dsp_mfhi(3) 1659 1660 #define mtlo0(x) _dsp_mtlo(x, 0) 1661 #define mtlo1(x) _dsp_mtlo(x, 1) 1662 #define mtlo2(x) _dsp_mtlo(x, 2) 1663 #define mtlo3(x) _dsp_mtlo(x, 3) 1664 1665 #define mthi0(x) _dsp_mthi(x, 0) 1666 #define mthi1(x) _dsp_mthi(x, 1) 1667 #define mthi2(x) _dsp_mthi(x, 2) 1668 #define mthi3(x) _dsp_mthi(x, 3) 1669 1670 #endif /* CONFIG_CPU_MICROMIPS */ 1671 #endif 1672 1673 /* 1674 * TLB operations. 1675 * 1676 * It is responsibility of the caller to take care of any TLB hazards. 1677 */ 1678 static inline void tlb_probe(void) 1679 { 1680 __asm__ __volatile__( 1681 ".set noreorder\n\t" 1682 "tlbp\n\t" 1683 ".set reorder"); 1684 } 1685 1686 static inline void tlb_read(void) 1687 { 1688 #if MIPS34K_MISSED_ITLB_WAR 1689 int res = 0; 1690 1691 __asm__ __volatile__( 1692 " .set push \n" 1693 " .set noreorder \n" 1694 " .set noat \n" 1695 " .set mips32r2 \n" 1696 " .word 0x41610001 # dvpe $1 \n" 1697 " move %0, $1 \n" 1698 " ehb \n" 1699 " .set pop \n" 1700 : "=r" (res)); 1701 1702 instruction_hazard(); 1703 #endif 1704 1705 __asm__ __volatile__( 1706 ".set noreorder\n\t" 1707 "tlbr\n\t" 1708 ".set reorder"); 1709 1710 #if MIPS34K_MISSED_ITLB_WAR 1711 if ((res & _ULCAST_(1))) 1712 __asm__ __volatile__( 1713 " .set push \n" 1714 " .set noreorder \n" 1715 " .set noat \n" 1716 " .set mips32r2 \n" 1717 " .word 0x41600021 # evpe \n" 1718 " ehb \n" 1719 " .set pop \n"); 1720 #endif 1721 } 1722 1723 static inline void tlb_write_indexed(void) 1724 { 1725 __asm__ __volatile__( 1726 ".set noreorder\n\t" 1727 "tlbwi\n\t" 1728 ".set reorder"); 1729 } 1730 1731 static inline void tlb_write_random(void) 1732 { 1733 __asm__ __volatile__( 1734 ".set noreorder\n\t" 1735 "tlbwr\n\t" 1736 ".set reorder"); 1737 } 1738 1739 /* 1740 * Manipulate bits in a c0 register. 1741 */ 1742 #define __BUILD_SET_C0(name) \ 1743 static inline unsigned int \ 1744 set_c0_##name(unsigned int set) \ 1745 { \ 1746 unsigned int res, new; \ 1747 \ 1748 res = read_c0_##name(); \ 1749 new = res | set; \ 1750 write_c0_##name(new); \ 1751 \ 1752 return res; \ 1753 } \ 1754 \ 1755 static inline unsigned int \ 1756 clear_c0_##name(unsigned int clear) \ 1757 { \ 1758 unsigned int res, new; \ 1759 \ 1760 res = read_c0_##name(); \ 1761 new = res & ~clear; \ 1762 write_c0_##name(new); \ 1763 \ 1764 return res; \ 1765 } \ 1766 \ 1767 static inline unsigned int \ 1768 change_c0_##name(unsigned int change, unsigned int val) \ 1769 { \ 1770 unsigned int res, new; \ 1771 \ 1772 res = read_c0_##name(); \ 1773 new = res & ~change; \ 1774 new |= (val & change); \ 1775 write_c0_##name(new); \ 1776 \ 1777 return res; \ 1778 } 1779 1780 __BUILD_SET_C0(status) 1781 __BUILD_SET_C0(cause) 1782 __BUILD_SET_C0(config) 1783 __BUILD_SET_C0(config5) 1784 __BUILD_SET_C0(intcontrol) 1785 __BUILD_SET_C0(intctl) 1786 __BUILD_SET_C0(srsmap) 1787 __BUILD_SET_C0(brcm_config_0) 1788 __BUILD_SET_C0(brcm_bus_pll) 1789 __BUILD_SET_C0(brcm_reset) 1790 __BUILD_SET_C0(brcm_cmt_intr) 1791 __BUILD_SET_C0(brcm_cmt_ctrl) 1792 __BUILD_SET_C0(brcm_config) 1793 __BUILD_SET_C0(brcm_mode) 1794 1795 /* 1796 * Return low 10 bits of ebase. 1797 * Note that under KVM (MIPSVZ) this returns vcpu id. 1798 */ 1799 static inline unsigned int get_ebase_cpunum(void) 1800 { 1801 return read_c0_ebase() & 0x3ff; 1802 } 1803 1804 #endif /* !__ASSEMBLY__ */ 1805 1806 #endif /* _ASM_MIPSREGS_H */ 1807