1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <asm/hazards.h> 18 #include <asm/war.h> 19 20 /* 21 * The following macros are especially useful for __asm__ 22 * inline assembler. 23 */ 24 #ifndef __STR 25 #define __STR(x) #x 26 #endif 27 #ifndef STR 28 #define STR(x) __STR(x) 29 #endif 30 31 /* 32 * Configure language 33 */ 34 #ifdef __ASSEMBLY__ 35 #define _ULCAST_ 36 #else 37 #define _ULCAST_ (unsigned long) 38 #endif 39 40 /* 41 * Coprocessor 0 register names 42 */ 43 #define CP0_INDEX $0 44 #define CP0_RANDOM $1 45 #define CP0_ENTRYLO0 $2 46 #define CP0_ENTRYLO1 $3 47 #define CP0_CONF $3 48 #define CP0_CONTEXT $4 49 #define CP0_PAGEMASK $5 50 #define CP0_WIRED $6 51 #define CP0_INFO $7 52 #define CP0_BADVADDR $8 53 #define CP0_COUNT $9 54 #define CP0_ENTRYHI $10 55 #define CP0_COMPARE $11 56 #define CP0_STATUS $12 57 #define CP0_CAUSE $13 58 #define CP0_EPC $14 59 #define CP0_PRID $15 60 #define CP0_CONFIG $16 61 #define CP0_LLADDR $17 62 #define CP0_WATCHLO $18 63 #define CP0_WATCHHI $19 64 #define CP0_XCONTEXT $20 65 #define CP0_FRAMEMASK $21 66 #define CP0_DIAGNOSTIC $22 67 #define CP0_DEBUG $23 68 #define CP0_DEPC $24 69 #define CP0_PERFORMANCE $25 70 #define CP0_ECC $26 71 #define CP0_CACHEERR $27 72 #define CP0_TAGLO $28 73 #define CP0_TAGHI $29 74 #define CP0_ERROREPC $30 75 #define CP0_DESAVE $31 76 77 /* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83 #define CP0_IBASE $0 84 #define CP0_IBOUND $1 85 #define CP0_DBASE $2 86 #define CP0_DBOUND $3 87 #define CP0_CALG $17 88 #define CP0_IWATCH $18 89 #define CP0_DWATCH $19 90 91 /* 92 * Coprocessor 0 Set 1 register names 93 */ 94 #define CP0_S1_DERRADDR0 $26 95 #define CP0_S1_DERRADDR1 $27 96 #define CP0_S1_INTCONTROL $20 97 98 /* 99 * Coprocessor 0 Set 2 register names 100 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103 /* 104 * Coprocessor 0 Set 3 register names 105 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108 /* 109 * TX39 Series 110 */ 111 #define CP0_TX39_CACHE $7 112 113 /* 114 * Coprocessor 1 (FPU) register names 115 */ 116 #define CP1_REVISION $0 117 #define CP1_STATUS $31 118 119 /* 120 * FPU Status Register Values 121 */ 122 /* 123 * Status Register Values 124 */ 125 126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 136 137 /* 138 * Bits 18 - 20 of the FPU Status Register will be read as 0, 139 * and should be written as zero. 140 */ 141 #define FPU_CSR_RSVD 0x001c0000 142 143 /* 144 * X the exception cause indicator 145 * E the exception enable 146 * S the sticky/flag bit 147 */ 148 #define FPU_CSR_ALL_X 0x0003f000 149 #define FPU_CSR_UNI_X 0x00020000 150 #define FPU_CSR_INV_X 0x00010000 151 #define FPU_CSR_DIV_X 0x00008000 152 #define FPU_CSR_OVF_X 0x00004000 153 #define FPU_CSR_UDF_X 0x00002000 154 #define FPU_CSR_INE_X 0x00001000 155 156 #define FPU_CSR_ALL_E 0x00000f80 157 #define FPU_CSR_INV_E 0x00000800 158 #define FPU_CSR_DIV_E 0x00000400 159 #define FPU_CSR_OVF_E 0x00000200 160 #define FPU_CSR_UDF_E 0x00000100 161 #define FPU_CSR_INE_E 0x00000080 162 163 #define FPU_CSR_ALL_S 0x0000007c 164 #define FPU_CSR_INV_S 0x00000040 165 #define FPU_CSR_DIV_S 0x00000020 166 #define FPU_CSR_OVF_S 0x00000010 167 #define FPU_CSR_UDF_S 0x00000008 168 #define FPU_CSR_INE_S 0x00000004 169 170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 171 #define FPU_CSR_RM 0x00000003 172 #define FPU_CSR_RN 0x0 /* nearest */ 173 #define FPU_CSR_RZ 0x1 /* towards zero */ 174 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 175 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 176 177 178 /* 179 * Values for PageMask register 180 */ 181 #ifdef CONFIG_CPU_VR41XX 182 183 /* Why doesn't stupidity hurt ... */ 184 185 #define PM_1K 0x00000000 186 #define PM_4K 0x00001800 187 #define PM_16K 0x00007800 188 #define PM_64K 0x0001f800 189 #define PM_256K 0x0007f800 190 191 #else 192 193 #define PM_4K 0x00000000 194 #define PM_8K 0x00002000 195 #define PM_16K 0x00006000 196 #define PM_32K 0x0000e000 197 #define PM_64K 0x0001e000 198 #define PM_128K 0x0003e000 199 #define PM_256K 0x0007e000 200 #define PM_512K 0x000fe000 201 #define PM_1M 0x001fe000 202 #define PM_2M 0x003fe000 203 #define PM_4M 0x007fe000 204 #define PM_8M 0x00ffe000 205 #define PM_16M 0x01ffe000 206 #define PM_32M 0x03ffe000 207 #define PM_64M 0x07ffe000 208 #define PM_256M 0x1fffe000 209 #define PM_1G 0x7fffe000 210 211 #endif 212 213 /* 214 * Default page size for a given kernel configuration 215 */ 216 #ifdef CONFIG_PAGE_SIZE_4KB 217 #define PM_DEFAULT_MASK PM_4K 218 #elif defined(CONFIG_PAGE_SIZE_8KB) 219 #define PM_DEFAULT_MASK PM_8K 220 #elif defined(CONFIG_PAGE_SIZE_16KB) 221 #define PM_DEFAULT_MASK PM_16K 222 #elif defined(CONFIG_PAGE_SIZE_32KB) 223 #define PM_DEFAULT_MASK PM_32K 224 #elif defined(CONFIG_PAGE_SIZE_64KB) 225 #define PM_DEFAULT_MASK PM_64K 226 #else 227 #error Bad page size configuration! 228 #endif 229 230 /* 231 * Default huge tlb size for a given kernel configuration 232 */ 233 #ifdef CONFIG_PAGE_SIZE_4KB 234 #define PM_HUGE_MASK PM_1M 235 #elif defined(CONFIG_PAGE_SIZE_8KB) 236 #define PM_HUGE_MASK PM_4M 237 #elif defined(CONFIG_PAGE_SIZE_16KB) 238 #define PM_HUGE_MASK PM_16M 239 #elif defined(CONFIG_PAGE_SIZE_32KB) 240 #define PM_HUGE_MASK PM_64M 241 #elif defined(CONFIG_PAGE_SIZE_64KB) 242 #define PM_HUGE_MASK PM_256M 243 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 244 #error Bad page size configuration for hugetlbfs! 245 #endif 246 247 /* 248 * Values used for computation of new tlb entries 249 */ 250 #define PL_4K 12 251 #define PL_16K 14 252 #define PL_64K 16 253 #define PL_256K 18 254 #define PL_1M 20 255 #define PL_4M 22 256 #define PL_16M 24 257 #define PL_64M 26 258 #define PL_256M 28 259 260 /* 261 * PageGrain bits 262 */ 263 #define PG_RIE (_ULCAST_(1) << 31) 264 #define PG_XIE (_ULCAST_(1) << 30) 265 #define PG_ELPA (_ULCAST_(1) << 29) 266 #define PG_ESP (_ULCAST_(1) << 28) 267 268 /* 269 * R4x00 interrupt enable / cause bits 270 */ 271 #define IE_SW0 (_ULCAST_(1) << 8) 272 #define IE_SW1 (_ULCAST_(1) << 9) 273 #define IE_IRQ0 (_ULCAST_(1) << 10) 274 #define IE_IRQ1 (_ULCAST_(1) << 11) 275 #define IE_IRQ2 (_ULCAST_(1) << 12) 276 #define IE_IRQ3 (_ULCAST_(1) << 13) 277 #define IE_IRQ4 (_ULCAST_(1) << 14) 278 #define IE_IRQ5 (_ULCAST_(1) << 15) 279 280 /* 281 * R4x00 interrupt cause bits 282 */ 283 #define C_SW0 (_ULCAST_(1) << 8) 284 #define C_SW1 (_ULCAST_(1) << 9) 285 #define C_IRQ0 (_ULCAST_(1) << 10) 286 #define C_IRQ1 (_ULCAST_(1) << 11) 287 #define C_IRQ2 (_ULCAST_(1) << 12) 288 #define C_IRQ3 (_ULCAST_(1) << 13) 289 #define C_IRQ4 (_ULCAST_(1) << 14) 290 #define C_IRQ5 (_ULCAST_(1) << 15) 291 292 /* 293 * Bitfields in the R4xx0 cp0 status register 294 */ 295 #define ST0_IE 0x00000001 296 #define ST0_EXL 0x00000002 297 #define ST0_ERL 0x00000004 298 #define ST0_KSU 0x00000018 299 # define KSU_USER 0x00000010 300 # define KSU_SUPERVISOR 0x00000008 301 # define KSU_KERNEL 0x00000000 302 #define ST0_UX 0x00000020 303 #define ST0_SX 0x00000040 304 #define ST0_KX 0x00000080 305 #define ST0_DE 0x00010000 306 #define ST0_CE 0x00020000 307 308 /* 309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 310 * cacheops in userspace. This bit exists only on RM7000 and RM9000 311 * processors. 312 */ 313 #define ST0_CO 0x08000000 314 315 /* 316 * Bitfields in the R[23]000 cp0 status register. 317 */ 318 #define ST0_IEC 0x00000001 319 #define ST0_KUC 0x00000002 320 #define ST0_IEP 0x00000004 321 #define ST0_KUP 0x00000008 322 #define ST0_IEO 0x00000010 323 #define ST0_KUO 0x00000020 324 /* bits 6 & 7 are reserved on R[23]000 */ 325 #define ST0_ISC 0x00010000 326 #define ST0_SWC 0x00020000 327 #define ST0_CM 0x00080000 328 329 /* 330 * Bits specific to the R4640/R4650 331 */ 332 #define ST0_UM (_ULCAST_(1) << 4) 333 #define ST0_IL (_ULCAST_(1) << 23) 334 #define ST0_DL (_ULCAST_(1) << 24) 335 336 /* 337 * Enable the MIPS MDMX and DSP ASEs 338 */ 339 #define ST0_MX 0x01000000 340 341 /* 342 * Bitfields in the TX39 family CP0 Configuration Register 3 343 */ 344 #define TX39_CONF_ICS_SHIFT 19 345 #define TX39_CONF_ICS_MASK 0x00380000 346 #define TX39_CONF_ICS_1KB 0x00000000 347 #define TX39_CONF_ICS_2KB 0x00080000 348 #define TX39_CONF_ICS_4KB 0x00100000 349 #define TX39_CONF_ICS_8KB 0x00180000 350 #define TX39_CONF_ICS_16KB 0x00200000 351 352 #define TX39_CONF_DCS_SHIFT 16 353 #define TX39_CONF_DCS_MASK 0x00070000 354 #define TX39_CONF_DCS_1KB 0x00000000 355 #define TX39_CONF_DCS_2KB 0x00010000 356 #define TX39_CONF_DCS_4KB 0x00020000 357 #define TX39_CONF_DCS_8KB 0x00030000 358 #define TX39_CONF_DCS_16KB 0x00040000 359 360 #define TX39_CONF_CWFON 0x00004000 361 #define TX39_CONF_WBON 0x00002000 362 #define TX39_CONF_RF_SHIFT 10 363 #define TX39_CONF_RF_MASK 0x00000c00 364 #define TX39_CONF_DOZE 0x00000200 365 #define TX39_CONF_HALT 0x00000100 366 #define TX39_CONF_LOCK 0x00000080 367 #define TX39_CONF_ICE 0x00000020 368 #define TX39_CONF_DCE 0x00000010 369 #define TX39_CONF_IRSIZE_SHIFT 2 370 #define TX39_CONF_IRSIZE_MASK 0x0000000c 371 #define TX39_CONF_DRSIZE_SHIFT 0 372 #define TX39_CONF_DRSIZE_MASK 0x00000003 373 374 /* 375 * Status register bits available in all MIPS CPUs. 376 */ 377 #define ST0_IM 0x0000ff00 378 #define STATUSB_IP0 8 379 #define STATUSF_IP0 (_ULCAST_(1) << 8) 380 #define STATUSB_IP1 9 381 #define STATUSF_IP1 (_ULCAST_(1) << 9) 382 #define STATUSB_IP2 10 383 #define STATUSF_IP2 (_ULCAST_(1) << 10) 384 #define STATUSB_IP3 11 385 #define STATUSF_IP3 (_ULCAST_(1) << 11) 386 #define STATUSB_IP4 12 387 #define STATUSF_IP4 (_ULCAST_(1) << 12) 388 #define STATUSB_IP5 13 389 #define STATUSF_IP5 (_ULCAST_(1) << 13) 390 #define STATUSB_IP6 14 391 #define STATUSF_IP6 (_ULCAST_(1) << 14) 392 #define STATUSB_IP7 15 393 #define STATUSF_IP7 (_ULCAST_(1) << 15) 394 #define STATUSB_IP8 0 395 #define STATUSF_IP8 (_ULCAST_(1) << 0) 396 #define STATUSB_IP9 1 397 #define STATUSF_IP9 (_ULCAST_(1) << 1) 398 #define STATUSB_IP10 2 399 #define STATUSF_IP10 (_ULCAST_(1) << 2) 400 #define STATUSB_IP11 3 401 #define STATUSF_IP11 (_ULCAST_(1) << 3) 402 #define STATUSB_IP12 4 403 #define STATUSF_IP12 (_ULCAST_(1) << 4) 404 #define STATUSB_IP13 5 405 #define STATUSF_IP13 (_ULCAST_(1) << 5) 406 #define STATUSB_IP14 6 407 #define STATUSF_IP14 (_ULCAST_(1) << 6) 408 #define STATUSB_IP15 7 409 #define STATUSF_IP15 (_ULCAST_(1) << 7) 410 #define ST0_CH 0x00040000 411 #define ST0_NMI 0x00080000 412 #define ST0_SR 0x00100000 413 #define ST0_TS 0x00200000 414 #define ST0_BEV 0x00400000 415 #define ST0_RE 0x02000000 416 #define ST0_FR 0x04000000 417 #define ST0_CU 0xf0000000 418 #define ST0_CU0 0x10000000 419 #define ST0_CU1 0x20000000 420 #define ST0_CU2 0x40000000 421 #define ST0_CU3 0x80000000 422 #define ST0_XX 0x80000000 /* MIPS IV naming */ 423 424 /* 425 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 426 * 427 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 428 */ 429 #define INTCTLB_IPPCI 26 430 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 431 #define INTCTLB_IPTI 29 432 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 433 434 /* 435 * Bitfields and bit numbers in the coprocessor 0 cause register. 436 * 437 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 438 */ 439 #define CAUSEB_EXCCODE 2 440 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 441 #define CAUSEB_IP 8 442 #define CAUSEF_IP (_ULCAST_(255) << 8) 443 #define CAUSEB_IP0 8 444 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 445 #define CAUSEB_IP1 9 446 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 447 #define CAUSEB_IP2 10 448 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 449 #define CAUSEB_IP3 11 450 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 451 #define CAUSEB_IP4 12 452 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 453 #define CAUSEB_IP5 13 454 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 455 #define CAUSEB_IP6 14 456 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 457 #define CAUSEB_IP7 15 458 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 459 #define CAUSEB_IV 23 460 #define CAUSEF_IV (_ULCAST_(1) << 23) 461 #define CAUSEB_PCI 26 462 #define CAUSEF_PCI (_ULCAST_(1) << 26) 463 #define CAUSEB_CE 28 464 #define CAUSEF_CE (_ULCAST_(3) << 28) 465 #define CAUSEB_TI 30 466 #define CAUSEF_TI (_ULCAST_(1) << 30) 467 #define CAUSEB_BD 31 468 #define CAUSEF_BD (_ULCAST_(1) << 31) 469 470 /* 471 * Bits in the coprocessor 0 config register. 472 */ 473 /* Generic bits. */ 474 #define CONF_CM_CACHABLE_NO_WA 0 475 #define CONF_CM_CACHABLE_WA 1 476 #define CONF_CM_UNCACHED 2 477 #define CONF_CM_CACHABLE_NONCOHERENT 3 478 #define CONF_CM_CACHABLE_CE 4 479 #define CONF_CM_CACHABLE_COW 5 480 #define CONF_CM_CACHABLE_CUW 6 481 #define CONF_CM_CACHABLE_ACCELERATED 7 482 #define CONF_CM_CMASK 7 483 #define CONF_BE (_ULCAST_(1) << 15) 484 485 /* Bits common to various processors. */ 486 #define CONF_CU (_ULCAST_(1) << 3) 487 #define CONF_DB (_ULCAST_(1) << 4) 488 #define CONF_IB (_ULCAST_(1) << 5) 489 #define CONF_DC (_ULCAST_(7) << 6) 490 #define CONF_IC (_ULCAST_(7) << 9) 491 #define CONF_EB (_ULCAST_(1) << 13) 492 #define CONF_EM (_ULCAST_(1) << 14) 493 #define CONF_SM (_ULCAST_(1) << 16) 494 #define CONF_SC (_ULCAST_(1) << 17) 495 #define CONF_EW (_ULCAST_(3) << 18) 496 #define CONF_EP (_ULCAST_(15)<< 24) 497 #define CONF_EC (_ULCAST_(7) << 28) 498 #define CONF_CM (_ULCAST_(1) << 31) 499 500 /* Bits specific to the R4xx0. */ 501 #define R4K_CONF_SW (_ULCAST_(1) << 20) 502 #define R4K_CONF_SS (_ULCAST_(1) << 21) 503 #define R4K_CONF_SB (_ULCAST_(3) << 22) 504 505 /* Bits specific to the R5000. */ 506 #define R5K_CONF_SE (_ULCAST_(1) << 12) 507 #define R5K_CONF_SS (_ULCAST_(3) << 20) 508 509 /* Bits specific to the RM7000. */ 510 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 511 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 512 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 513 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 514 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 515 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 516 517 /* Bits specific to the R10000. */ 518 #define R10K_CONF_DN (_ULCAST_(3) << 3) 519 #define R10K_CONF_CT (_ULCAST_(1) << 5) 520 #define R10K_CONF_PE (_ULCAST_(1) << 6) 521 #define R10K_CONF_PM (_ULCAST_(3) << 7) 522 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 523 #define R10K_CONF_SB (_ULCAST_(1) << 13) 524 #define R10K_CONF_SK (_ULCAST_(1) << 14) 525 #define R10K_CONF_SS (_ULCAST_(7) << 16) 526 #define R10K_CONF_SC (_ULCAST_(7) << 19) 527 #define R10K_CONF_DC (_ULCAST_(7) << 26) 528 #define R10K_CONF_IC (_ULCAST_(7) << 29) 529 530 /* Bits specific to the VR41xx. */ 531 #define VR41_CONF_CS (_ULCAST_(1) << 12) 532 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 533 #define VR41_CONF_BP (_ULCAST_(1) << 16) 534 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 535 #define VR41_CONF_AD (_ULCAST_(1) << 23) 536 537 /* Bits specific to the R30xx. */ 538 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 539 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 540 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 541 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 542 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 543 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 544 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 545 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 546 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 547 548 /* Bits specific to the TX49. */ 549 #define TX49_CONF_DC (_ULCAST_(1) << 16) 550 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 551 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 552 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 553 554 /* Bits specific to the MIPS32/64 PRA. */ 555 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 556 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 557 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 558 #define MIPS_CONF_M (_ULCAST_(1) << 31) 559 560 /* 561 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 562 */ 563 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 564 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 565 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 566 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 567 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 568 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 569 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 570 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 571 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 572 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 573 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 574 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 575 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 576 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 577 578 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 579 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 580 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 581 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 582 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 583 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 584 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 585 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 586 587 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 588 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 589 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 590 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 591 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 592 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 593 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 594 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 595 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 596 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 597 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 598 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 599 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 600 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 601 602 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 603 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 604 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 605 606 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 607 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 608 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 609 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 610 #define MIPS_CONF5_CV (_ULCAST_(1) << 29) 611 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 612 613 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 614 615 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 616 617 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 618 619 620 /* 621 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 622 */ 623 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 624 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 625 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 626 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 627 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 628 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 629 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 630 631 #ifndef __ASSEMBLY__ 632 633 /* 634 * Macros for handling the ISA mode bit for microMIPS. 635 */ 636 #define get_isa16_mode(x) ((x) & 0x1) 637 #define msk_isa16_mode(x) ((x) & ~0x1) 638 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) 639 640 /* 641 * microMIPS instructions can be 16-bit or 32-bit in length. This 642 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. 643 */ 644 static inline int mm_insn_16bit(u16 insn) 645 { 646 u16 opcode = (insn >> 10) & 0x7; 647 648 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 649 } 650 651 /* 652 * Functions to access the R10000 performance counters. These are basically 653 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 654 * performance counter number encoded into bits 1 ... 5 of the instruction. 655 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 656 * disassembler these will look like an access to sel 0 or 1. 657 */ 658 #define read_r10k_perf_cntr(counter) \ 659 ({ \ 660 unsigned int __res; \ 661 __asm__ __volatile__( \ 662 "mfpc\t%0, %1" \ 663 : "=r" (__res) \ 664 : "i" (counter)); \ 665 \ 666 __res; \ 667 }) 668 669 #define write_r10k_perf_cntr(counter,val) \ 670 do { \ 671 __asm__ __volatile__( \ 672 "mtpc\t%0, %1" \ 673 : \ 674 : "r" (val), "i" (counter)); \ 675 } while (0) 676 677 #define read_r10k_perf_event(counter) \ 678 ({ \ 679 unsigned int __res; \ 680 __asm__ __volatile__( \ 681 "mfps\t%0, %1" \ 682 : "=r" (__res) \ 683 : "i" (counter)); \ 684 \ 685 __res; \ 686 }) 687 688 #define write_r10k_perf_cntl(counter,val) \ 689 do { \ 690 __asm__ __volatile__( \ 691 "mtps\t%0, %1" \ 692 : \ 693 : "r" (val), "i" (counter)); \ 694 } while (0) 695 696 697 /* 698 * Macros to access the system control coprocessor 699 */ 700 701 #define __read_32bit_c0_register(source, sel) \ 702 ({ int __res; \ 703 if (sel == 0) \ 704 __asm__ __volatile__( \ 705 "mfc0\t%0, " #source "\n\t" \ 706 : "=r" (__res)); \ 707 else \ 708 __asm__ __volatile__( \ 709 ".set\tmips32\n\t" \ 710 "mfc0\t%0, " #source ", " #sel "\n\t" \ 711 ".set\tmips0\n\t" \ 712 : "=r" (__res)); \ 713 __res; \ 714 }) 715 716 #define __read_64bit_c0_register(source, sel) \ 717 ({ unsigned long long __res; \ 718 if (sizeof(unsigned long) == 4) \ 719 __res = __read_64bit_c0_split(source, sel); \ 720 else if (sel == 0) \ 721 __asm__ __volatile__( \ 722 ".set\tmips3\n\t" \ 723 "dmfc0\t%0, " #source "\n\t" \ 724 ".set\tmips0" \ 725 : "=r" (__res)); \ 726 else \ 727 __asm__ __volatile__( \ 728 ".set\tmips64\n\t" \ 729 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 730 ".set\tmips0" \ 731 : "=r" (__res)); \ 732 __res; \ 733 }) 734 735 #define __write_32bit_c0_register(register, sel, value) \ 736 do { \ 737 if (sel == 0) \ 738 __asm__ __volatile__( \ 739 "mtc0\t%z0, " #register "\n\t" \ 740 : : "Jr" ((unsigned int)(value))); \ 741 else \ 742 __asm__ __volatile__( \ 743 ".set\tmips32\n\t" \ 744 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 745 ".set\tmips0" \ 746 : : "Jr" ((unsigned int)(value))); \ 747 } while (0) 748 749 #define __write_64bit_c0_register(register, sel, value) \ 750 do { \ 751 if (sizeof(unsigned long) == 4) \ 752 __write_64bit_c0_split(register, sel, value); \ 753 else if (sel == 0) \ 754 __asm__ __volatile__( \ 755 ".set\tmips3\n\t" \ 756 "dmtc0\t%z0, " #register "\n\t" \ 757 ".set\tmips0" \ 758 : : "Jr" (value)); \ 759 else \ 760 __asm__ __volatile__( \ 761 ".set\tmips64\n\t" \ 762 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 763 ".set\tmips0" \ 764 : : "Jr" (value)); \ 765 } while (0) 766 767 #define __read_ulong_c0_register(reg, sel) \ 768 ((sizeof(unsigned long) == 4) ? \ 769 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 770 (unsigned long) __read_64bit_c0_register(reg, sel)) 771 772 #define __write_ulong_c0_register(reg, sel, val) \ 773 do { \ 774 if (sizeof(unsigned long) == 4) \ 775 __write_32bit_c0_register(reg, sel, val); \ 776 else \ 777 __write_64bit_c0_register(reg, sel, val); \ 778 } while (0) 779 780 /* 781 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 782 */ 783 #define __read_32bit_c0_ctrl_register(source) \ 784 ({ int __res; \ 785 __asm__ __volatile__( \ 786 "cfc0\t%0, " #source "\n\t" \ 787 : "=r" (__res)); \ 788 __res; \ 789 }) 790 791 #define __write_32bit_c0_ctrl_register(register, value) \ 792 do { \ 793 __asm__ __volatile__( \ 794 "ctc0\t%z0, " #register "\n\t" \ 795 : : "Jr" ((unsigned int)(value))); \ 796 } while (0) 797 798 /* 799 * These versions are only needed for systems with more than 38 bits of 800 * physical address space running the 32-bit kernel. That's none atm :-) 801 */ 802 #define __read_64bit_c0_split(source, sel) \ 803 ({ \ 804 unsigned long long __val; \ 805 unsigned long __flags; \ 806 \ 807 local_irq_save(__flags); \ 808 if (sel == 0) \ 809 __asm__ __volatile__( \ 810 ".set\tmips64\n\t" \ 811 "dmfc0\t%M0, " #source "\n\t" \ 812 "dsll\t%L0, %M0, 32\n\t" \ 813 "dsra\t%M0, %M0, 32\n\t" \ 814 "dsra\t%L0, %L0, 32\n\t" \ 815 ".set\tmips0" \ 816 : "=r" (__val)); \ 817 else \ 818 __asm__ __volatile__( \ 819 ".set\tmips64\n\t" \ 820 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 821 "dsll\t%L0, %M0, 32\n\t" \ 822 "dsra\t%M0, %M0, 32\n\t" \ 823 "dsra\t%L0, %L0, 32\n\t" \ 824 ".set\tmips0" \ 825 : "=r" (__val)); \ 826 local_irq_restore(__flags); \ 827 \ 828 __val; \ 829 }) 830 831 #define __write_64bit_c0_split(source, sel, val) \ 832 do { \ 833 unsigned long __flags; \ 834 \ 835 local_irq_save(__flags); \ 836 if (sel == 0) \ 837 __asm__ __volatile__( \ 838 ".set\tmips64\n\t" \ 839 "dsll\t%L0, %L0, 32\n\t" \ 840 "dsrl\t%L0, %L0, 32\n\t" \ 841 "dsll\t%M0, %M0, 32\n\t" \ 842 "or\t%L0, %L0, %M0\n\t" \ 843 "dmtc0\t%L0, " #source "\n\t" \ 844 ".set\tmips0" \ 845 : : "r" (val)); \ 846 else \ 847 __asm__ __volatile__( \ 848 ".set\tmips64\n\t" \ 849 "dsll\t%L0, %L0, 32\n\t" \ 850 "dsrl\t%L0, %L0, 32\n\t" \ 851 "dsll\t%M0, %M0, 32\n\t" \ 852 "or\t%L0, %L0, %M0\n\t" \ 853 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 854 ".set\tmips0" \ 855 : : "r" (val)); \ 856 local_irq_restore(__flags); \ 857 } while (0) 858 859 #define read_c0_index() __read_32bit_c0_register($0, 0) 860 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 861 862 #define read_c0_random() __read_32bit_c0_register($1, 0) 863 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 864 865 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 866 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 867 868 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 869 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 870 871 #define read_c0_conf() __read_32bit_c0_register($3, 0) 872 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 873 874 #define read_c0_context() __read_ulong_c0_register($4, 0) 875 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 876 877 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 878 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 879 880 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 881 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 882 883 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 884 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 885 886 #define read_c0_wired() __read_32bit_c0_register($6, 0) 887 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 888 889 #define read_c0_info() __read_32bit_c0_register($7, 0) 890 891 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 892 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 893 894 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 895 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 896 897 #define read_c0_count() __read_32bit_c0_register($9, 0) 898 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 899 900 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 901 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 902 903 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 904 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 905 906 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 907 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 908 909 #define read_c0_compare() __read_32bit_c0_register($11, 0) 910 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 911 912 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 913 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 914 915 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 916 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 917 918 #define read_c0_status() __read_32bit_c0_register($12, 0) 919 #ifdef CONFIG_MIPS_MT_SMTC 920 #define write_c0_status(val) \ 921 do { \ 922 __write_32bit_c0_register($12, 0, val); \ 923 __ehb(); \ 924 } while (0) 925 #else 926 /* 927 * Legacy non-SMTC code, which may be hazardous 928 * but which might not support EHB 929 */ 930 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 931 #endif /* CONFIG_MIPS_MT_SMTC */ 932 933 #define read_c0_cause() __read_32bit_c0_register($13, 0) 934 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 935 936 #define read_c0_epc() __read_ulong_c0_register($14, 0) 937 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 938 939 #define read_c0_prid() __read_32bit_c0_register($15, 0) 940 941 #define read_c0_config() __read_32bit_c0_register($16, 0) 942 #define read_c0_config1() __read_32bit_c0_register($16, 1) 943 #define read_c0_config2() __read_32bit_c0_register($16, 2) 944 #define read_c0_config3() __read_32bit_c0_register($16, 3) 945 #define read_c0_config4() __read_32bit_c0_register($16, 4) 946 #define read_c0_config5() __read_32bit_c0_register($16, 5) 947 #define read_c0_config6() __read_32bit_c0_register($16, 6) 948 #define read_c0_config7() __read_32bit_c0_register($16, 7) 949 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 950 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 951 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 952 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 953 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 954 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 955 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 956 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 957 958 /* 959 * The WatchLo register. There may be up to 8 of them. 960 */ 961 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 962 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 963 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 964 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 965 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 966 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 967 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 968 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 969 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 970 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 971 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 972 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 973 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 974 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 975 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 976 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 977 978 /* 979 * The WatchHi register. There may be up to 8 of them. 980 */ 981 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 982 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 983 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 984 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 985 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 986 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 987 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 988 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 989 990 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 991 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 992 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 993 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 994 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 995 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 996 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 997 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 998 999 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 1000 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 1001 1002 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 1003 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 1004 1005 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 1006 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 1007 1008 #define read_c0_diag() __read_32bit_c0_register($22, 0) 1009 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 1010 1011 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 1012 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 1013 1014 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 1015 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 1016 1017 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 1018 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1019 1020 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 1021 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1022 1023 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 1024 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1025 1026 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1027 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1028 1029 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1030 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1031 1032 /* 1033 * MIPS32 / MIPS64 performance counters 1034 */ 1035 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1036 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1037 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1038 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1039 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1040 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1041 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1042 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1043 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1044 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1045 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1046 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1047 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1048 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1049 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1050 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1051 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1052 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1053 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1054 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1055 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1056 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1057 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1058 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1059 1060 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1061 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1062 1063 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1064 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1065 1066 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1067 1068 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1069 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1070 1071 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1072 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1073 1074 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1075 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1076 1077 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1078 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1079 1080 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1081 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1082 1083 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1084 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1085 1086 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1087 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1088 1089 /* MIPSR2 */ 1090 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1091 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1092 1093 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1094 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1095 1096 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1097 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1098 1099 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1100 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1101 1102 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1103 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1104 1105 1106 /* Cavium OCTEON (cnMIPS) */ 1107 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1108 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1109 1110 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1111 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1112 1113 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1114 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1115 /* 1116 * The cacheerr registers are not standardized. On OCTEON, they are 1117 * 64 bits wide. 1118 */ 1119 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1120 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1121 1122 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1123 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1124 1125 /* BMIPS3300 */ 1126 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1127 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1128 1129 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1130 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1131 1132 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1133 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1134 1135 /* BMIPS43xx */ 1136 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1137 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1138 1139 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1140 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1141 1142 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1143 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1144 1145 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1146 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1147 1148 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1149 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1150 1151 /* BMIPS5000 */ 1152 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1153 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1154 1155 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1156 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1157 1158 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1159 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1160 1161 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1162 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1163 1164 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1165 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1166 1167 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1168 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1169 1170 /* 1171 * Macros to access the floating point coprocessor control registers 1172 */ 1173 #define read_32bit_cp1_register(source) \ 1174 ({ \ 1175 int __res; \ 1176 \ 1177 __asm__ __volatile__( \ 1178 " .set push \n" \ 1179 " .set reorder \n" \ 1180 " # gas fails to assemble cfc1 for some archs, \n" \ 1181 " # like Octeon. \n" \ 1182 " .set mips1 \n" \ 1183 " cfc1 %0,"STR(source)" \n" \ 1184 " .set pop \n" \ 1185 : "=r" (__res)); \ 1186 __res; \ 1187 }) 1188 1189 #ifdef HAVE_AS_DSP 1190 #define rddsp(mask) \ 1191 ({ \ 1192 unsigned int __dspctl; \ 1193 \ 1194 __asm__ __volatile__( \ 1195 " .set push \n" \ 1196 " .set dsp \n" \ 1197 " rddsp %0, %x1 \n" \ 1198 " .set pop \n" \ 1199 : "=r" (__dspctl) \ 1200 : "i" (mask)); \ 1201 __dspctl; \ 1202 }) 1203 1204 #define wrdsp(val, mask) \ 1205 do { \ 1206 __asm__ __volatile__( \ 1207 " .set push \n" \ 1208 " .set dsp \n" \ 1209 " wrdsp %0, %x1 \n" \ 1210 " .set pop \n" \ 1211 : \ 1212 : "r" (val), "i" (mask)); \ 1213 } while (0) 1214 1215 #define mflo0() \ 1216 ({ \ 1217 long mflo0; \ 1218 __asm__( \ 1219 " .set push \n" \ 1220 " .set dsp \n" \ 1221 " mflo %0, $ac0 \n" \ 1222 " .set pop \n" \ 1223 : "=r" (mflo0)); \ 1224 mflo0; \ 1225 }) 1226 1227 #define mflo1() \ 1228 ({ \ 1229 long mflo1; \ 1230 __asm__( \ 1231 " .set push \n" \ 1232 " .set dsp \n" \ 1233 " mflo %0, $ac1 \n" \ 1234 " .set pop \n" \ 1235 : "=r" (mflo1)); \ 1236 mflo1; \ 1237 }) 1238 1239 #define mflo2() \ 1240 ({ \ 1241 long mflo2; \ 1242 __asm__( \ 1243 " .set push \n" \ 1244 " .set dsp \n" \ 1245 " mflo %0, $ac2 \n" \ 1246 " .set pop \n" \ 1247 : "=r" (mflo2)); \ 1248 mflo2; \ 1249 }) 1250 1251 #define mflo3() \ 1252 ({ \ 1253 long mflo3; \ 1254 __asm__( \ 1255 " .set push \n" \ 1256 " .set dsp \n" \ 1257 " mflo %0, $ac3 \n" \ 1258 " .set pop \n" \ 1259 : "=r" (mflo3)); \ 1260 mflo3; \ 1261 }) 1262 1263 #define mfhi0() \ 1264 ({ \ 1265 long mfhi0; \ 1266 __asm__( \ 1267 " .set push \n" \ 1268 " .set dsp \n" \ 1269 " mfhi %0, $ac0 \n" \ 1270 " .set pop \n" \ 1271 : "=r" (mfhi0)); \ 1272 mfhi0; \ 1273 }) 1274 1275 #define mfhi1() \ 1276 ({ \ 1277 long mfhi1; \ 1278 __asm__( \ 1279 " .set push \n" \ 1280 " .set dsp \n" \ 1281 " mfhi %0, $ac1 \n" \ 1282 " .set pop \n" \ 1283 : "=r" (mfhi1)); \ 1284 mfhi1; \ 1285 }) 1286 1287 #define mfhi2() \ 1288 ({ \ 1289 long mfhi2; \ 1290 __asm__( \ 1291 " .set push \n" \ 1292 " .set dsp \n" \ 1293 " mfhi %0, $ac2 \n" \ 1294 " .set pop \n" \ 1295 : "=r" (mfhi2)); \ 1296 mfhi2; \ 1297 }) 1298 1299 #define mfhi3() \ 1300 ({ \ 1301 long mfhi3; \ 1302 __asm__( \ 1303 " .set push \n" \ 1304 " .set dsp \n" \ 1305 " mfhi %0, $ac3 \n" \ 1306 " .set pop \n" \ 1307 : "=r" (mfhi3)); \ 1308 mfhi3; \ 1309 }) 1310 1311 1312 #define mtlo0(x) \ 1313 ({ \ 1314 __asm__( \ 1315 " .set push \n" \ 1316 " .set dsp \n" \ 1317 " mtlo %0, $ac0 \n" \ 1318 " .set pop \n" \ 1319 : \ 1320 : "r" (x)); \ 1321 }) 1322 1323 #define mtlo1(x) \ 1324 ({ \ 1325 __asm__( \ 1326 " .set push \n" \ 1327 " .set dsp \n" \ 1328 " mtlo %0, $ac1 \n" \ 1329 " .set pop \n" \ 1330 : \ 1331 : "r" (x)); \ 1332 }) 1333 1334 #define mtlo2(x) \ 1335 ({ \ 1336 __asm__( \ 1337 " .set push \n" \ 1338 " .set dsp \n" \ 1339 " mtlo %0, $ac2 \n" \ 1340 " .set pop \n" \ 1341 : \ 1342 : "r" (x)); \ 1343 }) 1344 1345 #define mtlo3(x) \ 1346 ({ \ 1347 __asm__( \ 1348 " .set push \n" \ 1349 " .set dsp \n" \ 1350 " mtlo %0, $ac3 \n" \ 1351 " .set pop \n" \ 1352 : \ 1353 : "r" (x)); \ 1354 }) 1355 1356 #define mthi0(x) \ 1357 ({ \ 1358 __asm__( \ 1359 " .set push \n" \ 1360 " .set dsp \n" \ 1361 " mthi %0, $ac0 \n" \ 1362 " .set pop \n" \ 1363 : \ 1364 : "r" (x)); \ 1365 }) 1366 1367 #define mthi1(x) \ 1368 ({ \ 1369 __asm__( \ 1370 " .set push \n" \ 1371 " .set dsp \n" \ 1372 " mthi %0, $ac1 \n" \ 1373 " .set pop \n" \ 1374 : \ 1375 : "r" (x)); \ 1376 }) 1377 1378 #define mthi2(x) \ 1379 ({ \ 1380 __asm__( \ 1381 " .set push \n" \ 1382 " .set dsp \n" \ 1383 " mthi %0, $ac2 \n" \ 1384 " .set pop \n" \ 1385 : \ 1386 : "r" (x)); \ 1387 }) 1388 1389 #define mthi3(x) \ 1390 ({ \ 1391 __asm__( \ 1392 " .set push \n" \ 1393 " .set dsp \n" \ 1394 " mthi %0, $ac3 \n" \ 1395 " .set pop \n" \ 1396 : \ 1397 : "r" (x)); \ 1398 }) 1399 1400 #else 1401 1402 #ifdef CONFIG_CPU_MICROMIPS 1403 #define rddsp(mask) \ 1404 ({ \ 1405 unsigned int __res; \ 1406 \ 1407 __asm__ __volatile__( \ 1408 " .set push \n" \ 1409 " .set noat \n" \ 1410 " # rddsp $1, %x1 \n" \ 1411 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1412 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1413 " move %0, $1 \n" \ 1414 " .set pop \n" \ 1415 : "=r" (__res) \ 1416 : "i" (mask)); \ 1417 __res; \ 1418 }) 1419 1420 #define wrdsp(val, mask) \ 1421 do { \ 1422 __asm__ __volatile__( \ 1423 " .set push \n" \ 1424 " .set noat \n" \ 1425 " move $1, %0 \n" \ 1426 " # wrdsp $1, %x1 \n" \ 1427 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1428 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1429 " .set pop \n" \ 1430 : \ 1431 : "r" (val), "i" (mask)); \ 1432 } while (0) 1433 1434 #define _umips_dsp_mfxxx(ins) \ 1435 ({ \ 1436 unsigned long __treg; \ 1437 \ 1438 __asm__ __volatile__( \ 1439 " .set push \n" \ 1440 " .set noat \n" \ 1441 " .hword 0x0001 \n" \ 1442 " .hword %x1 \n" \ 1443 " move %0, $1 \n" \ 1444 " .set pop \n" \ 1445 : "=r" (__treg) \ 1446 : "i" (ins)); \ 1447 __treg; \ 1448 }) 1449 1450 #define _umips_dsp_mtxxx(val, ins) \ 1451 do { \ 1452 __asm__ __volatile__( \ 1453 " .set push \n" \ 1454 " .set noat \n" \ 1455 " move $1, %0 \n" \ 1456 " .hword 0x0001 \n" \ 1457 " .hword %x1 \n" \ 1458 " .set pop \n" \ 1459 : \ 1460 : "r" (val), "i" (ins)); \ 1461 } while (0) 1462 1463 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1464 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1465 1466 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1467 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1468 1469 #define mflo0() _umips_dsp_mflo(0) 1470 #define mflo1() _umips_dsp_mflo(1) 1471 #define mflo2() _umips_dsp_mflo(2) 1472 #define mflo3() _umips_dsp_mflo(3) 1473 1474 #define mfhi0() _umips_dsp_mfhi(0) 1475 #define mfhi1() _umips_dsp_mfhi(1) 1476 #define mfhi2() _umips_dsp_mfhi(2) 1477 #define mfhi3() _umips_dsp_mfhi(3) 1478 1479 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1480 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1481 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1482 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1483 1484 #define mthi0(x) _umips_dsp_mthi(x, 0) 1485 #define mthi1(x) _umips_dsp_mthi(x, 1) 1486 #define mthi2(x) _umips_dsp_mthi(x, 2) 1487 #define mthi3(x) _umips_dsp_mthi(x, 3) 1488 1489 #else /* !CONFIG_CPU_MICROMIPS */ 1490 #define rddsp(mask) \ 1491 ({ \ 1492 unsigned int __res; \ 1493 \ 1494 __asm__ __volatile__( \ 1495 " .set push \n" \ 1496 " .set noat \n" \ 1497 " # rddsp $1, %x1 \n" \ 1498 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1499 " move %0, $1 \n" \ 1500 " .set pop \n" \ 1501 : "=r" (__res) \ 1502 : "i" (mask)); \ 1503 __res; \ 1504 }) 1505 1506 #define wrdsp(val, mask) \ 1507 do { \ 1508 __asm__ __volatile__( \ 1509 " .set push \n" \ 1510 " .set noat \n" \ 1511 " move $1, %0 \n" \ 1512 " # wrdsp $1, %x1 \n" \ 1513 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1514 " .set pop \n" \ 1515 : \ 1516 : "r" (val), "i" (mask)); \ 1517 } while (0) 1518 1519 #define _dsp_mfxxx(ins) \ 1520 ({ \ 1521 unsigned long __treg; \ 1522 \ 1523 __asm__ __volatile__( \ 1524 " .set push \n" \ 1525 " .set noat \n" \ 1526 " .word (0x00000810 | %1) \n" \ 1527 " move %0, $1 \n" \ 1528 " .set pop \n" \ 1529 : "=r" (__treg) \ 1530 : "i" (ins)); \ 1531 __treg; \ 1532 }) 1533 1534 #define _dsp_mtxxx(val, ins) \ 1535 do { \ 1536 __asm__ __volatile__( \ 1537 " .set push \n" \ 1538 " .set noat \n" \ 1539 " move $1, %0 \n" \ 1540 " .word (0x00200011 | %1) \n" \ 1541 " .set pop \n" \ 1542 : \ 1543 : "r" (val), "i" (ins)); \ 1544 } while (0) 1545 1546 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1547 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1548 1549 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1550 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1551 1552 #define mflo0() _dsp_mflo(0) 1553 #define mflo1() _dsp_mflo(1) 1554 #define mflo2() _dsp_mflo(2) 1555 #define mflo3() _dsp_mflo(3) 1556 1557 #define mfhi0() _dsp_mfhi(0) 1558 #define mfhi1() _dsp_mfhi(1) 1559 #define mfhi2() _dsp_mfhi(2) 1560 #define mfhi3() _dsp_mfhi(3) 1561 1562 #define mtlo0(x) _dsp_mtlo(x, 0) 1563 #define mtlo1(x) _dsp_mtlo(x, 1) 1564 #define mtlo2(x) _dsp_mtlo(x, 2) 1565 #define mtlo3(x) _dsp_mtlo(x, 3) 1566 1567 #define mthi0(x) _dsp_mthi(x, 0) 1568 #define mthi1(x) _dsp_mthi(x, 1) 1569 #define mthi2(x) _dsp_mthi(x, 2) 1570 #define mthi3(x) _dsp_mthi(x, 3) 1571 1572 #endif /* CONFIG_CPU_MICROMIPS */ 1573 #endif 1574 1575 /* 1576 * TLB operations. 1577 * 1578 * It is responsibility of the caller to take care of any TLB hazards. 1579 */ 1580 static inline void tlb_probe(void) 1581 { 1582 __asm__ __volatile__( 1583 ".set noreorder\n\t" 1584 "tlbp\n\t" 1585 ".set reorder"); 1586 } 1587 1588 static inline void tlb_read(void) 1589 { 1590 #if MIPS34K_MISSED_ITLB_WAR 1591 int res = 0; 1592 1593 __asm__ __volatile__( 1594 " .set push \n" 1595 " .set noreorder \n" 1596 " .set noat \n" 1597 " .set mips32r2 \n" 1598 " .word 0x41610001 # dvpe $1 \n" 1599 " move %0, $1 \n" 1600 " ehb \n" 1601 " .set pop \n" 1602 : "=r" (res)); 1603 1604 instruction_hazard(); 1605 #endif 1606 1607 __asm__ __volatile__( 1608 ".set noreorder\n\t" 1609 "tlbr\n\t" 1610 ".set reorder"); 1611 1612 #if MIPS34K_MISSED_ITLB_WAR 1613 if ((res & _ULCAST_(1))) 1614 __asm__ __volatile__( 1615 " .set push \n" 1616 " .set noreorder \n" 1617 " .set noat \n" 1618 " .set mips32r2 \n" 1619 " .word 0x41600021 # evpe \n" 1620 " ehb \n" 1621 " .set pop \n"); 1622 #endif 1623 } 1624 1625 static inline void tlb_write_indexed(void) 1626 { 1627 __asm__ __volatile__( 1628 ".set noreorder\n\t" 1629 "tlbwi\n\t" 1630 ".set reorder"); 1631 } 1632 1633 static inline void tlb_write_random(void) 1634 { 1635 __asm__ __volatile__( 1636 ".set noreorder\n\t" 1637 "tlbwr\n\t" 1638 ".set reorder"); 1639 } 1640 1641 /* 1642 * Manipulate bits in a c0 register. 1643 */ 1644 #ifndef CONFIG_MIPS_MT_SMTC 1645 /* 1646 * SMTC Linux requires shutting-down microthread scheduling 1647 * during CP0 register read-modify-write sequences. 1648 */ 1649 #define __BUILD_SET_C0(name) \ 1650 static inline unsigned int \ 1651 set_c0_##name(unsigned int set) \ 1652 { \ 1653 unsigned int res, new; \ 1654 \ 1655 res = read_c0_##name(); \ 1656 new = res | set; \ 1657 write_c0_##name(new); \ 1658 \ 1659 return res; \ 1660 } \ 1661 \ 1662 static inline unsigned int \ 1663 clear_c0_##name(unsigned int clear) \ 1664 { \ 1665 unsigned int res, new; \ 1666 \ 1667 res = read_c0_##name(); \ 1668 new = res & ~clear; \ 1669 write_c0_##name(new); \ 1670 \ 1671 return res; \ 1672 } \ 1673 \ 1674 static inline unsigned int \ 1675 change_c0_##name(unsigned int change, unsigned int val) \ 1676 { \ 1677 unsigned int res, new; \ 1678 \ 1679 res = read_c0_##name(); \ 1680 new = res & ~change; \ 1681 new |= (val & change); \ 1682 write_c0_##name(new); \ 1683 \ 1684 return res; \ 1685 } 1686 1687 #else /* SMTC versions that manage MT scheduling */ 1688 1689 #include <linux/irqflags.h> 1690 1691 /* 1692 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1693 * header file recursion. 1694 */ 1695 static inline unsigned int __dmt(void) 1696 { 1697 int res; 1698 1699 __asm__ __volatile__( 1700 " .set push \n" 1701 " .set mips32r2 \n" 1702 " .set noat \n" 1703 " .word 0x41610BC1 # dmt $1 \n" 1704 " ehb \n" 1705 " move %0, $1 \n" 1706 " .set pop \n" 1707 : "=r" (res)); 1708 1709 instruction_hazard(); 1710 1711 return res; 1712 } 1713 1714 #define __VPECONTROL_TE_SHIFT 15 1715 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1716 1717 #define __EMT_ENABLE __VPECONTROL_TE 1718 1719 static inline void __emt(unsigned int previous) 1720 { 1721 if ((previous & __EMT_ENABLE)) 1722 __asm__ __volatile__( 1723 " .set mips32r2 \n" 1724 " .word 0x41600be1 # emt \n" 1725 " ehb \n" 1726 " .set mips0 \n"); 1727 } 1728 1729 static inline void __ehb(void) 1730 { 1731 __asm__ __volatile__( 1732 " .set mips32r2 \n" 1733 " ehb \n" " .set mips0 \n"); 1734 } 1735 1736 /* 1737 * Note that local_irq_save/restore affect TC-specific IXMT state, 1738 * not Status.IE as in non-SMTC kernel. 1739 */ 1740 1741 #define __BUILD_SET_C0(name) \ 1742 static inline unsigned int \ 1743 set_c0_##name(unsigned int set) \ 1744 { \ 1745 unsigned int res; \ 1746 unsigned int new; \ 1747 unsigned int omt; \ 1748 unsigned long flags; \ 1749 \ 1750 local_irq_save(flags); \ 1751 omt = __dmt(); \ 1752 res = read_c0_##name(); \ 1753 new = res | set; \ 1754 write_c0_##name(new); \ 1755 __emt(omt); \ 1756 local_irq_restore(flags); \ 1757 \ 1758 return res; \ 1759 } \ 1760 \ 1761 static inline unsigned int \ 1762 clear_c0_##name(unsigned int clear) \ 1763 { \ 1764 unsigned int res; \ 1765 unsigned int new; \ 1766 unsigned int omt; \ 1767 unsigned long flags; \ 1768 \ 1769 local_irq_save(flags); \ 1770 omt = __dmt(); \ 1771 res = read_c0_##name(); \ 1772 new = res & ~clear; \ 1773 write_c0_##name(new); \ 1774 __emt(omt); \ 1775 local_irq_restore(flags); \ 1776 \ 1777 return res; \ 1778 } \ 1779 \ 1780 static inline unsigned int \ 1781 change_c0_##name(unsigned int change, unsigned int newbits) \ 1782 { \ 1783 unsigned int res; \ 1784 unsigned int new; \ 1785 unsigned int omt; \ 1786 unsigned long flags; \ 1787 \ 1788 local_irq_save(flags); \ 1789 \ 1790 omt = __dmt(); \ 1791 res = read_c0_##name(); \ 1792 new = res & ~change; \ 1793 new |= (newbits & change); \ 1794 write_c0_##name(new); \ 1795 __emt(omt); \ 1796 local_irq_restore(flags); \ 1797 \ 1798 return res; \ 1799 } 1800 #endif 1801 1802 __BUILD_SET_C0(status) 1803 __BUILD_SET_C0(cause) 1804 __BUILD_SET_C0(config) 1805 __BUILD_SET_C0(intcontrol) 1806 __BUILD_SET_C0(intctl) 1807 __BUILD_SET_C0(srsmap) 1808 __BUILD_SET_C0(brcm_config_0) 1809 __BUILD_SET_C0(brcm_bus_pll) 1810 __BUILD_SET_C0(brcm_reset) 1811 __BUILD_SET_C0(brcm_cmt_intr) 1812 __BUILD_SET_C0(brcm_cmt_ctrl) 1813 __BUILD_SET_C0(brcm_config) 1814 __BUILD_SET_C0(brcm_mode) 1815 1816 #endif /* !__ASSEMBLY__ */ 1817 1818 #endif /* _ASM_MIPSREGS_H */ 1819