1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <asm/hazards.h> 18 #include <asm/war.h> 19 20 /* 21 * The following macros are especially useful for __asm__ 22 * inline assembler. 23 */ 24 #ifndef __STR 25 #define __STR(x) #x 26 #endif 27 #ifndef STR 28 #define STR(x) __STR(x) 29 #endif 30 31 /* 32 * Configure language 33 */ 34 #ifdef __ASSEMBLY__ 35 #define _ULCAST_ 36 #else 37 #define _ULCAST_ (unsigned long) 38 #endif 39 40 /* 41 * Coprocessor 0 register names 42 */ 43 #define CP0_INDEX $0 44 #define CP0_RANDOM $1 45 #define CP0_ENTRYLO0 $2 46 #define CP0_ENTRYLO1 $3 47 #define CP0_CONF $3 48 #define CP0_CONTEXT $4 49 #define CP0_PAGEMASK $5 50 #define CP0_WIRED $6 51 #define CP0_INFO $7 52 #define CP0_BADVADDR $8 53 #define CP0_COUNT $9 54 #define CP0_ENTRYHI $10 55 #define CP0_COMPARE $11 56 #define CP0_STATUS $12 57 #define CP0_CAUSE $13 58 #define CP0_EPC $14 59 #define CP0_PRID $15 60 #define CP0_CONFIG $16 61 #define CP0_LLADDR $17 62 #define CP0_WATCHLO $18 63 #define CP0_WATCHHI $19 64 #define CP0_XCONTEXT $20 65 #define CP0_FRAMEMASK $21 66 #define CP0_DIAGNOSTIC $22 67 #define CP0_DEBUG $23 68 #define CP0_DEPC $24 69 #define CP0_PERFORMANCE $25 70 #define CP0_ECC $26 71 #define CP0_CACHEERR $27 72 #define CP0_TAGLO $28 73 #define CP0_TAGHI $29 74 #define CP0_ERROREPC $30 75 #define CP0_DESAVE $31 76 77 /* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83 #define CP0_IBASE $0 84 #define CP0_IBOUND $1 85 #define CP0_DBASE $2 86 #define CP0_DBOUND $3 87 #define CP0_CALG $17 88 #define CP0_IWATCH $18 89 #define CP0_DWATCH $19 90 91 /* 92 * Coprocessor 0 Set 1 register names 93 */ 94 #define CP0_S1_DERRADDR0 $26 95 #define CP0_S1_DERRADDR1 $27 96 #define CP0_S1_INTCONTROL $20 97 98 /* 99 * Coprocessor 0 Set 2 register names 100 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103 /* 104 * Coprocessor 0 Set 3 register names 105 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108 /* 109 * TX39 Series 110 */ 111 #define CP0_TX39_CACHE $7 112 113 /* 114 * Coprocessor 1 (FPU) register names 115 */ 116 #define CP1_REVISION $0 117 #define CP1_STATUS $31 118 119 /* 120 * FPU Status Register Values 121 */ 122 /* 123 * Status Register Values 124 */ 125 126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 136 137 /* 138 * Bits 18 - 20 of the FPU Status Register will be read as 0, 139 * and should be written as zero. 140 */ 141 #define FPU_CSR_RSVD 0x001c0000 142 143 /* 144 * X the exception cause indicator 145 * E the exception enable 146 * S the sticky/flag bit 147 */ 148 #define FPU_CSR_ALL_X 0x0003f000 149 #define FPU_CSR_UNI_X 0x00020000 150 #define FPU_CSR_INV_X 0x00010000 151 #define FPU_CSR_DIV_X 0x00008000 152 #define FPU_CSR_OVF_X 0x00004000 153 #define FPU_CSR_UDF_X 0x00002000 154 #define FPU_CSR_INE_X 0x00001000 155 156 #define FPU_CSR_ALL_E 0x00000f80 157 #define FPU_CSR_INV_E 0x00000800 158 #define FPU_CSR_DIV_E 0x00000400 159 #define FPU_CSR_OVF_E 0x00000200 160 #define FPU_CSR_UDF_E 0x00000100 161 #define FPU_CSR_INE_E 0x00000080 162 163 #define FPU_CSR_ALL_S 0x0000007c 164 #define FPU_CSR_INV_S 0x00000040 165 #define FPU_CSR_DIV_S 0x00000020 166 #define FPU_CSR_OVF_S 0x00000010 167 #define FPU_CSR_UDF_S 0x00000008 168 #define FPU_CSR_INE_S 0x00000004 169 170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 171 #define FPU_CSR_RM 0x00000003 172 #define FPU_CSR_RN 0x0 /* nearest */ 173 #define FPU_CSR_RZ 0x1 /* towards zero */ 174 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 175 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 176 177 178 /* 179 * Values for PageMask register 180 */ 181 #ifdef CONFIG_CPU_VR41XX 182 183 /* Why doesn't stupidity hurt ... */ 184 185 #define PM_1K 0x00000000 186 #define PM_4K 0x00001800 187 #define PM_16K 0x00007800 188 #define PM_64K 0x0001f800 189 #define PM_256K 0x0007f800 190 191 #else 192 193 #define PM_4K 0x00000000 194 #define PM_8K 0x00002000 195 #define PM_16K 0x00006000 196 #define PM_32K 0x0000e000 197 #define PM_64K 0x0001e000 198 #define PM_128K 0x0003e000 199 #define PM_256K 0x0007e000 200 #define PM_512K 0x000fe000 201 #define PM_1M 0x001fe000 202 #define PM_2M 0x003fe000 203 #define PM_4M 0x007fe000 204 #define PM_8M 0x00ffe000 205 #define PM_16M 0x01ffe000 206 #define PM_32M 0x03ffe000 207 #define PM_64M 0x07ffe000 208 #define PM_256M 0x1fffe000 209 #define PM_1G 0x7fffe000 210 211 #endif 212 213 /* 214 * Default page size for a given kernel configuration 215 */ 216 #ifdef CONFIG_PAGE_SIZE_4KB 217 #define PM_DEFAULT_MASK PM_4K 218 #elif defined(CONFIG_PAGE_SIZE_8KB) 219 #define PM_DEFAULT_MASK PM_8K 220 #elif defined(CONFIG_PAGE_SIZE_16KB) 221 #define PM_DEFAULT_MASK PM_16K 222 #elif defined(CONFIG_PAGE_SIZE_32KB) 223 #define PM_DEFAULT_MASK PM_32K 224 #elif defined(CONFIG_PAGE_SIZE_64KB) 225 #define PM_DEFAULT_MASK PM_64K 226 #else 227 #error Bad page size configuration! 228 #endif 229 230 /* 231 * Default huge tlb size for a given kernel configuration 232 */ 233 #ifdef CONFIG_PAGE_SIZE_4KB 234 #define PM_HUGE_MASK PM_1M 235 #elif defined(CONFIG_PAGE_SIZE_8KB) 236 #define PM_HUGE_MASK PM_4M 237 #elif defined(CONFIG_PAGE_SIZE_16KB) 238 #define PM_HUGE_MASK PM_16M 239 #elif defined(CONFIG_PAGE_SIZE_32KB) 240 #define PM_HUGE_MASK PM_64M 241 #elif defined(CONFIG_PAGE_SIZE_64KB) 242 #define PM_HUGE_MASK PM_256M 243 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 244 #error Bad page size configuration for hugetlbfs! 245 #endif 246 247 /* 248 * Values used for computation of new tlb entries 249 */ 250 #define PL_4K 12 251 #define PL_16K 14 252 #define PL_64K 16 253 #define PL_256K 18 254 #define PL_1M 20 255 #define PL_4M 22 256 #define PL_16M 24 257 #define PL_64M 26 258 #define PL_256M 28 259 260 /* 261 * PageGrain bits 262 */ 263 #define PG_RIE (_ULCAST_(1) << 31) 264 #define PG_XIE (_ULCAST_(1) << 30) 265 #define PG_ELPA (_ULCAST_(1) << 29) 266 #define PG_ESP (_ULCAST_(1) << 28) 267 268 /* 269 * R4x00 interrupt enable / cause bits 270 */ 271 #define IE_SW0 (_ULCAST_(1) << 8) 272 #define IE_SW1 (_ULCAST_(1) << 9) 273 #define IE_IRQ0 (_ULCAST_(1) << 10) 274 #define IE_IRQ1 (_ULCAST_(1) << 11) 275 #define IE_IRQ2 (_ULCAST_(1) << 12) 276 #define IE_IRQ3 (_ULCAST_(1) << 13) 277 #define IE_IRQ4 (_ULCAST_(1) << 14) 278 #define IE_IRQ5 (_ULCAST_(1) << 15) 279 280 /* 281 * R4x00 interrupt cause bits 282 */ 283 #define C_SW0 (_ULCAST_(1) << 8) 284 #define C_SW1 (_ULCAST_(1) << 9) 285 #define C_IRQ0 (_ULCAST_(1) << 10) 286 #define C_IRQ1 (_ULCAST_(1) << 11) 287 #define C_IRQ2 (_ULCAST_(1) << 12) 288 #define C_IRQ3 (_ULCAST_(1) << 13) 289 #define C_IRQ4 (_ULCAST_(1) << 14) 290 #define C_IRQ5 (_ULCAST_(1) << 15) 291 292 /* 293 * Bitfields in the R4xx0 cp0 status register 294 */ 295 #define ST0_IE 0x00000001 296 #define ST0_EXL 0x00000002 297 #define ST0_ERL 0x00000004 298 #define ST0_KSU 0x00000018 299 # define KSU_USER 0x00000010 300 # define KSU_SUPERVISOR 0x00000008 301 # define KSU_KERNEL 0x00000000 302 #define ST0_UX 0x00000020 303 #define ST0_SX 0x00000040 304 #define ST0_KX 0x00000080 305 #define ST0_DE 0x00010000 306 #define ST0_CE 0x00020000 307 308 /* 309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 310 * cacheops in userspace. This bit exists only on RM7000 and RM9000 311 * processors. 312 */ 313 #define ST0_CO 0x08000000 314 315 /* 316 * Bitfields in the R[23]000 cp0 status register. 317 */ 318 #define ST0_IEC 0x00000001 319 #define ST0_KUC 0x00000002 320 #define ST0_IEP 0x00000004 321 #define ST0_KUP 0x00000008 322 #define ST0_IEO 0x00000010 323 #define ST0_KUO 0x00000020 324 /* bits 6 & 7 are reserved on R[23]000 */ 325 #define ST0_ISC 0x00010000 326 #define ST0_SWC 0x00020000 327 #define ST0_CM 0x00080000 328 329 /* 330 * Bits specific to the R4640/R4650 331 */ 332 #define ST0_UM (_ULCAST_(1) << 4) 333 #define ST0_IL (_ULCAST_(1) << 23) 334 #define ST0_DL (_ULCAST_(1) << 24) 335 336 /* 337 * Enable the MIPS MDMX and DSP ASEs 338 */ 339 #define ST0_MX 0x01000000 340 341 /* 342 * Bitfields in the TX39 family CP0 Configuration Register 3 343 */ 344 #define TX39_CONF_ICS_SHIFT 19 345 #define TX39_CONF_ICS_MASK 0x00380000 346 #define TX39_CONF_ICS_1KB 0x00000000 347 #define TX39_CONF_ICS_2KB 0x00080000 348 #define TX39_CONF_ICS_4KB 0x00100000 349 #define TX39_CONF_ICS_8KB 0x00180000 350 #define TX39_CONF_ICS_16KB 0x00200000 351 352 #define TX39_CONF_DCS_SHIFT 16 353 #define TX39_CONF_DCS_MASK 0x00070000 354 #define TX39_CONF_DCS_1KB 0x00000000 355 #define TX39_CONF_DCS_2KB 0x00010000 356 #define TX39_CONF_DCS_4KB 0x00020000 357 #define TX39_CONF_DCS_8KB 0x00030000 358 #define TX39_CONF_DCS_16KB 0x00040000 359 360 #define TX39_CONF_CWFON 0x00004000 361 #define TX39_CONF_WBON 0x00002000 362 #define TX39_CONF_RF_SHIFT 10 363 #define TX39_CONF_RF_MASK 0x00000c00 364 #define TX39_CONF_DOZE 0x00000200 365 #define TX39_CONF_HALT 0x00000100 366 #define TX39_CONF_LOCK 0x00000080 367 #define TX39_CONF_ICE 0x00000020 368 #define TX39_CONF_DCE 0x00000010 369 #define TX39_CONF_IRSIZE_SHIFT 2 370 #define TX39_CONF_IRSIZE_MASK 0x0000000c 371 #define TX39_CONF_DRSIZE_SHIFT 0 372 #define TX39_CONF_DRSIZE_MASK 0x00000003 373 374 /* 375 * Status register bits available in all MIPS CPUs. 376 */ 377 #define ST0_IM 0x0000ff00 378 #define STATUSB_IP0 8 379 #define STATUSF_IP0 (_ULCAST_(1) << 8) 380 #define STATUSB_IP1 9 381 #define STATUSF_IP1 (_ULCAST_(1) << 9) 382 #define STATUSB_IP2 10 383 #define STATUSF_IP2 (_ULCAST_(1) << 10) 384 #define STATUSB_IP3 11 385 #define STATUSF_IP3 (_ULCAST_(1) << 11) 386 #define STATUSB_IP4 12 387 #define STATUSF_IP4 (_ULCAST_(1) << 12) 388 #define STATUSB_IP5 13 389 #define STATUSF_IP5 (_ULCAST_(1) << 13) 390 #define STATUSB_IP6 14 391 #define STATUSF_IP6 (_ULCAST_(1) << 14) 392 #define STATUSB_IP7 15 393 #define STATUSF_IP7 (_ULCAST_(1) << 15) 394 #define STATUSB_IP8 0 395 #define STATUSF_IP8 (_ULCAST_(1) << 0) 396 #define STATUSB_IP9 1 397 #define STATUSF_IP9 (_ULCAST_(1) << 1) 398 #define STATUSB_IP10 2 399 #define STATUSF_IP10 (_ULCAST_(1) << 2) 400 #define STATUSB_IP11 3 401 #define STATUSF_IP11 (_ULCAST_(1) << 3) 402 #define STATUSB_IP12 4 403 #define STATUSF_IP12 (_ULCAST_(1) << 4) 404 #define STATUSB_IP13 5 405 #define STATUSF_IP13 (_ULCAST_(1) << 5) 406 #define STATUSB_IP14 6 407 #define STATUSF_IP14 (_ULCAST_(1) << 6) 408 #define STATUSB_IP15 7 409 #define STATUSF_IP15 (_ULCAST_(1) << 7) 410 #define ST0_CH 0x00040000 411 #define ST0_NMI 0x00080000 412 #define ST0_SR 0x00100000 413 #define ST0_TS 0x00200000 414 #define ST0_BEV 0x00400000 415 #define ST0_RE 0x02000000 416 #define ST0_FR 0x04000000 417 #define ST0_CU 0xf0000000 418 #define ST0_CU0 0x10000000 419 #define ST0_CU1 0x20000000 420 #define ST0_CU2 0x40000000 421 #define ST0_CU3 0x80000000 422 #define ST0_XX 0x80000000 /* MIPS IV naming */ 423 424 /* 425 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 426 * 427 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 428 */ 429 #define INTCTLB_IPPCI 26 430 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 431 #define INTCTLB_IPTI 29 432 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 433 434 /* 435 * Bitfields and bit numbers in the coprocessor 0 cause register. 436 * 437 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 438 */ 439 #define CAUSEB_EXCCODE 2 440 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 441 #define CAUSEB_IP 8 442 #define CAUSEF_IP (_ULCAST_(255) << 8) 443 #define CAUSEB_IP0 8 444 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 445 #define CAUSEB_IP1 9 446 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 447 #define CAUSEB_IP2 10 448 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 449 #define CAUSEB_IP3 11 450 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 451 #define CAUSEB_IP4 12 452 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 453 #define CAUSEB_IP5 13 454 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 455 #define CAUSEB_IP6 14 456 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 457 #define CAUSEB_IP7 15 458 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 459 #define CAUSEB_IV 23 460 #define CAUSEF_IV (_ULCAST_(1) << 23) 461 #define CAUSEB_PCI 26 462 #define CAUSEF_PCI (_ULCAST_(1) << 26) 463 #define CAUSEB_CE 28 464 #define CAUSEF_CE (_ULCAST_(3) << 28) 465 #define CAUSEB_TI 30 466 #define CAUSEF_TI (_ULCAST_(1) << 30) 467 #define CAUSEB_BD 31 468 #define CAUSEF_BD (_ULCAST_(1) << 31) 469 470 /* 471 * Bits in the coprocessor 0 config register. 472 */ 473 /* Generic bits. */ 474 #define CONF_CM_CACHABLE_NO_WA 0 475 #define CONF_CM_CACHABLE_WA 1 476 #define CONF_CM_UNCACHED 2 477 #define CONF_CM_CACHABLE_NONCOHERENT 3 478 #define CONF_CM_CACHABLE_CE 4 479 #define CONF_CM_CACHABLE_COW 5 480 #define CONF_CM_CACHABLE_CUW 6 481 #define CONF_CM_CACHABLE_ACCELERATED 7 482 #define CONF_CM_CMASK 7 483 #define CONF_BE (_ULCAST_(1) << 15) 484 485 /* Bits common to various processors. */ 486 #define CONF_CU (_ULCAST_(1) << 3) 487 #define CONF_DB (_ULCAST_(1) << 4) 488 #define CONF_IB (_ULCAST_(1) << 5) 489 #define CONF_DC (_ULCAST_(7) << 6) 490 #define CONF_IC (_ULCAST_(7) << 9) 491 #define CONF_EB (_ULCAST_(1) << 13) 492 #define CONF_EM (_ULCAST_(1) << 14) 493 #define CONF_SM (_ULCAST_(1) << 16) 494 #define CONF_SC (_ULCAST_(1) << 17) 495 #define CONF_EW (_ULCAST_(3) << 18) 496 #define CONF_EP (_ULCAST_(15)<< 24) 497 #define CONF_EC (_ULCAST_(7) << 28) 498 #define CONF_CM (_ULCAST_(1) << 31) 499 500 /* Bits specific to the R4xx0. */ 501 #define R4K_CONF_SW (_ULCAST_(1) << 20) 502 #define R4K_CONF_SS (_ULCAST_(1) << 21) 503 #define R4K_CONF_SB (_ULCAST_(3) << 22) 504 505 /* Bits specific to the R5000. */ 506 #define R5K_CONF_SE (_ULCAST_(1) << 12) 507 #define R5K_CONF_SS (_ULCAST_(3) << 20) 508 509 /* Bits specific to the RM7000. */ 510 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 511 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 512 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 513 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 514 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 515 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 516 517 /* Bits specific to the R10000. */ 518 #define R10K_CONF_DN (_ULCAST_(3) << 3) 519 #define R10K_CONF_CT (_ULCAST_(1) << 5) 520 #define R10K_CONF_PE (_ULCAST_(1) << 6) 521 #define R10K_CONF_PM (_ULCAST_(3) << 7) 522 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 523 #define R10K_CONF_SB (_ULCAST_(1) << 13) 524 #define R10K_CONF_SK (_ULCAST_(1) << 14) 525 #define R10K_CONF_SS (_ULCAST_(7) << 16) 526 #define R10K_CONF_SC (_ULCAST_(7) << 19) 527 #define R10K_CONF_DC (_ULCAST_(7) << 26) 528 #define R10K_CONF_IC (_ULCAST_(7) << 29) 529 530 /* Bits specific to the VR41xx. */ 531 #define VR41_CONF_CS (_ULCAST_(1) << 12) 532 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 533 #define VR41_CONF_BP (_ULCAST_(1) << 16) 534 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 535 #define VR41_CONF_AD (_ULCAST_(1) << 23) 536 537 /* Bits specific to the R30xx. */ 538 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 539 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 540 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 541 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 542 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 543 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 544 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 545 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 546 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 547 548 /* Bits specific to the TX49. */ 549 #define TX49_CONF_DC (_ULCAST_(1) << 16) 550 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 551 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 552 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 553 554 /* Bits specific to the MIPS32/64 PRA. */ 555 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 556 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 557 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 558 #define MIPS_CONF_M (_ULCAST_(1) << 31) 559 560 /* 561 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 562 */ 563 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 564 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 565 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 566 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 567 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 568 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 569 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 570 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 571 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 572 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 573 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 574 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 575 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 576 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 577 578 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 579 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 580 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 581 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 582 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 583 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 584 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 585 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 586 587 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 588 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 589 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 590 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 591 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 592 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 593 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 594 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 595 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 596 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 597 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 598 599 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 600 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 601 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 602 603 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 604 605 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 606 607 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 608 609 610 /* 611 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 612 */ 613 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 614 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 615 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 616 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 617 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 618 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 619 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 620 621 #ifndef __ASSEMBLY__ 622 623 /* 624 * Functions to access the R10000 performance counters. These are basically 625 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 626 * performance counter number encoded into bits 1 ... 5 of the instruction. 627 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 628 * disassembler these will look like an access to sel 0 or 1. 629 */ 630 #define read_r10k_perf_cntr(counter) \ 631 ({ \ 632 unsigned int __res; \ 633 __asm__ __volatile__( \ 634 "mfpc\t%0, %1" \ 635 : "=r" (__res) \ 636 : "i" (counter)); \ 637 \ 638 __res; \ 639 }) 640 641 #define write_r10k_perf_cntr(counter,val) \ 642 do { \ 643 __asm__ __volatile__( \ 644 "mtpc\t%0, %1" \ 645 : \ 646 : "r" (val), "i" (counter)); \ 647 } while (0) 648 649 #define read_r10k_perf_event(counter) \ 650 ({ \ 651 unsigned int __res; \ 652 __asm__ __volatile__( \ 653 "mfps\t%0, %1" \ 654 : "=r" (__res) \ 655 : "i" (counter)); \ 656 \ 657 __res; \ 658 }) 659 660 #define write_r10k_perf_cntl(counter,val) \ 661 do { \ 662 __asm__ __volatile__( \ 663 "mtps\t%0, %1" \ 664 : \ 665 : "r" (val), "i" (counter)); \ 666 } while (0) 667 668 669 /* 670 * Macros to access the system control coprocessor 671 */ 672 673 #define __read_32bit_c0_register(source, sel) \ 674 ({ int __res; \ 675 if (sel == 0) \ 676 __asm__ __volatile__( \ 677 "mfc0\t%0, " #source "\n\t" \ 678 : "=r" (__res)); \ 679 else \ 680 __asm__ __volatile__( \ 681 ".set\tmips32\n\t" \ 682 "mfc0\t%0, " #source ", " #sel "\n\t" \ 683 ".set\tmips0\n\t" \ 684 : "=r" (__res)); \ 685 __res; \ 686 }) 687 688 #define __read_64bit_c0_register(source, sel) \ 689 ({ unsigned long long __res; \ 690 if (sizeof(unsigned long) == 4) \ 691 __res = __read_64bit_c0_split(source, sel); \ 692 else if (sel == 0) \ 693 __asm__ __volatile__( \ 694 ".set\tmips3\n\t" \ 695 "dmfc0\t%0, " #source "\n\t" \ 696 ".set\tmips0" \ 697 : "=r" (__res)); \ 698 else \ 699 __asm__ __volatile__( \ 700 ".set\tmips64\n\t" \ 701 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 702 ".set\tmips0" \ 703 : "=r" (__res)); \ 704 __res; \ 705 }) 706 707 #define __write_32bit_c0_register(register, sel, value) \ 708 do { \ 709 if (sel == 0) \ 710 __asm__ __volatile__( \ 711 "mtc0\t%z0, " #register "\n\t" \ 712 : : "Jr" ((unsigned int)(value))); \ 713 else \ 714 __asm__ __volatile__( \ 715 ".set\tmips32\n\t" \ 716 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 717 ".set\tmips0" \ 718 : : "Jr" ((unsigned int)(value))); \ 719 } while (0) 720 721 #define __write_64bit_c0_register(register, sel, value) \ 722 do { \ 723 if (sizeof(unsigned long) == 4) \ 724 __write_64bit_c0_split(register, sel, value); \ 725 else if (sel == 0) \ 726 __asm__ __volatile__( \ 727 ".set\tmips3\n\t" \ 728 "dmtc0\t%z0, " #register "\n\t" \ 729 ".set\tmips0" \ 730 : : "Jr" (value)); \ 731 else \ 732 __asm__ __volatile__( \ 733 ".set\tmips64\n\t" \ 734 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 735 ".set\tmips0" \ 736 : : "Jr" (value)); \ 737 } while (0) 738 739 #define __read_ulong_c0_register(reg, sel) \ 740 ((sizeof(unsigned long) == 4) ? \ 741 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 742 (unsigned long) __read_64bit_c0_register(reg, sel)) 743 744 #define __write_ulong_c0_register(reg, sel, val) \ 745 do { \ 746 if (sizeof(unsigned long) == 4) \ 747 __write_32bit_c0_register(reg, sel, val); \ 748 else \ 749 __write_64bit_c0_register(reg, sel, val); \ 750 } while (0) 751 752 /* 753 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 754 */ 755 #define __read_32bit_c0_ctrl_register(source) \ 756 ({ int __res; \ 757 __asm__ __volatile__( \ 758 "cfc0\t%0, " #source "\n\t" \ 759 : "=r" (__res)); \ 760 __res; \ 761 }) 762 763 #define __write_32bit_c0_ctrl_register(register, value) \ 764 do { \ 765 __asm__ __volatile__( \ 766 "ctc0\t%z0, " #register "\n\t" \ 767 : : "Jr" ((unsigned int)(value))); \ 768 } while (0) 769 770 /* 771 * These versions are only needed for systems with more than 38 bits of 772 * physical address space running the 32-bit kernel. That's none atm :-) 773 */ 774 #define __read_64bit_c0_split(source, sel) \ 775 ({ \ 776 unsigned long long __val; \ 777 unsigned long __flags; \ 778 \ 779 local_irq_save(__flags); \ 780 if (sel == 0) \ 781 __asm__ __volatile__( \ 782 ".set\tmips64\n\t" \ 783 "dmfc0\t%M0, " #source "\n\t" \ 784 "dsll\t%L0, %M0, 32\n\t" \ 785 "dsra\t%M0, %M0, 32\n\t" \ 786 "dsra\t%L0, %L0, 32\n\t" \ 787 ".set\tmips0" \ 788 : "=r" (__val)); \ 789 else \ 790 __asm__ __volatile__( \ 791 ".set\tmips64\n\t" \ 792 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 793 "dsll\t%L0, %M0, 32\n\t" \ 794 "dsra\t%M0, %M0, 32\n\t" \ 795 "dsra\t%L0, %L0, 32\n\t" \ 796 ".set\tmips0" \ 797 : "=r" (__val)); \ 798 local_irq_restore(__flags); \ 799 \ 800 __val; \ 801 }) 802 803 #define __write_64bit_c0_split(source, sel, val) \ 804 do { \ 805 unsigned long __flags; \ 806 \ 807 local_irq_save(__flags); \ 808 if (sel == 0) \ 809 __asm__ __volatile__( \ 810 ".set\tmips64\n\t" \ 811 "dsll\t%L0, %L0, 32\n\t" \ 812 "dsrl\t%L0, %L0, 32\n\t" \ 813 "dsll\t%M0, %M0, 32\n\t" \ 814 "or\t%L0, %L0, %M0\n\t" \ 815 "dmtc0\t%L0, " #source "\n\t" \ 816 ".set\tmips0" \ 817 : : "r" (val)); \ 818 else \ 819 __asm__ __volatile__( \ 820 ".set\tmips64\n\t" \ 821 "dsll\t%L0, %L0, 32\n\t" \ 822 "dsrl\t%L0, %L0, 32\n\t" \ 823 "dsll\t%M0, %M0, 32\n\t" \ 824 "or\t%L0, %L0, %M0\n\t" \ 825 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 826 ".set\tmips0" \ 827 : : "r" (val)); \ 828 local_irq_restore(__flags); \ 829 } while (0) 830 831 #define read_c0_index() __read_32bit_c0_register($0, 0) 832 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 833 834 #define read_c0_random() __read_32bit_c0_register($1, 0) 835 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 836 837 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 838 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 839 840 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 841 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 842 843 #define read_c0_conf() __read_32bit_c0_register($3, 0) 844 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 845 846 #define read_c0_context() __read_ulong_c0_register($4, 0) 847 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 848 849 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 850 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 851 852 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 853 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 854 855 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 856 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 857 858 #define read_c0_wired() __read_32bit_c0_register($6, 0) 859 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 860 861 #define read_c0_info() __read_32bit_c0_register($7, 0) 862 863 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 864 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 865 866 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 867 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 868 869 #define read_c0_count() __read_32bit_c0_register($9, 0) 870 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 871 872 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 873 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 874 875 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 876 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 877 878 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 879 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 880 881 #define read_c0_compare() __read_32bit_c0_register($11, 0) 882 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 883 884 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 885 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 886 887 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 888 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 889 890 #define read_c0_status() __read_32bit_c0_register($12, 0) 891 #ifdef CONFIG_MIPS_MT_SMTC 892 #define write_c0_status(val) \ 893 do { \ 894 __write_32bit_c0_register($12, 0, val); \ 895 __ehb(); \ 896 } while (0) 897 #else 898 /* 899 * Legacy non-SMTC code, which may be hazardous 900 * but which might not support EHB 901 */ 902 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 903 #endif /* CONFIG_MIPS_MT_SMTC */ 904 905 #define read_c0_cause() __read_32bit_c0_register($13, 0) 906 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 907 908 #define read_c0_epc() __read_ulong_c0_register($14, 0) 909 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 910 911 #define read_c0_prid() __read_32bit_c0_register($15, 0) 912 913 #define read_c0_config() __read_32bit_c0_register($16, 0) 914 #define read_c0_config1() __read_32bit_c0_register($16, 1) 915 #define read_c0_config2() __read_32bit_c0_register($16, 2) 916 #define read_c0_config3() __read_32bit_c0_register($16, 3) 917 #define read_c0_config4() __read_32bit_c0_register($16, 4) 918 #define read_c0_config5() __read_32bit_c0_register($16, 5) 919 #define read_c0_config6() __read_32bit_c0_register($16, 6) 920 #define read_c0_config7() __read_32bit_c0_register($16, 7) 921 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 922 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 923 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 924 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 925 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 926 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 927 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 928 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 929 930 /* 931 * The WatchLo register. There may be up to 8 of them. 932 */ 933 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 934 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 935 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 936 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 937 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 938 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 939 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 940 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 941 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 942 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 943 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 944 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 945 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 946 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 947 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 948 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 949 950 /* 951 * The WatchHi register. There may be up to 8 of them. 952 */ 953 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 954 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 955 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 956 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 957 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 958 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 959 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 960 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 961 962 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 963 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 964 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 965 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 966 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 967 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 968 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 969 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 970 971 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 972 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 973 974 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 975 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 976 977 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 978 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 979 980 #define read_c0_diag() __read_32bit_c0_register($22, 0) 981 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 982 983 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 984 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 985 986 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 987 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 988 989 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 990 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 991 992 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 993 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 994 995 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 996 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 997 998 #define read_c0_debug() __read_32bit_c0_register($23, 0) 999 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1000 1001 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1002 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1003 1004 /* 1005 * MIPS32 / MIPS64 performance counters 1006 */ 1007 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1008 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1009 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1010 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1011 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1012 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1013 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1014 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1015 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1016 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1017 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1018 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1019 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1020 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1021 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1022 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1023 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1024 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1025 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1026 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1027 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1028 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1029 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1030 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1031 1032 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1033 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1034 1035 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1036 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1037 1038 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1039 1040 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1041 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1042 1043 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1044 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1045 1046 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1047 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1048 1049 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1050 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1051 1052 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1053 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1054 1055 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1056 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1057 1058 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1059 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1060 1061 /* MIPSR2 */ 1062 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1063 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1064 1065 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1066 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1067 1068 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1069 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1070 1071 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1072 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1073 1074 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1075 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1076 1077 1078 /* Cavium OCTEON (cnMIPS) */ 1079 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1080 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1081 1082 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1083 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1084 1085 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1086 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1087 /* 1088 * The cacheerr registers are not standardized. On OCTEON, they are 1089 * 64 bits wide. 1090 */ 1091 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1092 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1093 1094 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1095 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1096 1097 /* BMIPS3300 */ 1098 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1099 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1100 1101 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1102 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1103 1104 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1105 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1106 1107 /* BMIPS43xx */ 1108 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1109 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1110 1111 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1112 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1113 1114 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1115 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1116 1117 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1118 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1119 1120 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1121 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1122 1123 /* BMIPS5000 */ 1124 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1125 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1126 1127 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1128 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1129 1130 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1131 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1132 1133 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1134 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1135 1136 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1137 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1138 1139 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1140 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1141 1142 /* 1143 * Macros to access the floating point coprocessor control registers 1144 */ 1145 #define read_32bit_cp1_register(source) \ 1146 ({ int __res; \ 1147 __asm__ __volatile__( \ 1148 ".set\tpush\n\t" \ 1149 ".set\treorder\n\t" \ 1150 /* gas fails to assemble cfc1 for some archs (octeon).*/ \ 1151 ".set\tmips1\n\t" \ 1152 "cfc1\t%0,"STR(source)"\n\t" \ 1153 ".set\tpop" \ 1154 : "=r" (__res)); \ 1155 __res;}) 1156 1157 #define rddsp(mask) \ 1158 ({ \ 1159 unsigned int __res; \ 1160 \ 1161 __asm__ __volatile__( \ 1162 " .set push \n" \ 1163 " .set noat \n" \ 1164 " # rddsp $1, %x1 \n" \ 1165 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1166 " move %0, $1 \n" \ 1167 " .set pop \n" \ 1168 : "=r" (__res) \ 1169 : "i" (mask)); \ 1170 __res; \ 1171 }) 1172 1173 #define wrdsp(val, mask) \ 1174 do { \ 1175 __asm__ __volatile__( \ 1176 " .set push \n" \ 1177 " .set noat \n" \ 1178 " move $1, %0 \n" \ 1179 " # wrdsp $1, %x1 \n" \ 1180 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1181 " .set pop \n" \ 1182 : \ 1183 : "r" (val), "i" (mask)); \ 1184 } while (0) 1185 1186 #if 0 /* Need DSP ASE capable assembler ... */ 1187 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1188 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1189 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1190 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) 1191 1192 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) 1193 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) 1194 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) 1195 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) 1196 1197 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) 1198 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) 1199 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) 1200 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) 1201 1202 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) 1203 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) 1204 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) 1205 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) 1206 1207 #else 1208 1209 #define mfhi0() \ 1210 ({ \ 1211 unsigned long __treg; \ 1212 \ 1213 __asm__ __volatile__( \ 1214 " .set push \n" \ 1215 " .set noat \n" \ 1216 " # mfhi %0, $ac0 \n" \ 1217 " .word 0x00000810 \n" \ 1218 " move %0, $1 \n" \ 1219 " .set pop \n" \ 1220 : "=r" (__treg)); \ 1221 __treg; \ 1222 }) 1223 1224 #define mfhi1() \ 1225 ({ \ 1226 unsigned long __treg; \ 1227 \ 1228 __asm__ __volatile__( \ 1229 " .set push \n" \ 1230 " .set noat \n" \ 1231 " # mfhi %0, $ac1 \n" \ 1232 " .word 0x00200810 \n" \ 1233 " move %0, $1 \n" \ 1234 " .set pop \n" \ 1235 : "=r" (__treg)); \ 1236 __treg; \ 1237 }) 1238 1239 #define mfhi2() \ 1240 ({ \ 1241 unsigned long __treg; \ 1242 \ 1243 __asm__ __volatile__( \ 1244 " .set push \n" \ 1245 " .set noat \n" \ 1246 " # mfhi %0, $ac2 \n" \ 1247 " .word 0x00400810 \n" \ 1248 " move %0, $1 \n" \ 1249 " .set pop \n" \ 1250 : "=r" (__treg)); \ 1251 __treg; \ 1252 }) 1253 1254 #define mfhi3() \ 1255 ({ \ 1256 unsigned long __treg; \ 1257 \ 1258 __asm__ __volatile__( \ 1259 " .set push \n" \ 1260 " .set noat \n" \ 1261 " # mfhi %0, $ac3 \n" \ 1262 " .word 0x00600810 \n" \ 1263 " move %0, $1 \n" \ 1264 " .set pop \n" \ 1265 : "=r" (__treg)); \ 1266 __treg; \ 1267 }) 1268 1269 #define mflo0() \ 1270 ({ \ 1271 unsigned long __treg; \ 1272 \ 1273 __asm__ __volatile__( \ 1274 " .set push \n" \ 1275 " .set noat \n" \ 1276 " # mflo %0, $ac0 \n" \ 1277 " .word 0x00000812 \n" \ 1278 " move %0, $1 \n" \ 1279 " .set pop \n" \ 1280 : "=r" (__treg)); \ 1281 __treg; \ 1282 }) 1283 1284 #define mflo1() \ 1285 ({ \ 1286 unsigned long __treg; \ 1287 \ 1288 __asm__ __volatile__( \ 1289 " .set push \n" \ 1290 " .set noat \n" \ 1291 " # mflo %0, $ac1 \n" \ 1292 " .word 0x00200812 \n" \ 1293 " move %0, $1 \n" \ 1294 " .set pop \n" \ 1295 : "=r" (__treg)); \ 1296 __treg; \ 1297 }) 1298 1299 #define mflo2() \ 1300 ({ \ 1301 unsigned long __treg; \ 1302 \ 1303 __asm__ __volatile__( \ 1304 " .set push \n" \ 1305 " .set noat \n" \ 1306 " # mflo %0, $ac2 \n" \ 1307 " .word 0x00400812 \n" \ 1308 " move %0, $1 \n" \ 1309 " .set pop \n" \ 1310 : "=r" (__treg)); \ 1311 __treg; \ 1312 }) 1313 1314 #define mflo3() \ 1315 ({ \ 1316 unsigned long __treg; \ 1317 \ 1318 __asm__ __volatile__( \ 1319 " .set push \n" \ 1320 " .set noat \n" \ 1321 " # mflo %0, $ac3 \n" \ 1322 " .word 0x00600812 \n" \ 1323 " move %0, $1 \n" \ 1324 " .set pop \n" \ 1325 : "=r" (__treg)); \ 1326 __treg; \ 1327 }) 1328 1329 #define mthi0(x) \ 1330 do { \ 1331 __asm__ __volatile__( \ 1332 " .set push \n" \ 1333 " .set noat \n" \ 1334 " move $1, %0 \n" \ 1335 " # mthi $1, $ac0 \n" \ 1336 " .word 0x00200011 \n" \ 1337 " .set pop \n" \ 1338 : \ 1339 : "r" (x)); \ 1340 } while (0) 1341 1342 #define mthi1(x) \ 1343 do { \ 1344 __asm__ __volatile__( \ 1345 " .set push \n" \ 1346 " .set noat \n" \ 1347 " move $1, %0 \n" \ 1348 " # mthi $1, $ac1 \n" \ 1349 " .word 0x00200811 \n" \ 1350 " .set pop \n" \ 1351 : \ 1352 : "r" (x)); \ 1353 } while (0) 1354 1355 #define mthi2(x) \ 1356 do { \ 1357 __asm__ __volatile__( \ 1358 " .set push \n" \ 1359 " .set noat \n" \ 1360 " move $1, %0 \n" \ 1361 " # mthi $1, $ac2 \n" \ 1362 " .word 0x00201011 \n" \ 1363 " .set pop \n" \ 1364 : \ 1365 : "r" (x)); \ 1366 } while (0) 1367 1368 #define mthi3(x) \ 1369 do { \ 1370 __asm__ __volatile__( \ 1371 " .set push \n" \ 1372 " .set noat \n" \ 1373 " move $1, %0 \n" \ 1374 " # mthi $1, $ac3 \n" \ 1375 " .word 0x00201811 \n" \ 1376 " .set pop \n" \ 1377 : \ 1378 : "r" (x)); \ 1379 } while (0) 1380 1381 #define mtlo0(x) \ 1382 do { \ 1383 __asm__ __volatile__( \ 1384 " .set push \n" \ 1385 " .set noat \n" \ 1386 " move $1, %0 \n" \ 1387 " # mtlo $1, $ac0 \n" \ 1388 " .word 0x00200013 \n" \ 1389 " .set pop \n" \ 1390 : \ 1391 : "r" (x)); \ 1392 } while (0) 1393 1394 #define mtlo1(x) \ 1395 do { \ 1396 __asm__ __volatile__( \ 1397 " .set push \n" \ 1398 " .set noat \n" \ 1399 " move $1, %0 \n" \ 1400 " # mtlo $1, $ac1 \n" \ 1401 " .word 0x00200813 \n" \ 1402 " .set pop \n" \ 1403 : \ 1404 : "r" (x)); \ 1405 } while (0) 1406 1407 #define mtlo2(x) \ 1408 do { \ 1409 __asm__ __volatile__( \ 1410 " .set push \n" \ 1411 " .set noat \n" \ 1412 " move $1, %0 \n" \ 1413 " # mtlo $1, $ac2 \n" \ 1414 " .word 0x00201013 \n" \ 1415 " .set pop \n" \ 1416 : \ 1417 : "r" (x)); \ 1418 } while (0) 1419 1420 #define mtlo3(x) \ 1421 do { \ 1422 __asm__ __volatile__( \ 1423 " .set push \n" \ 1424 " .set noat \n" \ 1425 " move $1, %0 \n" \ 1426 " # mtlo $1, $ac3 \n" \ 1427 " .word 0x00201813 \n" \ 1428 " .set pop \n" \ 1429 : \ 1430 : "r" (x)); \ 1431 } while (0) 1432 1433 #endif 1434 1435 /* 1436 * TLB operations. 1437 * 1438 * It is responsibility of the caller to take care of any TLB hazards. 1439 */ 1440 static inline void tlb_probe(void) 1441 { 1442 __asm__ __volatile__( 1443 ".set noreorder\n\t" 1444 "tlbp\n\t" 1445 ".set reorder"); 1446 } 1447 1448 static inline void tlb_read(void) 1449 { 1450 #if MIPS34K_MISSED_ITLB_WAR 1451 int res = 0; 1452 1453 __asm__ __volatile__( 1454 " .set push \n" 1455 " .set noreorder \n" 1456 " .set noat \n" 1457 " .set mips32r2 \n" 1458 " .word 0x41610001 # dvpe $1 \n" 1459 " move %0, $1 \n" 1460 " ehb \n" 1461 " .set pop \n" 1462 : "=r" (res)); 1463 1464 instruction_hazard(); 1465 #endif 1466 1467 __asm__ __volatile__( 1468 ".set noreorder\n\t" 1469 "tlbr\n\t" 1470 ".set reorder"); 1471 1472 #if MIPS34K_MISSED_ITLB_WAR 1473 if ((res & _ULCAST_(1))) 1474 __asm__ __volatile__( 1475 " .set push \n" 1476 " .set noreorder \n" 1477 " .set noat \n" 1478 " .set mips32r2 \n" 1479 " .word 0x41600021 # evpe \n" 1480 " ehb \n" 1481 " .set pop \n"); 1482 #endif 1483 } 1484 1485 static inline void tlb_write_indexed(void) 1486 { 1487 __asm__ __volatile__( 1488 ".set noreorder\n\t" 1489 "tlbwi\n\t" 1490 ".set reorder"); 1491 } 1492 1493 static inline void tlb_write_random(void) 1494 { 1495 __asm__ __volatile__( 1496 ".set noreorder\n\t" 1497 "tlbwr\n\t" 1498 ".set reorder"); 1499 } 1500 1501 /* 1502 * Manipulate bits in a c0 register. 1503 */ 1504 #ifndef CONFIG_MIPS_MT_SMTC 1505 /* 1506 * SMTC Linux requires shutting-down microthread scheduling 1507 * during CP0 register read-modify-write sequences. 1508 */ 1509 #define __BUILD_SET_C0(name) \ 1510 static inline unsigned int \ 1511 set_c0_##name(unsigned int set) \ 1512 { \ 1513 unsigned int res, new; \ 1514 \ 1515 res = read_c0_##name(); \ 1516 new = res | set; \ 1517 write_c0_##name(new); \ 1518 \ 1519 return res; \ 1520 } \ 1521 \ 1522 static inline unsigned int \ 1523 clear_c0_##name(unsigned int clear) \ 1524 { \ 1525 unsigned int res, new; \ 1526 \ 1527 res = read_c0_##name(); \ 1528 new = res & ~clear; \ 1529 write_c0_##name(new); \ 1530 \ 1531 return res; \ 1532 } \ 1533 \ 1534 static inline unsigned int \ 1535 change_c0_##name(unsigned int change, unsigned int val) \ 1536 { \ 1537 unsigned int res, new; \ 1538 \ 1539 res = read_c0_##name(); \ 1540 new = res & ~change; \ 1541 new |= (val & change); \ 1542 write_c0_##name(new); \ 1543 \ 1544 return res; \ 1545 } 1546 1547 #else /* SMTC versions that manage MT scheduling */ 1548 1549 #include <linux/irqflags.h> 1550 1551 /* 1552 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1553 * header file recursion. 1554 */ 1555 static inline unsigned int __dmt(void) 1556 { 1557 int res; 1558 1559 __asm__ __volatile__( 1560 " .set push \n" 1561 " .set mips32r2 \n" 1562 " .set noat \n" 1563 " .word 0x41610BC1 # dmt $1 \n" 1564 " ehb \n" 1565 " move %0, $1 \n" 1566 " .set pop \n" 1567 : "=r" (res)); 1568 1569 instruction_hazard(); 1570 1571 return res; 1572 } 1573 1574 #define __VPECONTROL_TE_SHIFT 15 1575 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1576 1577 #define __EMT_ENABLE __VPECONTROL_TE 1578 1579 static inline void __emt(unsigned int previous) 1580 { 1581 if ((previous & __EMT_ENABLE)) 1582 __asm__ __volatile__( 1583 " .set mips32r2 \n" 1584 " .word 0x41600be1 # emt \n" 1585 " ehb \n" 1586 " .set mips0 \n"); 1587 } 1588 1589 static inline void __ehb(void) 1590 { 1591 __asm__ __volatile__( 1592 " .set mips32r2 \n" 1593 " ehb \n" " .set mips0 \n"); 1594 } 1595 1596 /* 1597 * Note that local_irq_save/restore affect TC-specific IXMT state, 1598 * not Status.IE as in non-SMTC kernel. 1599 */ 1600 1601 #define __BUILD_SET_C0(name) \ 1602 static inline unsigned int \ 1603 set_c0_##name(unsigned int set) \ 1604 { \ 1605 unsigned int res; \ 1606 unsigned int new; \ 1607 unsigned int omt; \ 1608 unsigned long flags; \ 1609 \ 1610 local_irq_save(flags); \ 1611 omt = __dmt(); \ 1612 res = read_c0_##name(); \ 1613 new = res | set; \ 1614 write_c0_##name(new); \ 1615 __emt(omt); \ 1616 local_irq_restore(flags); \ 1617 \ 1618 return res; \ 1619 } \ 1620 \ 1621 static inline unsigned int \ 1622 clear_c0_##name(unsigned int clear) \ 1623 { \ 1624 unsigned int res; \ 1625 unsigned int new; \ 1626 unsigned int omt; \ 1627 unsigned long flags; \ 1628 \ 1629 local_irq_save(flags); \ 1630 omt = __dmt(); \ 1631 res = read_c0_##name(); \ 1632 new = res & ~clear; \ 1633 write_c0_##name(new); \ 1634 __emt(omt); \ 1635 local_irq_restore(flags); \ 1636 \ 1637 return res; \ 1638 } \ 1639 \ 1640 static inline unsigned int \ 1641 change_c0_##name(unsigned int change, unsigned int newbits) \ 1642 { \ 1643 unsigned int res; \ 1644 unsigned int new; \ 1645 unsigned int omt; \ 1646 unsigned long flags; \ 1647 \ 1648 local_irq_save(flags); \ 1649 \ 1650 omt = __dmt(); \ 1651 res = read_c0_##name(); \ 1652 new = res & ~change; \ 1653 new |= (newbits & change); \ 1654 write_c0_##name(new); \ 1655 __emt(omt); \ 1656 local_irq_restore(flags); \ 1657 \ 1658 return res; \ 1659 } 1660 #endif 1661 1662 __BUILD_SET_C0(status) 1663 __BUILD_SET_C0(cause) 1664 __BUILD_SET_C0(config) 1665 __BUILD_SET_C0(intcontrol) 1666 __BUILD_SET_C0(intctl) 1667 __BUILD_SET_C0(srsmap) 1668 __BUILD_SET_C0(brcm_config_0) 1669 __BUILD_SET_C0(brcm_bus_pll) 1670 __BUILD_SET_C0(brcm_reset) 1671 __BUILD_SET_C0(brcm_cmt_intr) 1672 __BUILD_SET_C0(brcm_cmt_ctrl) 1673 __BUILD_SET_C0(brcm_config) 1674 __BUILD_SET_C0(brcm_mode) 1675 1676 #endif /* !__ASSEMBLY__ */ 1677 1678 #endif /* _ASM_MIPSREGS_H */ 1679