1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <linux/types.h> 18 #include <asm/hazards.h> 19 #include <asm/war.h> 20 21 /* 22 * The following macros are especially useful for __asm__ 23 * inline assembler. 24 */ 25 #ifndef __STR 26 #define __STR(x) #x 27 #endif 28 #ifndef STR 29 #define STR(x) __STR(x) 30 #endif 31 32 /* 33 * Configure language 34 */ 35 #ifdef __ASSEMBLY__ 36 #define _ULCAST_ 37 #else 38 #define _ULCAST_ (unsigned long) 39 #endif 40 41 /* 42 * Coprocessor 0 register names 43 */ 44 #define CP0_INDEX $0 45 #define CP0_RANDOM $1 46 #define CP0_ENTRYLO0 $2 47 #define CP0_ENTRYLO1 $3 48 #define CP0_CONF $3 49 #define CP0_CONTEXT $4 50 #define CP0_PAGEMASK $5 51 #define CP0_WIRED $6 52 #define CP0_INFO $7 53 #define CP0_BADVADDR $8 54 #define CP0_COUNT $9 55 #define CP0_ENTRYHI $10 56 #define CP0_COMPARE $11 57 #define CP0_STATUS $12 58 #define CP0_CAUSE $13 59 #define CP0_EPC $14 60 #define CP0_PRID $15 61 #define CP0_CONFIG $16 62 #define CP0_LLADDR $17 63 #define CP0_WATCHLO $18 64 #define CP0_WATCHHI $19 65 #define CP0_XCONTEXT $20 66 #define CP0_FRAMEMASK $21 67 #define CP0_DIAGNOSTIC $22 68 #define CP0_DEBUG $23 69 #define CP0_DEPC $24 70 #define CP0_PERFORMANCE $25 71 #define CP0_ECC $26 72 #define CP0_CACHEERR $27 73 #define CP0_TAGLO $28 74 #define CP0_TAGHI $29 75 #define CP0_ERROREPC $30 76 #define CP0_DESAVE $31 77 78 /* 79 * R4640/R4650 cp0 register names. These registers are listed 80 * here only for completeness; without MMU these CPUs are not useable 81 * by Linux. A future ELKS port might take make Linux run on them 82 * though ... 83 */ 84 #define CP0_IBASE $0 85 #define CP0_IBOUND $1 86 #define CP0_DBASE $2 87 #define CP0_DBOUND $3 88 #define CP0_CALG $17 89 #define CP0_IWATCH $18 90 #define CP0_DWATCH $19 91 92 /* 93 * Coprocessor 0 Set 1 register names 94 */ 95 #define CP0_S1_DERRADDR0 $26 96 #define CP0_S1_DERRADDR1 $27 97 #define CP0_S1_INTCONTROL $20 98 99 /* 100 * Coprocessor 0 Set 2 register names 101 */ 102 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 103 104 /* 105 * Coprocessor 0 Set 3 register names 106 */ 107 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 108 109 /* 110 * TX39 Series 111 */ 112 #define CP0_TX39_CACHE $7 113 114 /* 115 * Coprocessor 1 (FPU) register names 116 */ 117 #define CP1_REVISION $0 118 #define CP1_STATUS $31 119 120 /* 121 * FPU Status Register Values 122 */ 123 /* 124 * Status Register Values 125 */ 126 127 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 128 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 130 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 131 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 132 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 133 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 134 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 135 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 136 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 137 138 /* 139 * Bits 18 - 20 of the FPU Status Register will be read as 0, 140 * and should be written as zero. 141 */ 142 #define FPU_CSR_RSVD 0x001c0000 143 144 /* 145 * X the exception cause indicator 146 * E the exception enable 147 * S the sticky/flag bit 148 */ 149 #define FPU_CSR_ALL_X 0x0003f000 150 #define FPU_CSR_UNI_X 0x00020000 151 #define FPU_CSR_INV_X 0x00010000 152 #define FPU_CSR_DIV_X 0x00008000 153 #define FPU_CSR_OVF_X 0x00004000 154 #define FPU_CSR_UDF_X 0x00002000 155 #define FPU_CSR_INE_X 0x00001000 156 157 #define FPU_CSR_ALL_E 0x00000f80 158 #define FPU_CSR_INV_E 0x00000800 159 #define FPU_CSR_DIV_E 0x00000400 160 #define FPU_CSR_OVF_E 0x00000200 161 #define FPU_CSR_UDF_E 0x00000100 162 #define FPU_CSR_INE_E 0x00000080 163 164 #define FPU_CSR_ALL_S 0x0000007c 165 #define FPU_CSR_INV_S 0x00000040 166 #define FPU_CSR_DIV_S 0x00000020 167 #define FPU_CSR_OVF_S 0x00000010 168 #define FPU_CSR_UDF_S 0x00000008 169 #define FPU_CSR_INE_S 0x00000004 170 171 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 172 #define FPU_CSR_RM 0x00000003 173 #define FPU_CSR_RN 0x0 /* nearest */ 174 #define FPU_CSR_RZ 0x1 /* towards zero */ 175 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 176 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 177 178 179 /* 180 * Values for PageMask register 181 */ 182 #ifdef CONFIG_CPU_VR41XX 183 184 /* Why doesn't stupidity hurt ... */ 185 186 #define PM_1K 0x00000000 187 #define PM_4K 0x00001800 188 #define PM_16K 0x00007800 189 #define PM_64K 0x0001f800 190 #define PM_256K 0x0007f800 191 192 #else 193 194 #define PM_4K 0x00000000 195 #define PM_8K 0x00002000 196 #define PM_16K 0x00006000 197 #define PM_32K 0x0000e000 198 #define PM_64K 0x0001e000 199 #define PM_128K 0x0003e000 200 #define PM_256K 0x0007e000 201 #define PM_512K 0x000fe000 202 #define PM_1M 0x001fe000 203 #define PM_2M 0x003fe000 204 #define PM_4M 0x007fe000 205 #define PM_8M 0x00ffe000 206 #define PM_16M 0x01ffe000 207 #define PM_32M 0x03ffe000 208 #define PM_64M 0x07ffe000 209 #define PM_256M 0x1fffe000 210 #define PM_1G 0x7fffe000 211 212 #endif 213 214 /* 215 * Default page size for a given kernel configuration 216 */ 217 #ifdef CONFIG_PAGE_SIZE_4KB 218 #define PM_DEFAULT_MASK PM_4K 219 #elif defined(CONFIG_PAGE_SIZE_8KB) 220 #define PM_DEFAULT_MASK PM_8K 221 #elif defined(CONFIG_PAGE_SIZE_16KB) 222 #define PM_DEFAULT_MASK PM_16K 223 #elif defined(CONFIG_PAGE_SIZE_32KB) 224 #define PM_DEFAULT_MASK PM_32K 225 #elif defined(CONFIG_PAGE_SIZE_64KB) 226 #define PM_DEFAULT_MASK PM_64K 227 #else 228 #error Bad page size configuration! 229 #endif 230 231 /* 232 * Default huge tlb size for a given kernel configuration 233 */ 234 #ifdef CONFIG_PAGE_SIZE_4KB 235 #define PM_HUGE_MASK PM_1M 236 #elif defined(CONFIG_PAGE_SIZE_8KB) 237 #define PM_HUGE_MASK PM_4M 238 #elif defined(CONFIG_PAGE_SIZE_16KB) 239 #define PM_HUGE_MASK PM_16M 240 #elif defined(CONFIG_PAGE_SIZE_32KB) 241 #define PM_HUGE_MASK PM_64M 242 #elif defined(CONFIG_PAGE_SIZE_64KB) 243 #define PM_HUGE_MASK PM_256M 244 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 245 #error Bad page size configuration for hugetlbfs! 246 #endif 247 248 /* 249 * Values used for computation of new tlb entries 250 */ 251 #define PL_4K 12 252 #define PL_16K 14 253 #define PL_64K 16 254 #define PL_256K 18 255 #define PL_1M 20 256 #define PL_4M 22 257 #define PL_16M 24 258 #define PL_64M 26 259 #define PL_256M 28 260 261 /* 262 * PageGrain bits 263 */ 264 #define PG_RIE (_ULCAST_(1) << 31) 265 #define PG_XIE (_ULCAST_(1) << 30) 266 #define PG_ELPA (_ULCAST_(1) << 29) 267 #define PG_ESP (_ULCAST_(1) << 28) 268 269 /* 270 * R4x00 interrupt enable / cause bits 271 */ 272 #define IE_SW0 (_ULCAST_(1) << 8) 273 #define IE_SW1 (_ULCAST_(1) << 9) 274 #define IE_IRQ0 (_ULCAST_(1) << 10) 275 #define IE_IRQ1 (_ULCAST_(1) << 11) 276 #define IE_IRQ2 (_ULCAST_(1) << 12) 277 #define IE_IRQ3 (_ULCAST_(1) << 13) 278 #define IE_IRQ4 (_ULCAST_(1) << 14) 279 #define IE_IRQ5 (_ULCAST_(1) << 15) 280 281 /* 282 * R4x00 interrupt cause bits 283 */ 284 #define C_SW0 (_ULCAST_(1) << 8) 285 #define C_SW1 (_ULCAST_(1) << 9) 286 #define C_IRQ0 (_ULCAST_(1) << 10) 287 #define C_IRQ1 (_ULCAST_(1) << 11) 288 #define C_IRQ2 (_ULCAST_(1) << 12) 289 #define C_IRQ3 (_ULCAST_(1) << 13) 290 #define C_IRQ4 (_ULCAST_(1) << 14) 291 #define C_IRQ5 (_ULCAST_(1) << 15) 292 293 /* 294 * Bitfields in the R4xx0 cp0 status register 295 */ 296 #define ST0_IE 0x00000001 297 #define ST0_EXL 0x00000002 298 #define ST0_ERL 0x00000004 299 #define ST0_KSU 0x00000018 300 # define KSU_USER 0x00000010 301 # define KSU_SUPERVISOR 0x00000008 302 # define KSU_KERNEL 0x00000000 303 #define ST0_UX 0x00000020 304 #define ST0_SX 0x00000040 305 #define ST0_KX 0x00000080 306 #define ST0_DE 0x00010000 307 #define ST0_CE 0x00020000 308 309 /* 310 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 311 * cacheops in userspace. This bit exists only on RM7000 and RM9000 312 * processors. 313 */ 314 #define ST0_CO 0x08000000 315 316 /* 317 * Bitfields in the R[23]000 cp0 status register. 318 */ 319 #define ST0_IEC 0x00000001 320 #define ST0_KUC 0x00000002 321 #define ST0_IEP 0x00000004 322 #define ST0_KUP 0x00000008 323 #define ST0_IEO 0x00000010 324 #define ST0_KUO 0x00000020 325 /* bits 6 & 7 are reserved on R[23]000 */ 326 #define ST0_ISC 0x00010000 327 #define ST0_SWC 0x00020000 328 #define ST0_CM 0x00080000 329 330 /* 331 * Bits specific to the R4640/R4650 332 */ 333 #define ST0_UM (_ULCAST_(1) << 4) 334 #define ST0_IL (_ULCAST_(1) << 23) 335 #define ST0_DL (_ULCAST_(1) << 24) 336 337 /* 338 * Enable the MIPS MDMX and DSP ASEs 339 */ 340 #define ST0_MX 0x01000000 341 342 /* 343 * Bitfields in the TX39 family CP0 Configuration Register 3 344 */ 345 #define TX39_CONF_ICS_SHIFT 19 346 #define TX39_CONF_ICS_MASK 0x00380000 347 #define TX39_CONF_ICS_1KB 0x00000000 348 #define TX39_CONF_ICS_2KB 0x00080000 349 #define TX39_CONF_ICS_4KB 0x00100000 350 #define TX39_CONF_ICS_8KB 0x00180000 351 #define TX39_CONF_ICS_16KB 0x00200000 352 353 #define TX39_CONF_DCS_SHIFT 16 354 #define TX39_CONF_DCS_MASK 0x00070000 355 #define TX39_CONF_DCS_1KB 0x00000000 356 #define TX39_CONF_DCS_2KB 0x00010000 357 #define TX39_CONF_DCS_4KB 0x00020000 358 #define TX39_CONF_DCS_8KB 0x00030000 359 #define TX39_CONF_DCS_16KB 0x00040000 360 361 #define TX39_CONF_CWFON 0x00004000 362 #define TX39_CONF_WBON 0x00002000 363 #define TX39_CONF_RF_SHIFT 10 364 #define TX39_CONF_RF_MASK 0x00000c00 365 #define TX39_CONF_DOZE 0x00000200 366 #define TX39_CONF_HALT 0x00000100 367 #define TX39_CONF_LOCK 0x00000080 368 #define TX39_CONF_ICE 0x00000020 369 #define TX39_CONF_DCE 0x00000010 370 #define TX39_CONF_IRSIZE_SHIFT 2 371 #define TX39_CONF_IRSIZE_MASK 0x0000000c 372 #define TX39_CONF_DRSIZE_SHIFT 0 373 #define TX39_CONF_DRSIZE_MASK 0x00000003 374 375 /* 376 * Status register bits available in all MIPS CPUs. 377 */ 378 #define ST0_IM 0x0000ff00 379 #define STATUSB_IP0 8 380 #define STATUSF_IP0 (_ULCAST_(1) << 8) 381 #define STATUSB_IP1 9 382 #define STATUSF_IP1 (_ULCAST_(1) << 9) 383 #define STATUSB_IP2 10 384 #define STATUSF_IP2 (_ULCAST_(1) << 10) 385 #define STATUSB_IP3 11 386 #define STATUSF_IP3 (_ULCAST_(1) << 11) 387 #define STATUSB_IP4 12 388 #define STATUSF_IP4 (_ULCAST_(1) << 12) 389 #define STATUSB_IP5 13 390 #define STATUSF_IP5 (_ULCAST_(1) << 13) 391 #define STATUSB_IP6 14 392 #define STATUSF_IP6 (_ULCAST_(1) << 14) 393 #define STATUSB_IP7 15 394 #define STATUSF_IP7 (_ULCAST_(1) << 15) 395 #define STATUSB_IP8 0 396 #define STATUSF_IP8 (_ULCAST_(1) << 0) 397 #define STATUSB_IP9 1 398 #define STATUSF_IP9 (_ULCAST_(1) << 1) 399 #define STATUSB_IP10 2 400 #define STATUSF_IP10 (_ULCAST_(1) << 2) 401 #define STATUSB_IP11 3 402 #define STATUSF_IP11 (_ULCAST_(1) << 3) 403 #define STATUSB_IP12 4 404 #define STATUSF_IP12 (_ULCAST_(1) << 4) 405 #define STATUSB_IP13 5 406 #define STATUSF_IP13 (_ULCAST_(1) << 5) 407 #define STATUSB_IP14 6 408 #define STATUSF_IP14 (_ULCAST_(1) << 6) 409 #define STATUSB_IP15 7 410 #define STATUSF_IP15 (_ULCAST_(1) << 7) 411 #define ST0_CH 0x00040000 412 #define ST0_NMI 0x00080000 413 #define ST0_SR 0x00100000 414 #define ST0_TS 0x00200000 415 #define ST0_BEV 0x00400000 416 #define ST0_RE 0x02000000 417 #define ST0_FR 0x04000000 418 #define ST0_CU 0xf0000000 419 #define ST0_CU0 0x10000000 420 #define ST0_CU1 0x20000000 421 #define ST0_CU2 0x40000000 422 #define ST0_CU3 0x80000000 423 #define ST0_XX 0x80000000 /* MIPS IV naming */ 424 425 /* 426 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 427 * 428 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 429 */ 430 #define INTCTLB_IPPCI 26 431 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 432 #define INTCTLB_IPTI 29 433 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 434 435 /* 436 * Bitfields and bit numbers in the coprocessor 0 cause register. 437 * 438 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 439 */ 440 #define CAUSEB_EXCCODE 2 441 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 442 #define CAUSEB_IP 8 443 #define CAUSEF_IP (_ULCAST_(255) << 8) 444 #define CAUSEB_IP0 8 445 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 446 #define CAUSEB_IP1 9 447 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 448 #define CAUSEB_IP2 10 449 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 450 #define CAUSEB_IP3 11 451 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 452 #define CAUSEB_IP4 12 453 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 454 #define CAUSEB_IP5 13 455 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 456 #define CAUSEB_IP6 14 457 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 458 #define CAUSEB_IP7 15 459 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 460 #define CAUSEB_IV 23 461 #define CAUSEF_IV (_ULCAST_(1) << 23) 462 #define CAUSEB_PCI 26 463 #define CAUSEF_PCI (_ULCAST_(1) << 26) 464 #define CAUSEB_CE 28 465 #define CAUSEF_CE (_ULCAST_(3) << 28) 466 #define CAUSEB_TI 30 467 #define CAUSEF_TI (_ULCAST_(1) << 30) 468 #define CAUSEB_BD 31 469 #define CAUSEF_BD (_ULCAST_(1) << 31) 470 471 /* 472 * Bits in the coprocessor 0 config register. 473 */ 474 /* Generic bits. */ 475 #define CONF_CM_CACHABLE_NO_WA 0 476 #define CONF_CM_CACHABLE_WA 1 477 #define CONF_CM_UNCACHED 2 478 #define CONF_CM_CACHABLE_NONCOHERENT 3 479 #define CONF_CM_CACHABLE_CE 4 480 #define CONF_CM_CACHABLE_COW 5 481 #define CONF_CM_CACHABLE_CUW 6 482 #define CONF_CM_CACHABLE_ACCELERATED 7 483 #define CONF_CM_CMASK 7 484 #define CONF_BE (_ULCAST_(1) << 15) 485 486 /* Bits common to various processors. */ 487 #define CONF_CU (_ULCAST_(1) << 3) 488 #define CONF_DB (_ULCAST_(1) << 4) 489 #define CONF_IB (_ULCAST_(1) << 5) 490 #define CONF_DC (_ULCAST_(7) << 6) 491 #define CONF_IC (_ULCAST_(7) << 9) 492 #define CONF_EB (_ULCAST_(1) << 13) 493 #define CONF_EM (_ULCAST_(1) << 14) 494 #define CONF_SM (_ULCAST_(1) << 16) 495 #define CONF_SC (_ULCAST_(1) << 17) 496 #define CONF_EW (_ULCAST_(3) << 18) 497 #define CONF_EP (_ULCAST_(15)<< 24) 498 #define CONF_EC (_ULCAST_(7) << 28) 499 #define CONF_CM (_ULCAST_(1) << 31) 500 501 /* Bits specific to the R4xx0. */ 502 #define R4K_CONF_SW (_ULCAST_(1) << 20) 503 #define R4K_CONF_SS (_ULCAST_(1) << 21) 504 #define R4K_CONF_SB (_ULCAST_(3) << 22) 505 506 /* Bits specific to the R5000. */ 507 #define R5K_CONF_SE (_ULCAST_(1) << 12) 508 #define R5K_CONF_SS (_ULCAST_(3) << 20) 509 510 /* Bits specific to the RM7000. */ 511 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 512 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 513 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 514 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 515 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 516 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 517 518 /* Bits specific to the R10000. */ 519 #define R10K_CONF_DN (_ULCAST_(3) << 3) 520 #define R10K_CONF_CT (_ULCAST_(1) << 5) 521 #define R10K_CONF_PE (_ULCAST_(1) << 6) 522 #define R10K_CONF_PM (_ULCAST_(3) << 7) 523 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 524 #define R10K_CONF_SB (_ULCAST_(1) << 13) 525 #define R10K_CONF_SK (_ULCAST_(1) << 14) 526 #define R10K_CONF_SS (_ULCAST_(7) << 16) 527 #define R10K_CONF_SC (_ULCAST_(7) << 19) 528 #define R10K_CONF_DC (_ULCAST_(7) << 26) 529 #define R10K_CONF_IC (_ULCAST_(7) << 29) 530 531 /* Bits specific to the VR41xx. */ 532 #define VR41_CONF_CS (_ULCAST_(1) << 12) 533 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 534 #define VR41_CONF_BP (_ULCAST_(1) << 16) 535 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 536 #define VR41_CONF_AD (_ULCAST_(1) << 23) 537 538 /* Bits specific to the R30xx. */ 539 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 540 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 541 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 542 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 543 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 544 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 545 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 546 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 547 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 548 549 /* Bits specific to the TX49. */ 550 #define TX49_CONF_DC (_ULCAST_(1) << 16) 551 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 552 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 553 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 554 555 /* Bits specific to the MIPS32/64 PRA. */ 556 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 557 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 558 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 559 #define MIPS_CONF_M (_ULCAST_(1) << 31) 560 561 /* 562 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 563 */ 564 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 565 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 566 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 567 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 568 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 569 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 570 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 571 #define MIPS_CONF1_DA_SHF 7 572 #define MIPS_CONF1_DA_SZ 3 573 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 574 #define MIPS_CONF1_DL_SHF 10 575 #define MIPS_CONF1_DL_SZ 3 576 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 577 #define MIPS_CONF1_DS_SHF 13 578 #define MIPS_CONF1_DS_SZ 3 579 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 580 #define MIPS_CONF1_IA_SHF 16 581 #define MIPS_CONF1_IA_SZ 3 582 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 583 #define MIPS_CONF1_IL_SHF 19 584 #define MIPS_CONF1_IL_SZ 3 585 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 586 #define MIPS_CONF1_IS_SHF 22 587 #define MIPS_CONF1_IS_SZ 3 588 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 589 #define MIPS_CONF1_TLBS_SHIFT (25) 590 #define MIPS_CONF1_TLBS_SIZE (6) 591 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) 592 593 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 594 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 595 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 596 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 597 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 598 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 599 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 600 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 601 602 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 603 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 604 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 605 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) 606 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 607 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 608 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 609 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 610 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) 611 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 612 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 613 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 614 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 615 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 616 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 617 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 618 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) 619 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) 620 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) 621 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 622 #define MIPS_CONF3_PW (_ULCAST_(1) << 24) 623 #define MIPS_CONF3_SC (_ULCAST_(1) << 25) 624 #define MIPS_CONF3_BI (_ULCAST_(1) << 26) 625 #define MIPS_CONF3_BP (_ULCAST_(1) << 27) 626 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) 627 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) 628 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) 629 630 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 631 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 632 #define MIPS_CONF4_FTLBSETS_SHIFT (0) 633 #define MIPS_CONF4_FTLBSETS_SHIFT (0) 634 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 635 #define MIPS_CONF4_FTLBWAYS_SHIFT (4) 636 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 637 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) 638 /* bits 10:8 in FTLB-only configurations */ 639 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 640 /* bits 12:8 in VTLB-FTLB only configurations */ 641 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 642 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 643 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 644 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) 645 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) 646 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) 647 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) 648 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) 649 #define MIPS_CONF4_AE (_ULCAST_(1) << 28) 650 #define MIPS_CONF4_IE (_ULCAST_(3) << 29) 651 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) 652 653 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 654 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 655 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 656 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 657 #define MIPS_CONF5_CV (_ULCAST_(1) << 29) 658 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 659 660 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 661 /* proAptiv FTLB on/off bit */ 662 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) 663 664 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 665 666 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 667 668 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 669 #define MIPS_CONF7_AR (_ULCAST_(1) << 16) 670 671 /* EntryHI bit definition */ 672 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 673 674 /* CMGCRBase bit definitions */ 675 #define MIPS_CMGCRB_BASE 11 676 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) 677 678 /* 679 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 680 */ 681 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 682 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 683 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 684 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 685 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 686 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 687 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 688 689 /* 690 * Bits in the MIPS32 Memory Segmentation registers. 691 */ 692 #define MIPS_SEGCFG_PA_SHIFT 9 693 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) 694 #define MIPS_SEGCFG_AM_SHIFT 4 695 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) 696 #define MIPS_SEGCFG_EU_SHIFT 3 697 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) 698 #define MIPS_SEGCFG_C_SHIFT 0 699 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) 700 701 #define MIPS_SEGCFG_UUSK _ULCAST_(7) 702 #define MIPS_SEGCFG_USK _ULCAST_(5) 703 #define MIPS_SEGCFG_MUSUK _ULCAST_(4) 704 #define MIPS_SEGCFG_MUSK _ULCAST_(3) 705 #define MIPS_SEGCFG_MSK _ULCAST_(2) 706 #define MIPS_SEGCFG_MK _ULCAST_(1) 707 #define MIPS_SEGCFG_UK _ULCAST_(0) 708 709 #ifndef __ASSEMBLY__ 710 711 /* 712 * Macros for handling the ISA mode bit for microMIPS. 713 */ 714 #define get_isa16_mode(x) ((x) & 0x1) 715 #define msk_isa16_mode(x) ((x) & ~0x1) 716 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) 717 718 /* 719 * microMIPS instructions can be 16-bit or 32-bit in length. This 720 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. 721 */ 722 static inline int mm_insn_16bit(u16 insn) 723 { 724 u16 opcode = (insn >> 10) & 0x7; 725 726 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 727 } 728 729 /* 730 * TLB Invalidate Flush 731 */ 732 static inline void tlbinvf(void) 733 { 734 __asm__ __volatile__( 735 ".set push\n\t" 736 ".set noreorder\n\t" 737 ".word 0x42000004\n\t" /* tlbinvf */ 738 ".set pop"); 739 } 740 741 742 /* 743 * Functions to access the R10000 performance counters. These are basically 744 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 745 * performance counter number encoded into bits 1 ... 5 of the instruction. 746 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 747 * disassembler these will look like an access to sel 0 or 1. 748 */ 749 #define read_r10k_perf_cntr(counter) \ 750 ({ \ 751 unsigned int __res; \ 752 __asm__ __volatile__( \ 753 "mfpc\t%0, %1" \ 754 : "=r" (__res) \ 755 : "i" (counter)); \ 756 \ 757 __res; \ 758 }) 759 760 #define write_r10k_perf_cntr(counter,val) \ 761 do { \ 762 __asm__ __volatile__( \ 763 "mtpc\t%0, %1" \ 764 : \ 765 : "r" (val), "i" (counter)); \ 766 } while (0) 767 768 #define read_r10k_perf_event(counter) \ 769 ({ \ 770 unsigned int __res; \ 771 __asm__ __volatile__( \ 772 "mfps\t%0, %1" \ 773 : "=r" (__res) \ 774 : "i" (counter)); \ 775 \ 776 __res; \ 777 }) 778 779 #define write_r10k_perf_cntl(counter,val) \ 780 do { \ 781 __asm__ __volatile__( \ 782 "mtps\t%0, %1" \ 783 : \ 784 : "r" (val), "i" (counter)); \ 785 } while (0) 786 787 788 /* 789 * Macros to access the system control coprocessor 790 */ 791 792 #define __read_32bit_c0_register(source, sel) \ 793 ({ int __res; \ 794 if (sel == 0) \ 795 __asm__ __volatile__( \ 796 "mfc0\t%0, " #source "\n\t" \ 797 : "=r" (__res)); \ 798 else \ 799 __asm__ __volatile__( \ 800 ".set\tmips32\n\t" \ 801 "mfc0\t%0, " #source ", " #sel "\n\t" \ 802 ".set\tmips0\n\t" \ 803 : "=r" (__res)); \ 804 __res; \ 805 }) 806 807 #define __read_64bit_c0_register(source, sel) \ 808 ({ unsigned long long __res; \ 809 if (sizeof(unsigned long) == 4) \ 810 __res = __read_64bit_c0_split(source, sel); \ 811 else if (sel == 0) \ 812 __asm__ __volatile__( \ 813 ".set\tmips3\n\t" \ 814 "dmfc0\t%0, " #source "\n\t" \ 815 ".set\tmips0" \ 816 : "=r" (__res)); \ 817 else \ 818 __asm__ __volatile__( \ 819 ".set\tmips64\n\t" \ 820 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 821 ".set\tmips0" \ 822 : "=r" (__res)); \ 823 __res; \ 824 }) 825 826 #define __write_32bit_c0_register(register, sel, value) \ 827 do { \ 828 if (sel == 0) \ 829 __asm__ __volatile__( \ 830 "mtc0\t%z0, " #register "\n\t" \ 831 : : "Jr" ((unsigned int)(value))); \ 832 else \ 833 __asm__ __volatile__( \ 834 ".set\tmips32\n\t" \ 835 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 836 ".set\tmips0" \ 837 : : "Jr" ((unsigned int)(value))); \ 838 } while (0) 839 840 #define __write_64bit_c0_register(register, sel, value) \ 841 do { \ 842 if (sizeof(unsigned long) == 4) \ 843 __write_64bit_c0_split(register, sel, value); \ 844 else if (sel == 0) \ 845 __asm__ __volatile__( \ 846 ".set\tmips3\n\t" \ 847 "dmtc0\t%z0, " #register "\n\t" \ 848 ".set\tmips0" \ 849 : : "Jr" (value)); \ 850 else \ 851 __asm__ __volatile__( \ 852 ".set\tmips64\n\t" \ 853 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 854 ".set\tmips0" \ 855 : : "Jr" (value)); \ 856 } while (0) 857 858 #define __read_ulong_c0_register(reg, sel) \ 859 ((sizeof(unsigned long) == 4) ? \ 860 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 861 (unsigned long) __read_64bit_c0_register(reg, sel)) 862 863 #define __write_ulong_c0_register(reg, sel, val) \ 864 do { \ 865 if (sizeof(unsigned long) == 4) \ 866 __write_32bit_c0_register(reg, sel, val); \ 867 else \ 868 __write_64bit_c0_register(reg, sel, val); \ 869 } while (0) 870 871 /* 872 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 873 */ 874 #define __read_32bit_c0_ctrl_register(source) \ 875 ({ int __res; \ 876 __asm__ __volatile__( \ 877 "cfc0\t%0, " #source "\n\t" \ 878 : "=r" (__res)); \ 879 __res; \ 880 }) 881 882 #define __write_32bit_c0_ctrl_register(register, value) \ 883 do { \ 884 __asm__ __volatile__( \ 885 "ctc0\t%z0, " #register "\n\t" \ 886 : : "Jr" ((unsigned int)(value))); \ 887 } while (0) 888 889 /* 890 * These versions are only needed for systems with more than 38 bits of 891 * physical address space running the 32-bit kernel. That's none atm :-) 892 */ 893 #define __read_64bit_c0_split(source, sel) \ 894 ({ \ 895 unsigned long long __val; \ 896 unsigned long __flags; \ 897 \ 898 local_irq_save(__flags); \ 899 if (sel == 0) \ 900 __asm__ __volatile__( \ 901 ".set\tmips64\n\t" \ 902 "dmfc0\t%M0, " #source "\n\t" \ 903 "dsll\t%L0, %M0, 32\n\t" \ 904 "dsra\t%M0, %M0, 32\n\t" \ 905 "dsra\t%L0, %L0, 32\n\t" \ 906 ".set\tmips0" \ 907 : "=r" (__val)); \ 908 else \ 909 __asm__ __volatile__( \ 910 ".set\tmips64\n\t" \ 911 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 912 "dsll\t%L0, %M0, 32\n\t" \ 913 "dsra\t%M0, %M0, 32\n\t" \ 914 "dsra\t%L0, %L0, 32\n\t" \ 915 ".set\tmips0" \ 916 : "=r" (__val)); \ 917 local_irq_restore(__flags); \ 918 \ 919 __val; \ 920 }) 921 922 #define __write_64bit_c0_split(source, sel, val) \ 923 do { \ 924 unsigned long __flags; \ 925 \ 926 local_irq_save(__flags); \ 927 if (sel == 0) \ 928 __asm__ __volatile__( \ 929 ".set\tmips64\n\t" \ 930 "dsll\t%L0, %L0, 32\n\t" \ 931 "dsrl\t%L0, %L0, 32\n\t" \ 932 "dsll\t%M0, %M0, 32\n\t" \ 933 "or\t%L0, %L0, %M0\n\t" \ 934 "dmtc0\t%L0, " #source "\n\t" \ 935 ".set\tmips0" \ 936 : : "r" (val)); \ 937 else \ 938 __asm__ __volatile__( \ 939 ".set\tmips64\n\t" \ 940 "dsll\t%L0, %L0, 32\n\t" \ 941 "dsrl\t%L0, %L0, 32\n\t" \ 942 "dsll\t%M0, %M0, 32\n\t" \ 943 "or\t%L0, %L0, %M0\n\t" \ 944 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 945 ".set\tmips0" \ 946 : : "r" (val)); \ 947 local_irq_restore(__flags); \ 948 } while (0) 949 950 #define read_c0_index() __read_32bit_c0_register($0, 0) 951 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 952 953 #define read_c0_random() __read_32bit_c0_register($1, 0) 954 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 955 956 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 957 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 958 959 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 960 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 961 962 #define read_c0_conf() __read_32bit_c0_register($3, 0) 963 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 964 965 #define read_c0_context() __read_ulong_c0_register($4, 0) 966 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 967 968 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 969 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 970 971 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 972 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 973 974 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 975 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 976 977 #define read_c0_wired() __read_32bit_c0_register($6, 0) 978 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 979 980 #define read_c0_info() __read_32bit_c0_register($7, 0) 981 982 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 983 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 984 985 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 986 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 987 988 #define read_c0_count() __read_32bit_c0_register($9, 0) 989 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 990 991 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 992 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 993 994 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 995 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 996 997 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 998 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 999 1000 #define read_c0_compare() __read_32bit_c0_register($11, 0) 1001 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 1002 1003 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 1004 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 1005 1006 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 1007 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 1008 1009 #define read_c0_status() __read_32bit_c0_register($12, 0) 1010 #ifdef CONFIG_MIPS_MT_SMTC 1011 #define write_c0_status(val) \ 1012 do { \ 1013 __write_32bit_c0_register($12, 0, val); \ 1014 __ehb(); \ 1015 } while (0) 1016 #else 1017 /* 1018 * Legacy non-SMTC code, which may be hazardous 1019 * but which might not support EHB 1020 */ 1021 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 1022 #endif /* CONFIG_MIPS_MT_SMTC */ 1023 1024 #define read_c0_cause() __read_32bit_c0_register($13, 0) 1025 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 1026 1027 #define read_c0_epc() __read_ulong_c0_register($14, 0) 1028 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 1029 1030 #define read_c0_prid() __read_32bit_c0_register($15, 0) 1031 1032 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) 1033 1034 #define read_c0_config() __read_32bit_c0_register($16, 0) 1035 #define read_c0_config1() __read_32bit_c0_register($16, 1) 1036 #define read_c0_config2() __read_32bit_c0_register($16, 2) 1037 #define read_c0_config3() __read_32bit_c0_register($16, 3) 1038 #define read_c0_config4() __read_32bit_c0_register($16, 4) 1039 #define read_c0_config5() __read_32bit_c0_register($16, 5) 1040 #define read_c0_config6() __read_32bit_c0_register($16, 6) 1041 #define read_c0_config7() __read_32bit_c0_register($16, 7) 1042 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 1043 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 1044 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 1045 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 1046 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 1047 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 1048 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1049 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1050 1051 /* 1052 * The WatchLo register. There may be up to 8 of them. 1053 */ 1054 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 1055 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 1056 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 1057 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 1058 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 1059 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 1060 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 1061 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 1062 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 1063 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 1064 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 1065 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 1066 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 1067 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 1068 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 1069 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 1070 1071 /* 1072 * The WatchHi register. There may be up to 8 of them. 1073 */ 1074 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 1075 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 1076 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 1077 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 1078 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 1079 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 1080 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 1081 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 1082 1083 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 1084 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 1085 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 1086 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 1087 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 1088 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 1089 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 1090 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 1091 1092 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 1093 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 1094 1095 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 1096 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 1097 1098 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 1099 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 1100 1101 #define read_c0_diag() __read_32bit_c0_register($22, 0) 1102 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 1103 1104 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 1105 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 1106 1107 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 1108 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 1109 1110 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 1111 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1112 1113 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 1114 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1115 1116 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 1117 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1118 1119 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1120 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1121 1122 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1123 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1124 1125 /* 1126 * MIPS32 / MIPS64 performance counters 1127 */ 1128 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1129 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1130 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1131 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1132 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1133 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1134 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1135 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1136 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1137 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1138 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1139 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1140 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1141 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1142 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1143 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1144 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1145 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1146 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1147 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1148 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1149 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1150 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1151 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1152 1153 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1154 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1155 1156 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1157 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1158 1159 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1160 1161 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1162 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1163 1164 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1165 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1166 1167 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1168 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1169 1170 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1171 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1172 1173 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1174 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1175 1176 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1177 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1178 1179 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1180 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1181 1182 /* MIPSR2 */ 1183 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1184 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1185 1186 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1187 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1188 1189 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1190 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1191 1192 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1193 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1194 1195 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1196 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1197 1198 /* MIPSR3 */ 1199 #define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1200 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1201 1202 #define read_c0_segctl1() __read_32bit_c0_register($5, 3) 1203 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) 1204 1205 #define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1206 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1207 1208 /* Cavium OCTEON (cnMIPS) */ 1209 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1210 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1211 1212 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1213 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1214 1215 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1216 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1217 /* 1218 * The cacheerr registers are not standardized. On OCTEON, they are 1219 * 64 bits wide. 1220 */ 1221 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1222 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1223 1224 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1225 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1226 1227 /* BMIPS3300 */ 1228 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1229 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1230 1231 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1232 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1233 1234 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1235 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1236 1237 /* BMIPS43xx */ 1238 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1239 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1240 1241 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1242 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1243 1244 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1245 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1246 1247 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1248 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1249 1250 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1251 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1252 1253 /* BMIPS5000 */ 1254 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1255 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1256 1257 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1258 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1259 1260 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1261 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1262 1263 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1264 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1265 1266 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1267 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1268 1269 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1270 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1271 1272 /* 1273 * Macros to access the floating point coprocessor control registers 1274 */ 1275 #define read_32bit_cp1_register(source) \ 1276 ({ \ 1277 int __res; \ 1278 \ 1279 __asm__ __volatile__( \ 1280 " .set push \n" \ 1281 " .set reorder \n" \ 1282 " # gas fails to assemble cfc1 for some archs, \n" \ 1283 " # like Octeon. \n" \ 1284 " .set mips1 \n" \ 1285 " cfc1 %0,"STR(source)" \n" \ 1286 " .set pop \n" \ 1287 : "=r" (__res)); \ 1288 __res; \ 1289 }) 1290 1291 #ifdef HAVE_AS_DSP 1292 #define rddsp(mask) \ 1293 ({ \ 1294 unsigned int __dspctl; \ 1295 \ 1296 __asm__ __volatile__( \ 1297 " .set push \n" \ 1298 " .set dsp \n" \ 1299 " rddsp %0, %x1 \n" \ 1300 " .set pop \n" \ 1301 : "=r" (__dspctl) \ 1302 : "i" (mask)); \ 1303 __dspctl; \ 1304 }) 1305 1306 #define wrdsp(val, mask) \ 1307 do { \ 1308 __asm__ __volatile__( \ 1309 " .set push \n" \ 1310 " .set dsp \n" \ 1311 " wrdsp %0, %x1 \n" \ 1312 " .set pop \n" \ 1313 : \ 1314 : "r" (val), "i" (mask)); \ 1315 } while (0) 1316 1317 #define mflo0() \ 1318 ({ \ 1319 long mflo0; \ 1320 __asm__( \ 1321 " .set push \n" \ 1322 " .set dsp \n" \ 1323 " mflo %0, $ac0 \n" \ 1324 " .set pop \n" \ 1325 : "=r" (mflo0)); \ 1326 mflo0; \ 1327 }) 1328 1329 #define mflo1() \ 1330 ({ \ 1331 long mflo1; \ 1332 __asm__( \ 1333 " .set push \n" \ 1334 " .set dsp \n" \ 1335 " mflo %0, $ac1 \n" \ 1336 " .set pop \n" \ 1337 : "=r" (mflo1)); \ 1338 mflo1; \ 1339 }) 1340 1341 #define mflo2() \ 1342 ({ \ 1343 long mflo2; \ 1344 __asm__( \ 1345 " .set push \n" \ 1346 " .set dsp \n" \ 1347 " mflo %0, $ac2 \n" \ 1348 " .set pop \n" \ 1349 : "=r" (mflo2)); \ 1350 mflo2; \ 1351 }) 1352 1353 #define mflo3() \ 1354 ({ \ 1355 long mflo3; \ 1356 __asm__( \ 1357 " .set push \n" \ 1358 " .set dsp \n" \ 1359 " mflo %0, $ac3 \n" \ 1360 " .set pop \n" \ 1361 : "=r" (mflo3)); \ 1362 mflo3; \ 1363 }) 1364 1365 #define mfhi0() \ 1366 ({ \ 1367 long mfhi0; \ 1368 __asm__( \ 1369 " .set push \n" \ 1370 " .set dsp \n" \ 1371 " mfhi %0, $ac0 \n" \ 1372 " .set pop \n" \ 1373 : "=r" (mfhi0)); \ 1374 mfhi0; \ 1375 }) 1376 1377 #define mfhi1() \ 1378 ({ \ 1379 long mfhi1; \ 1380 __asm__( \ 1381 " .set push \n" \ 1382 " .set dsp \n" \ 1383 " mfhi %0, $ac1 \n" \ 1384 " .set pop \n" \ 1385 : "=r" (mfhi1)); \ 1386 mfhi1; \ 1387 }) 1388 1389 #define mfhi2() \ 1390 ({ \ 1391 long mfhi2; \ 1392 __asm__( \ 1393 " .set push \n" \ 1394 " .set dsp \n" \ 1395 " mfhi %0, $ac2 \n" \ 1396 " .set pop \n" \ 1397 : "=r" (mfhi2)); \ 1398 mfhi2; \ 1399 }) 1400 1401 #define mfhi3() \ 1402 ({ \ 1403 long mfhi3; \ 1404 __asm__( \ 1405 " .set push \n" \ 1406 " .set dsp \n" \ 1407 " mfhi %0, $ac3 \n" \ 1408 " .set pop \n" \ 1409 : "=r" (mfhi3)); \ 1410 mfhi3; \ 1411 }) 1412 1413 1414 #define mtlo0(x) \ 1415 ({ \ 1416 __asm__( \ 1417 " .set push \n" \ 1418 " .set dsp \n" \ 1419 " mtlo %0, $ac0 \n" \ 1420 " .set pop \n" \ 1421 : \ 1422 : "r" (x)); \ 1423 }) 1424 1425 #define mtlo1(x) \ 1426 ({ \ 1427 __asm__( \ 1428 " .set push \n" \ 1429 " .set dsp \n" \ 1430 " mtlo %0, $ac1 \n" \ 1431 " .set pop \n" \ 1432 : \ 1433 : "r" (x)); \ 1434 }) 1435 1436 #define mtlo2(x) \ 1437 ({ \ 1438 __asm__( \ 1439 " .set push \n" \ 1440 " .set dsp \n" \ 1441 " mtlo %0, $ac2 \n" \ 1442 " .set pop \n" \ 1443 : \ 1444 : "r" (x)); \ 1445 }) 1446 1447 #define mtlo3(x) \ 1448 ({ \ 1449 __asm__( \ 1450 " .set push \n" \ 1451 " .set dsp \n" \ 1452 " mtlo %0, $ac3 \n" \ 1453 " .set pop \n" \ 1454 : \ 1455 : "r" (x)); \ 1456 }) 1457 1458 #define mthi0(x) \ 1459 ({ \ 1460 __asm__( \ 1461 " .set push \n" \ 1462 " .set dsp \n" \ 1463 " mthi %0, $ac0 \n" \ 1464 " .set pop \n" \ 1465 : \ 1466 : "r" (x)); \ 1467 }) 1468 1469 #define mthi1(x) \ 1470 ({ \ 1471 __asm__( \ 1472 " .set push \n" \ 1473 " .set dsp \n" \ 1474 " mthi %0, $ac1 \n" \ 1475 " .set pop \n" \ 1476 : \ 1477 : "r" (x)); \ 1478 }) 1479 1480 #define mthi2(x) \ 1481 ({ \ 1482 __asm__( \ 1483 " .set push \n" \ 1484 " .set dsp \n" \ 1485 " mthi %0, $ac2 \n" \ 1486 " .set pop \n" \ 1487 : \ 1488 : "r" (x)); \ 1489 }) 1490 1491 #define mthi3(x) \ 1492 ({ \ 1493 __asm__( \ 1494 " .set push \n" \ 1495 " .set dsp \n" \ 1496 " mthi %0, $ac3 \n" \ 1497 " .set pop \n" \ 1498 : \ 1499 : "r" (x)); \ 1500 }) 1501 1502 #else 1503 1504 #ifdef CONFIG_CPU_MICROMIPS 1505 #define rddsp(mask) \ 1506 ({ \ 1507 unsigned int __res; \ 1508 \ 1509 __asm__ __volatile__( \ 1510 " .set push \n" \ 1511 " .set noat \n" \ 1512 " # rddsp $1, %x1 \n" \ 1513 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1514 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1515 " move %0, $1 \n" \ 1516 " .set pop \n" \ 1517 : "=r" (__res) \ 1518 : "i" (mask)); \ 1519 __res; \ 1520 }) 1521 1522 #define wrdsp(val, mask) \ 1523 do { \ 1524 __asm__ __volatile__( \ 1525 " .set push \n" \ 1526 " .set noat \n" \ 1527 " move $1, %0 \n" \ 1528 " # wrdsp $1, %x1 \n" \ 1529 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1530 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1531 " .set pop \n" \ 1532 : \ 1533 : "r" (val), "i" (mask)); \ 1534 } while (0) 1535 1536 #define _umips_dsp_mfxxx(ins) \ 1537 ({ \ 1538 unsigned long __treg; \ 1539 \ 1540 __asm__ __volatile__( \ 1541 " .set push \n" \ 1542 " .set noat \n" \ 1543 " .hword 0x0001 \n" \ 1544 " .hword %x1 \n" \ 1545 " move %0, $1 \n" \ 1546 " .set pop \n" \ 1547 : "=r" (__treg) \ 1548 : "i" (ins)); \ 1549 __treg; \ 1550 }) 1551 1552 #define _umips_dsp_mtxxx(val, ins) \ 1553 do { \ 1554 __asm__ __volatile__( \ 1555 " .set push \n" \ 1556 " .set noat \n" \ 1557 " move $1, %0 \n" \ 1558 " .hword 0x0001 \n" \ 1559 " .hword %x1 \n" \ 1560 " .set pop \n" \ 1561 : \ 1562 : "r" (val), "i" (ins)); \ 1563 } while (0) 1564 1565 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1566 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1567 1568 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1569 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1570 1571 #define mflo0() _umips_dsp_mflo(0) 1572 #define mflo1() _umips_dsp_mflo(1) 1573 #define mflo2() _umips_dsp_mflo(2) 1574 #define mflo3() _umips_dsp_mflo(3) 1575 1576 #define mfhi0() _umips_dsp_mfhi(0) 1577 #define mfhi1() _umips_dsp_mfhi(1) 1578 #define mfhi2() _umips_dsp_mfhi(2) 1579 #define mfhi3() _umips_dsp_mfhi(3) 1580 1581 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1582 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1583 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1584 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1585 1586 #define mthi0(x) _umips_dsp_mthi(x, 0) 1587 #define mthi1(x) _umips_dsp_mthi(x, 1) 1588 #define mthi2(x) _umips_dsp_mthi(x, 2) 1589 #define mthi3(x) _umips_dsp_mthi(x, 3) 1590 1591 #else /* !CONFIG_CPU_MICROMIPS */ 1592 #define rddsp(mask) \ 1593 ({ \ 1594 unsigned int __res; \ 1595 \ 1596 __asm__ __volatile__( \ 1597 " .set push \n" \ 1598 " .set noat \n" \ 1599 " # rddsp $1, %x1 \n" \ 1600 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1601 " move %0, $1 \n" \ 1602 " .set pop \n" \ 1603 : "=r" (__res) \ 1604 : "i" (mask)); \ 1605 __res; \ 1606 }) 1607 1608 #define wrdsp(val, mask) \ 1609 do { \ 1610 __asm__ __volatile__( \ 1611 " .set push \n" \ 1612 " .set noat \n" \ 1613 " move $1, %0 \n" \ 1614 " # wrdsp $1, %x1 \n" \ 1615 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1616 " .set pop \n" \ 1617 : \ 1618 : "r" (val), "i" (mask)); \ 1619 } while (0) 1620 1621 #define _dsp_mfxxx(ins) \ 1622 ({ \ 1623 unsigned long __treg; \ 1624 \ 1625 __asm__ __volatile__( \ 1626 " .set push \n" \ 1627 " .set noat \n" \ 1628 " .word (0x00000810 | %1) \n" \ 1629 " move %0, $1 \n" \ 1630 " .set pop \n" \ 1631 : "=r" (__treg) \ 1632 : "i" (ins)); \ 1633 __treg; \ 1634 }) 1635 1636 #define _dsp_mtxxx(val, ins) \ 1637 do { \ 1638 __asm__ __volatile__( \ 1639 " .set push \n" \ 1640 " .set noat \n" \ 1641 " move $1, %0 \n" \ 1642 " .word (0x00200011 | %1) \n" \ 1643 " .set pop \n" \ 1644 : \ 1645 : "r" (val), "i" (ins)); \ 1646 } while (0) 1647 1648 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1649 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1650 1651 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1652 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1653 1654 #define mflo0() _dsp_mflo(0) 1655 #define mflo1() _dsp_mflo(1) 1656 #define mflo2() _dsp_mflo(2) 1657 #define mflo3() _dsp_mflo(3) 1658 1659 #define mfhi0() _dsp_mfhi(0) 1660 #define mfhi1() _dsp_mfhi(1) 1661 #define mfhi2() _dsp_mfhi(2) 1662 #define mfhi3() _dsp_mfhi(3) 1663 1664 #define mtlo0(x) _dsp_mtlo(x, 0) 1665 #define mtlo1(x) _dsp_mtlo(x, 1) 1666 #define mtlo2(x) _dsp_mtlo(x, 2) 1667 #define mtlo3(x) _dsp_mtlo(x, 3) 1668 1669 #define mthi0(x) _dsp_mthi(x, 0) 1670 #define mthi1(x) _dsp_mthi(x, 1) 1671 #define mthi2(x) _dsp_mthi(x, 2) 1672 #define mthi3(x) _dsp_mthi(x, 3) 1673 1674 #endif /* CONFIG_CPU_MICROMIPS */ 1675 #endif 1676 1677 /* 1678 * TLB operations. 1679 * 1680 * It is responsibility of the caller to take care of any TLB hazards. 1681 */ 1682 static inline void tlb_probe(void) 1683 { 1684 __asm__ __volatile__( 1685 ".set noreorder\n\t" 1686 "tlbp\n\t" 1687 ".set reorder"); 1688 } 1689 1690 static inline void tlb_read(void) 1691 { 1692 #if MIPS34K_MISSED_ITLB_WAR 1693 int res = 0; 1694 1695 __asm__ __volatile__( 1696 " .set push \n" 1697 " .set noreorder \n" 1698 " .set noat \n" 1699 " .set mips32r2 \n" 1700 " .word 0x41610001 # dvpe $1 \n" 1701 " move %0, $1 \n" 1702 " ehb \n" 1703 " .set pop \n" 1704 : "=r" (res)); 1705 1706 instruction_hazard(); 1707 #endif 1708 1709 __asm__ __volatile__( 1710 ".set noreorder\n\t" 1711 "tlbr\n\t" 1712 ".set reorder"); 1713 1714 #if MIPS34K_MISSED_ITLB_WAR 1715 if ((res & _ULCAST_(1))) 1716 __asm__ __volatile__( 1717 " .set push \n" 1718 " .set noreorder \n" 1719 " .set noat \n" 1720 " .set mips32r2 \n" 1721 " .word 0x41600021 # evpe \n" 1722 " ehb \n" 1723 " .set pop \n"); 1724 #endif 1725 } 1726 1727 static inline void tlb_write_indexed(void) 1728 { 1729 __asm__ __volatile__( 1730 ".set noreorder\n\t" 1731 "tlbwi\n\t" 1732 ".set reorder"); 1733 } 1734 1735 static inline void tlb_write_random(void) 1736 { 1737 __asm__ __volatile__( 1738 ".set noreorder\n\t" 1739 "tlbwr\n\t" 1740 ".set reorder"); 1741 } 1742 1743 /* 1744 * Manipulate bits in a c0 register. 1745 */ 1746 #ifndef CONFIG_MIPS_MT_SMTC 1747 /* 1748 * SMTC Linux requires shutting-down microthread scheduling 1749 * during CP0 register read-modify-write sequences. 1750 */ 1751 #define __BUILD_SET_C0(name) \ 1752 static inline unsigned int \ 1753 set_c0_##name(unsigned int set) \ 1754 { \ 1755 unsigned int res, new; \ 1756 \ 1757 res = read_c0_##name(); \ 1758 new = res | set; \ 1759 write_c0_##name(new); \ 1760 \ 1761 return res; \ 1762 } \ 1763 \ 1764 static inline unsigned int \ 1765 clear_c0_##name(unsigned int clear) \ 1766 { \ 1767 unsigned int res, new; \ 1768 \ 1769 res = read_c0_##name(); \ 1770 new = res & ~clear; \ 1771 write_c0_##name(new); \ 1772 \ 1773 return res; \ 1774 } \ 1775 \ 1776 static inline unsigned int \ 1777 change_c0_##name(unsigned int change, unsigned int val) \ 1778 { \ 1779 unsigned int res, new; \ 1780 \ 1781 res = read_c0_##name(); \ 1782 new = res & ~change; \ 1783 new |= (val & change); \ 1784 write_c0_##name(new); \ 1785 \ 1786 return res; \ 1787 } 1788 1789 #else /* SMTC versions that manage MT scheduling */ 1790 1791 #include <linux/irqflags.h> 1792 1793 /* 1794 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1795 * header file recursion. 1796 */ 1797 static inline unsigned int __dmt(void) 1798 { 1799 int res; 1800 1801 __asm__ __volatile__( 1802 " .set push \n" 1803 " .set mips32r2 \n" 1804 " .set noat \n" 1805 " .word 0x41610BC1 # dmt $1 \n" 1806 " ehb \n" 1807 " move %0, $1 \n" 1808 " .set pop \n" 1809 : "=r" (res)); 1810 1811 instruction_hazard(); 1812 1813 return res; 1814 } 1815 1816 #define __VPECONTROL_TE_SHIFT 15 1817 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1818 1819 #define __EMT_ENABLE __VPECONTROL_TE 1820 1821 static inline void __emt(unsigned int previous) 1822 { 1823 if ((previous & __EMT_ENABLE)) 1824 __asm__ __volatile__( 1825 " .set mips32r2 \n" 1826 " .word 0x41600be1 # emt \n" 1827 " ehb \n" 1828 " .set mips0 \n"); 1829 } 1830 1831 static inline void __ehb(void) 1832 { 1833 __asm__ __volatile__( 1834 " .set mips32r2 \n" 1835 " ehb \n" " .set mips0 \n"); 1836 } 1837 1838 /* 1839 * Note that local_irq_save/restore affect TC-specific IXMT state, 1840 * not Status.IE as in non-SMTC kernel. 1841 */ 1842 1843 #define __BUILD_SET_C0(name) \ 1844 static inline unsigned int \ 1845 set_c0_##name(unsigned int set) \ 1846 { \ 1847 unsigned int res; \ 1848 unsigned int new; \ 1849 unsigned int omt; \ 1850 unsigned long flags; \ 1851 \ 1852 local_irq_save(flags); \ 1853 omt = __dmt(); \ 1854 res = read_c0_##name(); \ 1855 new = res | set; \ 1856 write_c0_##name(new); \ 1857 __emt(omt); \ 1858 local_irq_restore(flags); \ 1859 \ 1860 return res; \ 1861 } \ 1862 \ 1863 static inline unsigned int \ 1864 clear_c0_##name(unsigned int clear) \ 1865 { \ 1866 unsigned int res; \ 1867 unsigned int new; \ 1868 unsigned int omt; \ 1869 unsigned long flags; \ 1870 \ 1871 local_irq_save(flags); \ 1872 omt = __dmt(); \ 1873 res = read_c0_##name(); \ 1874 new = res & ~clear; \ 1875 write_c0_##name(new); \ 1876 __emt(omt); \ 1877 local_irq_restore(flags); \ 1878 \ 1879 return res; \ 1880 } \ 1881 \ 1882 static inline unsigned int \ 1883 change_c0_##name(unsigned int change, unsigned int newbits) \ 1884 { \ 1885 unsigned int res; \ 1886 unsigned int new; \ 1887 unsigned int omt; \ 1888 unsigned long flags; \ 1889 \ 1890 local_irq_save(flags); \ 1891 \ 1892 omt = __dmt(); \ 1893 res = read_c0_##name(); \ 1894 new = res & ~change; \ 1895 new |= (newbits & change); \ 1896 write_c0_##name(new); \ 1897 __emt(omt); \ 1898 local_irq_restore(flags); \ 1899 \ 1900 return res; \ 1901 } 1902 #endif 1903 1904 __BUILD_SET_C0(status) 1905 __BUILD_SET_C0(cause) 1906 __BUILD_SET_C0(config) 1907 __BUILD_SET_C0(config5) 1908 __BUILD_SET_C0(intcontrol) 1909 __BUILD_SET_C0(intctl) 1910 __BUILD_SET_C0(srsmap) 1911 __BUILD_SET_C0(brcm_config_0) 1912 __BUILD_SET_C0(brcm_bus_pll) 1913 __BUILD_SET_C0(brcm_reset) 1914 __BUILD_SET_C0(brcm_cmt_intr) 1915 __BUILD_SET_C0(brcm_cmt_ctrl) 1916 __BUILD_SET_C0(brcm_config) 1917 __BUILD_SET_C0(brcm_mode) 1918 1919 #endif /* !__ASSEMBLY__ */ 1920 1921 #endif /* _ASM_MIPSREGS_H */ 1922