1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <asm/hazards.h> 18 #include <asm/war.h> 19 20 /* 21 * The following macros are especially useful for __asm__ 22 * inline assembler. 23 */ 24 #ifndef __STR 25 #define __STR(x) #x 26 #endif 27 #ifndef STR 28 #define STR(x) __STR(x) 29 #endif 30 31 /* 32 * Configure language 33 */ 34 #ifdef __ASSEMBLY__ 35 #define _ULCAST_ 36 #else 37 #define _ULCAST_ (unsigned long) 38 #endif 39 40 /* 41 * Coprocessor 0 register names 42 */ 43 #define CP0_INDEX $0 44 #define CP0_RANDOM $1 45 #define CP0_ENTRYLO0 $2 46 #define CP0_ENTRYLO1 $3 47 #define CP0_CONF $3 48 #define CP0_CONTEXT $4 49 #define CP0_PAGEMASK $5 50 #define CP0_WIRED $6 51 #define CP0_INFO $7 52 #define CP0_BADVADDR $8 53 #define CP0_COUNT $9 54 #define CP0_ENTRYHI $10 55 #define CP0_COMPARE $11 56 #define CP0_STATUS $12 57 #define CP0_CAUSE $13 58 #define CP0_EPC $14 59 #define CP0_PRID $15 60 #define CP0_CONFIG $16 61 #define CP0_LLADDR $17 62 #define CP0_WATCHLO $18 63 #define CP0_WATCHHI $19 64 #define CP0_XCONTEXT $20 65 #define CP0_FRAMEMASK $21 66 #define CP0_DIAGNOSTIC $22 67 #define CP0_DEBUG $23 68 #define CP0_DEPC $24 69 #define CP0_PERFORMANCE $25 70 #define CP0_ECC $26 71 #define CP0_CACHEERR $27 72 #define CP0_TAGLO $28 73 #define CP0_TAGHI $29 74 #define CP0_ERROREPC $30 75 #define CP0_DESAVE $31 76 77 /* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83 #define CP0_IBASE $0 84 #define CP0_IBOUND $1 85 #define CP0_DBASE $2 86 #define CP0_DBOUND $3 87 #define CP0_CALG $17 88 #define CP0_IWATCH $18 89 #define CP0_DWATCH $19 90 91 /* 92 * Coprocessor 0 Set 1 register names 93 */ 94 #define CP0_S1_DERRADDR0 $26 95 #define CP0_S1_DERRADDR1 $27 96 #define CP0_S1_INTCONTROL $20 97 98 /* 99 * Coprocessor 0 Set 2 register names 100 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103 /* 104 * Coprocessor 0 Set 3 register names 105 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108 /* 109 * TX39 Series 110 */ 111 #define CP0_TX39_CACHE $7 112 113 /* 114 * Coprocessor 1 (FPU) register names 115 */ 116 #define CP1_REVISION $0 117 #define CP1_STATUS $31 118 119 /* 120 * FPU Status Register Values 121 */ 122 /* 123 * Status Register Values 124 */ 125 126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 136 137 /* 138 * X the exception cause indicator 139 * E the exception enable 140 * S the sticky/flag bit 141 */ 142 #define FPU_CSR_ALL_X 0x0003f000 143 #define FPU_CSR_UNI_X 0x00020000 144 #define FPU_CSR_INV_X 0x00010000 145 #define FPU_CSR_DIV_X 0x00008000 146 #define FPU_CSR_OVF_X 0x00004000 147 #define FPU_CSR_UDF_X 0x00002000 148 #define FPU_CSR_INE_X 0x00001000 149 150 #define FPU_CSR_ALL_E 0x00000f80 151 #define FPU_CSR_INV_E 0x00000800 152 #define FPU_CSR_DIV_E 0x00000400 153 #define FPU_CSR_OVF_E 0x00000200 154 #define FPU_CSR_UDF_E 0x00000100 155 #define FPU_CSR_INE_E 0x00000080 156 157 #define FPU_CSR_ALL_S 0x0000007c 158 #define FPU_CSR_INV_S 0x00000040 159 #define FPU_CSR_DIV_S 0x00000020 160 #define FPU_CSR_OVF_S 0x00000010 161 #define FPU_CSR_UDF_S 0x00000008 162 #define FPU_CSR_INE_S 0x00000004 163 164 /* rounding mode */ 165 #define FPU_CSR_RN 0x0 /* nearest */ 166 #define FPU_CSR_RZ 0x1 /* towards zero */ 167 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 168 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 169 170 171 /* 172 * Values for PageMask register 173 */ 174 #ifdef CONFIG_CPU_VR41XX 175 176 /* Why doesn't stupidity hurt ... */ 177 178 #define PM_1K 0x00000000 179 #define PM_4K 0x00001800 180 #define PM_16K 0x00007800 181 #define PM_64K 0x0001f800 182 #define PM_256K 0x0007f800 183 184 #else 185 186 #define PM_4K 0x00000000 187 #define PM_8K 0x00002000 188 #define PM_16K 0x00006000 189 #define PM_32K 0x0000e000 190 #define PM_64K 0x0001e000 191 #define PM_128K 0x0003e000 192 #define PM_256K 0x0007e000 193 #define PM_512K 0x000fe000 194 #define PM_1M 0x001fe000 195 #define PM_2M 0x003fe000 196 #define PM_4M 0x007fe000 197 #define PM_8M 0x00ffe000 198 #define PM_16M 0x01ffe000 199 #define PM_32M 0x03ffe000 200 #define PM_64M 0x07ffe000 201 #define PM_256M 0x1fffe000 202 #define PM_1G 0x7fffe000 203 204 #endif 205 206 /* 207 * Default page size for a given kernel configuration 208 */ 209 #ifdef CONFIG_PAGE_SIZE_4KB 210 #define PM_DEFAULT_MASK PM_4K 211 #elif defined(CONFIG_PAGE_SIZE_8KB) 212 #define PM_DEFAULT_MASK PM_8K 213 #elif defined(CONFIG_PAGE_SIZE_16KB) 214 #define PM_DEFAULT_MASK PM_16K 215 #elif defined(CONFIG_PAGE_SIZE_32KB) 216 #define PM_DEFAULT_MASK PM_32K 217 #elif defined(CONFIG_PAGE_SIZE_64KB) 218 #define PM_DEFAULT_MASK PM_64K 219 #else 220 #error Bad page size configuration! 221 #endif 222 223 224 /* 225 * Values used for computation of new tlb entries 226 */ 227 #define PL_4K 12 228 #define PL_16K 14 229 #define PL_64K 16 230 #define PL_256K 18 231 #define PL_1M 20 232 #define PL_4M 22 233 #define PL_16M 24 234 #define PL_64M 26 235 #define PL_256M 28 236 237 /* 238 * R4x00 interrupt enable / cause bits 239 */ 240 #define IE_SW0 (_ULCAST_(1) << 8) 241 #define IE_SW1 (_ULCAST_(1) << 9) 242 #define IE_IRQ0 (_ULCAST_(1) << 10) 243 #define IE_IRQ1 (_ULCAST_(1) << 11) 244 #define IE_IRQ2 (_ULCAST_(1) << 12) 245 #define IE_IRQ3 (_ULCAST_(1) << 13) 246 #define IE_IRQ4 (_ULCAST_(1) << 14) 247 #define IE_IRQ5 (_ULCAST_(1) << 15) 248 249 /* 250 * R4x00 interrupt cause bits 251 */ 252 #define C_SW0 (_ULCAST_(1) << 8) 253 #define C_SW1 (_ULCAST_(1) << 9) 254 #define C_IRQ0 (_ULCAST_(1) << 10) 255 #define C_IRQ1 (_ULCAST_(1) << 11) 256 #define C_IRQ2 (_ULCAST_(1) << 12) 257 #define C_IRQ3 (_ULCAST_(1) << 13) 258 #define C_IRQ4 (_ULCAST_(1) << 14) 259 #define C_IRQ5 (_ULCAST_(1) << 15) 260 261 /* 262 * Bitfields in the R4xx0 cp0 status register 263 */ 264 #define ST0_IE 0x00000001 265 #define ST0_EXL 0x00000002 266 #define ST0_ERL 0x00000004 267 #define ST0_KSU 0x00000018 268 # define KSU_USER 0x00000010 269 # define KSU_SUPERVISOR 0x00000008 270 # define KSU_KERNEL 0x00000000 271 #define ST0_UX 0x00000020 272 #define ST0_SX 0x00000040 273 #define ST0_KX 0x00000080 274 #define ST0_DE 0x00010000 275 #define ST0_CE 0x00020000 276 277 /* 278 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 279 * cacheops in userspace. This bit exists only on RM7000 and RM9000 280 * processors. 281 */ 282 #define ST0_CO 0x08000000 283 284 /* 285 * Bitfields in the R[23]000 cp0 status register. 286 */ 287 #define ST0_IEC 0x00000001 288 #define ST0_KUC 0x00000002 289 #define ST0_IEP 0x00000004 290 #define ST0_KUP 0x00000008 291 #define ST0_IEO 0x00000010 292 #define ST0_KUO 0x00000020 293 /* bits 6 & 7 are reserved on R[23]000 */ 294 #define ST0_ISC 0x00010000 295 #define ST0_SWC 0x00020000 296 #define ST0_CM 0x00080000 297 298 /* 299 * Bits specific to the R4640/R4650 300 */ 301 #define ST0_UM (_ULCAST_(1) << 4) 302 #define ST0_IL (_ULCAST_(1) << 23) 303 #define ST0_DL (_ULCAST_(1) << 24) 304 305 /* 306 * Enable the MIPS MDMX and DSP ASEs 307 */ 308 #define ST0_MX 0x01000000 309 310 /* 311 * Bitfields in the TX39 family CP0 Configuration Register 3 312 */ 313 #define TX39_CONF_ICS_SHIFT 19 314 #define TX39_CONF_ICS_MASK 0x00380000 315 #define TX39_CONF_ICS_1KB 0x00000000 316 #define TX39_CONF_ICS_2KB 0x00080000 317 #define TX39_CONF_ICS_4KB 0x00100000 318 #define TX39_CONF_ICS_8KB 0x00180000 319 #define TX39_CONF_ICS_16KB 0x00200000 320 321 #define TX39_CONF_DCS_SHIFT 16 322 #define TX39_CONF_DCS_MASK 0x00070000 323 #define TX39_CONF_DCS_1KB 0x00000000 324 #define TX39_CONF_DCS_2KB 0x00010000 325 #define TX39_CONF_DCS_4KB 0x00020000 326 #define TX39_CONF_DCS_8KB 0x00030000 327 #define TX39_CONF_DCS_16KB 0x00040000 328 329 #define TX39_CONF_CWFON 0x00004000 330 #define TX39_CONF_WBON 0x00002000 331 #define TX39_CONF_RF_SHIFT 10 332 #define TX39_CONF_RF_MASK 0x00000c00 333 #define TX39_CONF_DOZE 0x00000200 334 #define TX39_CONF_HALT 0x00000100 335 #define TX39_CONF_LOCK 0x00000080 336 #define TX39_CONF_ICE 0x00000020 337 #define TX39_CONF_DCE 0x00000010 338 #define TX39_CONF_IRSIZE_SHIFT 2 339 #define TX39_CONF_IRSIZE_MASK 0x0000000c 340 #define TX39_CONF_DRSIZE_SHIFT 0 341 #define TX39_CONF_DRSIZE_MASK 0x00000003 342 343 /* 344 * Status register bits available in all MIPS CPUs. 345 */ 346 #define ST0_IM 0x0000ff00 347 #define STATUSB_IP0 8 348 #define STATUSF_IP0 (_ULCAST_(1) << 8) 349 #define STATUSB_IP1 9 350 #define STATUSF_IP1 (_ULCAST_(1) << 9) 351 #define STATUSB_IP2 10 352 #define STATUSF_IP2 (_ULCAST_(1) << 10) 353 #define STATUSB_IP3 11 354 #define STATUSF_IP3 (_ULCAST_(1) << 11) 355 #define STATUSB_IP4 12 356 #define STATUSF_IP4 (_ULCAST_(1) << 12) 357 #define STATUSB_IP5 13 358 #define STATUSF_IP5 (_ULCAST_(1) << 13) 359 #define STATUSB_IP6 14 360 #define STATUSF_IP6 (_ULCAST_(1) << 14) 361 #define STATUSB_IP7 15 362 #define STATUSF_IP7 (_ULCAST_(1) << 15) 363 #define STATUSB_IP8 0 364 #define STATUSF_IP8 (_ULCAST_(1) << 0) 365 #define STATUSB_IP9 1 366 #define STATUSF_IP9 (_ULCAST_(1) << 1) 367 #define STATUSB_IP10 2 368 #define STATUSF_IP10 (_ULCAST_(1) << 2) 369 #define STATUSB_IP11 3 370 #define STATUSF_IP11 (_ULCAST_(1) << 3) 371 #define STATUSB_IP12 4 372 #define STATUSF_IP12 (_ULCAST_(1) << 4) 373 #define STATUSB_IP13 5 374 #define STATUSF_IP13 (_ULCAST_(1) << 5) 375 #define STATUSB_IP14 6 376 #define STATUSF_IP14 (_ULCAST_(1) << 6) 377 #define STATUSB_IP15 7 378 #define STATUSF_IP15 (_ULCAST_(1) << 7) 379 #define ST0_CH 0x00040000 380 #define ST0_SR 0x00100000 381 #define ST0_TS 0x00200000 382 #define ST0_BEV 0x00400000 383 #define ST0_RE 0x02000000 384 #define ST0_FR 0x04000000 385 #define ST0_CU 0xf0000000 386 #define ST0_CU0 0x10000000 387 #define ST0_CU1 0x20000000 388 #define ST0_CU2 0x40000000 389 #define ST0_CU3 0x80000000 390 #define ST0_XX 0x80000000 /* MIPS IV naming */ 391 392 /* 393 * Bitfields and bit numbers in the coprocessor 0 cause register. 394 * 395 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 396 */ 397 #define CAUSEB_EXCCODE 2 398 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 399 #define CAUSEB_IP 8 400 #define CAUSEF_IP (_ULCAST_(255) << 8) 401 #define CAUSEB_IP0 8 402 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 403 #define CAUSEB_IP1 9 404 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 405 #define CAUSEB_IP2 10 406 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 407 #define CAUSEB_IP3 11 408 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 409 #define CAUSEB_IP4 12 410 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 411 #define CAUSEB_IP5 13 412 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 413 #define CAUSEB_IP6 14 414 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 415 #define CAUSEB_IP7 15 416 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 417 #define CAUSEB_IV 23 418 #define CAUSEF_IV (_ULCAST_(1) << 23) 419 #define CAUSEB_CE 28 420 #define CAUSEF_CE (_ULCAST_(3) << 28) 421 #define CAUSEB_BD 31 422 #define CAUSEF_BD (_ULCAST_(1) << 31) 423 424 /* 425 * Bits in the coprocessor 0 config register. 426 */ 427 /* Generic bits. */ 428 #define CONF_CM_CACHABLE_NO_WA 0 429 #define CONF_CM_CACHABLE_WA 1 430 #define CONF_CM_UNCACHED 2 431 #define CONF_CM_CACHABLE_NONCOHERENT 3 432 #define CONF_CM_CACHABLE_CE 4 433 #define CONF_CM_CACHABLE_COW 5 434 #define CONF_CM_CACHABLE_CUW 6 435 #define CONF_CM_CACHABLE_ACCELERATED 7 436 #define CONF_CM_CMASK 7 437 #define CONF_BE (_ULCAST_(1) << 15) 438 439 /* Bits common to various processors. */ 440 #define CONF_CU (_ULCAST_(1) << 3) 441 #define CONF_DB (_ULCAST_(1) << 4) 442 #define CONF_IB (_ULCAST_(1) << 5) 443 #define CONF_DC (_ULCAST_(7) << 6) 444 #define CONF_IC (_ULCAST_(7) << 9) 445 #define CONF_EB (_ULCAST_(1) << 13) 446 #define CONF_EM (_ULCAST_(1) << 14) 447 #define CONF_SM (_ULCAST_(1) << 16) 448 #define CONF_SC (_ULCAST_(1) << 17) 449 #define CONF_EW (_ULCAST_(3) << 18) 450 #define CONF_EP (_ULCAST_(15)<< 24) 451 #define CONF_EC (_ULCAST_(7) << 28) 452 #define CONF_CM (_ULCAST_(1) << 31) 453 454 /* Bits specific to the R4xx0. */ 455 #define R4K_CONF_SW (_ULCAST_(1) << 20) 456 #define R4K_CONF_SS (_ULCAST_(1) << 21) 457 #define R4K_CONF_SB (_ULCAST_(3) << 22) 458 459 /* Bits specific to the R5000. */ 460 #define R5K_CONF_SE (_ULCAST_(1) << 12) 461 #define R5K_CONF_SS (_ULCAST_(3) << 20) 462 463 /* Bits specific to the RM7000. */ 464 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 465 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 466 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 467 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 468 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 469 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 470 471 /* Bits specific to the R10000. */ 472 #define R10K_CONF_DN (_ULCAST_(3) << 3) 473 #define R10K_CONF_CT (_ULCAST_(1) << 5) 474 #define R10K_CONF_PE (_ULCAST_(1) << 6) 475 #define R10K_CONF_PM (_ULCAST_(3) << 7) 476 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 477 #define R10K_CONF_SB (_ULCAST_(1) << 13) 478 #define R10K_CONF_SK (_ULCAST_(1) << 14) 479 #define R10K_CONF_SS (_ULCAST_(7) << 16) 480 #define R10K_CONF_SC (_ULCAST_(7) << 19) 481 #define R10K_CONF_DC (_ULCAST_(7) << 26) 482 #define R10K_CONF_IC (_ULCAST_(7) << 29) 483 484 /* Bits specific to the VR41xx. */ 485 #define VR41_CONF_CS (_ULCAST_(1) << 12) 486 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 487 #define VR41_CONF_BP (_ULCAST_(1) << 16) 488 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 489 #define VR41_CONF_AD (_ULCAST_(1) << 23) 490 491 /* Bits specific to the R30xx. */ 492 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 493 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 494 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 495 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 496 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 497 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 498 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 499 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 500 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 501 502 /* Bits specific to the TX49. */ 503 #define TX49_CONF_DC (_ULCAST_(1) << 16) 504 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 505 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 506 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 507 508 /* Bits specific to the MIPS32/64 PRA. */ 509 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 510 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 511 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 512 #define MIPS_CONF_M (_ULCAST_(1) << 31) 513 514 /* 515 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 516 */ 517 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 518 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 519 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 520 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 521 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 522 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 523 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 524 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 525 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 526 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 527 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 528 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 529 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 530 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 531 532 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 533 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 534 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 535 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 536 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 537 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 538 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 539 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 540 541 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 542 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 543 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 544 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 545 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 546 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 547 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 548 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 549 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 550 551 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 552 553 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 554 555 556 /* 557 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 558 */ 559 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 560 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 561 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 562 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 563 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 564 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 565 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 566 567 #ifndef __ASSEMBLY__ 568 569 /* 570 * Functions to access the R10000 performance counters. These are basically 571 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 572 * performance counter number encoded into bits 1 ... 5 of the instruction. 573 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 574 * disassembler these will look like an access to sel 0 or 1. 575 */ 576 #define read_r10k_perf_cntr(counter) \ 577 ({ \ 578 unsigned int __res; \ 579 __asm__ __volatile__( \ 580 "mfpc\t%0, %1" \ 581 : "=r" (__res) \ 582 : "i" (counter)); \ 583 \ 584 __res; \ 585 }) 586 587 #define write_r10k_perf_cntr(counter,val) \ 588 do { \ 589 __asm__ __volatile__( \ 590 "mtpc\t%0, %1" \ 591 : \ 592 : "r" (val), "i" (counter)); \ 593 } while (0) 594 595 #define read_r10k_perf_event(counter) \ 596 ({ \ 597 unsigned int __res; \ 598 __asm__ __volatile__( \ 599 "mfps\t%0, %1" \ 600 : "=r" (__res) \ 601 : "i" (counter)); \ 602 \ 603 __res; \ 604 }) 605 606 #define write_r10k_perf_cntl(counter,val) \ 607 do { \ 608 __asm__ __volatile__( \ 609 "mtps\t%0, %1" \ 610 : \ 611 : "r" (val), "i" (counter)); \ 612 } while (0) 613 614 615 /* 616 * Macros to access the system control coprocessor 617 */ 618 619 #define __read_32bit_c0_register(source, sel) \ 620 ({ int __res; \ 621 if (sel == 0) \ 622 __asm__ __volatile__( \ 623 "mfc0\t%0, " #source "\n\t" \ 624 : "=r" (__res)); \ 625 else \ 626 __asm__ __volatile__( \ 627 ".set\tmips32\n\t" \ 628 "mfc0\t%0, " #source ", " #sel "\n\t" \ 629 ".set\tmips0\n\t" \ 630 : "=r" (__res)); \ 631 __res; \ 632 }) 633 634 #define __read_64bit_c0_register(source, sel) \ 635 ({ unsigned long long __res; \ 636 if (sizeof(unsigned long) == 4) \ 637 __res = __read_64bit_c0_split(source, sel); \ 638 else if (sel == 0) \ 639 __asm__ __volatile__( \ 640 ".set\tmips3\n\t" \ 641 "dmfc0\t%0, " #source "\n\t" \ 642 ".set\tmips0" \ 643 : "=r" (__res)); \ 644 else \ 645 __asm__ __volatile__( \ 646 ".set\tmips64\n\t" \ 647 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 648 ".set\tmips0" \ 649 : "=r" (__res)); \ 650 __res; \ 651 }) 652 653 #define __write_32bit_c0_register(register, sel, value) \ 654 do { \ 655 if (sel == 0) \ 656 __asm__ __volatile__( \ 657 "mtc0\t%z0, " #register "\n\t" \ 658 : : "Jr" ((unsigned int)(value))); \ 659 else \ 660 __asm__ __volatile__( \ 661 ".set\tmips32\n\t" \ 662 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 663 ".set\tmips0" \ 664 : : "Jr" ((unsigned int)(value))); \ 665 } while (0) 666 667 #define __write_64bit_c0_register(register, sel, value) \ 668 do { \ 669 if (sizeof(unsigned long) == 4) \ 670 __write_64bit_c0_split(register, sel, value); \ 671 else if (sel == 0) \ 672 __asm__ __volatile__( \ 673 ".set\tmips3\n\t" \ 674 "dmtc0\t%z0, " #register "\n\t" \ 675 ".set\tmips0" \ 676 : : "Jr" (value)); \ 677 else \ 678 __asm__ __volatile__( \ 679 ".set\tmips64\n\t" \ 680 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 681 ".set\tmips0" \ 682 : : "Jr" (value)); \ 683 } while (0) 684 685 #define __read_ulong_c0_register(reg, sel) \ 686 ((sizeof(unsigned long) == 4) ? \ 687 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 688 (unsigned long) __read_64bit_c0_register(reg, sel)) 689 690 #define __write_ulong_c0_register(reg, sel, val) \ 691 do { \ 692 if (sizeof(unsigned long) == 4) \ 693 __write_32bit_c0_register(reg, sel, val); \ 694 else \ 695 __write_64bit_c0_register(reg, sel, val); \ 696 } while (0) 697 698 /* 699 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 700 */ 701 #define __read_32bit_c0_ctrl_register(source) \ 702 ({ int __res; \ 703 __asm__ __volatile__( \ 704 "cfc0\t%0, " #source "\n\t" \ 705 : "=r" (__res)); \ 706 __res; \ 707 }) 708 709 #define __write_32bit_c0_ctrl_register(register, value) \ 710 do { \ 711 __asm__ __volatile__( \ 712 "ctc0\t%z0, " #register "\n\t" \ 713 : : "Jr" ((unsigned int)(value))); \ 714 } while (0) 715 716 /* 717 * These versions are only needed for systems with more than 38 bits of 718 * physical address space running the 32-bit kernel. That's none atm :-) 719 */ 720 #define __read_64bit_c0_split(source, sel) \ 721 ({ \ 722 unsigned long long __val; \ 723 unsigned long __flags; \ 724 \ 725 local_irq_save(__flags); \ 726 if (sel == 0) \ 727 __asm__ __volatile__( \ 728 ".set\tmips64\n\t" \ 729 "dmfc0\t%M0, " #source "\n\t" \ 730 "dsll\t%L0, %M0, 32\n\t" \ 731 "dsra\t%M0, %M0, 32\n\t" \ 732 "dsra\t%L0, %L0, 32\n\t" \ 733 ".set\tmips0" \ 734 : "=r" (__val)); \ 735 else \ 736 __asm__ __volatile__( \ 737 ".set\tmips64\n\t" \ 738 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 739 "dsll\t%L0, %M0, 32\n\t" \ 740 "dsra\t%M0, %M0, 32\n\t" \ 741 "dsra\t%L0, %L0, 32\n\t" \ 742 ".set\tmips0" \ 743 : "=r" (__val)); \ 744 local_irq_restore(__flags); \ 745 \ 746 __val; \ 747 }) 748 749 #define __write_64bit_c0_split(source, sel, val) \ 750 do { \ 751 unsigned long __flags; \ 752 \ 753 local_irq_save(__flags); \ 754 if (sel == 0) \ 755 __asm__ __volatile__( \ 756 ".set\tmips64\n\t" \ 757 "dsll\t%L0, %L0, 32\n\t" \ 758 "dsrl\t%L0, %L0, 32\n\t" \ 759 "dsll\t%M0, %M0, 32\n\t" \ 760 "or\t%L0, %L0, %M0\n\t" \ 761 "dmtc0\t%L0, " #source "\n\t" \ 762 ".set\tmips0" \ 763 : : "r" (val)); \ 764 else \ 765 __asm__ __volatile__( \ 766 ".set\tmips64\n\t" \ 767 "dsll\t%L0, %L0, 32\n\t" \ 768 "dsrl\t%L0, %L0, 32\n\t" \ 769 "dsll\t%M0, %M0, 32\n\t" \ 770 "or\t%L0, %L0, %M0\n\t" \ 771 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 772 ".set\tmips0" \ 773 : : "r" (val)); \ 774 local_irq_restore(__flags); \ 775 } while (0) 776 777 #define read_c0_index() __read_32bit_c0_register($0, 0) 778 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 779 780 #define read_c0_random() __read_32bit_c0_register($1, 0) 781 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 782 783 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 784 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 785 786 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 787 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 788 789 #define read_c0_conf() __read_32bit_c0_register($3, 0) 790 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 791 792 #define read_c0_context() __read_ulong_c0_register($4, 0) 793 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 794 795 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 796 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 797 798 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 799 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 800 801 #define read_c0_wired() __read_32bit_c0_register($6, 0) 802 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 803 804 #define read_c0_info() __read_32bit_c0_register($7, 0) 805 806 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 807 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 808 809 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 810 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 811 812 #define read_c0_count() __read_32bit_c0_register($9, 0) 813 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 814 815 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 816 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 817 818 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 819 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 820 821 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 822 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 823 824 #define read_c0_compare() __read_32bit_c0_register($11, 0) 825 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 826 827 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 828 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 829 830 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 831 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 832 833 #define read_c0_status() __read_32bit_c0_register($12, 0) 834 #ifdef CONFIG_MIPS_MT_SMTC 835 #define write_c0_status(val) \ 836 do { \ 837 __write_32bit_c0_register($12, 0, val); \ 838 __ehb(); \ 839 } while (0) 840 #else 841 /* 842 * Legacy non-SMTC code, which may be hazardous 843 * but which might not support EHB 844 */ 845 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 846 #endif /* CONFIG_MIPS_MT_SMTC */ 847 848 #define read_c0_cause() __read_32bit_c0_register($13, 0) 849 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 850 851 #define read_c0_epc() __read_ulong_c0_register($14, 0) 852 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 853 854 #define read_c0_prid() __read_32bit_c0_register($15, 0) 855 856 #define read_c0_config() __read_32bit_c0_register($16, 0) 857 #define read_c0_config1() __read_32bit_c0_register($16, 1) 858 #define read_c0_config2() __read_32bit_c0_register($16, 2) 859 #define read_c0_config3() __read_32bit_c0_register($16, 3) 860 #define read_c0_config4() __read_32bit_c0_register($16, 4) 861 #define read_c0_config5() __read_32bit_c0_register($16, 5) 862 #define read_c0_config6() __read_32bit_c0_register($16, 6) 863 #define read_c0_config7() __read_32bit_c0_register($16, 7) 864 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 865 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 866 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 867 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 868 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 869 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 870 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 871 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 872 873 /* 874 * The WatchLo register. There may be upto 8 of them. 875 */ 876 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 877 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 878 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 879 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 880 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 881 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 882 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 883 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 884 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 885 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 886 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 887 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 888 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 889 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 890 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 891 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 892 893 /* 894 * The WatchHi register. There may be upto 8 of them. 895 */ 896 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 897 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 898 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 899 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 900 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 901 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 902 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 903 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 904 905 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 906 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 907 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 908 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 909 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 910 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 911 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 912 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 913 914 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 915 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 916 917 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 918 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 919 920 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 921 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 922 923 /* RM9000 PerfControl performance counter control register */ 924 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) 925 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) 926 927 #define read_c0_diag() __read_32bit_c0_register($22, 0) 928 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 929 930 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 931 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 932 933 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 934 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 935 936 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 937 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 938 939 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 940 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 941 942 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 943 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 944 945 #define read_c0_debug() __read_32bit_c0_register($23, 0) 946 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 947 948 #define read_c0_depc() __read_ulong_c0_register($24, 0) 949 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 950 951 /* 952 * MIPS32 / MIPS64 performance counters 953 */ 954 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 955 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 956 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 957 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 958 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 959 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 960 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 961 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 962 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 963 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 964 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 965 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 966 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 967 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 968 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 969 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 970 971 /* RM9000 PerfCount performance counter register */ 972 #define read_c0_perfcount() __read_64bit_c0_register($25, 0) 973 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) 974 975 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 976 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 977 978 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 979 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 980 981 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 982 983 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 984 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 985 986 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 987 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 988 989 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 990 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 991 992 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 993 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 994 995 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 996 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 997 998 /* MIPSR2 */ 999 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1000 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1001 1002 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1003 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1004 1005 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1006 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1007 1008 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1009 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1010 1011 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1012 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1013 1014 1015 /* Cavium OCTEON (cnMIPS) */ 1016 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1017 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1018 1019 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1020 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1021 1022 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1023 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1024 /* 1025 * The cacheerr registers are not standardized. On OCTEON, they are 1026 * 64 bits wide. 1027 */ 1028 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1029 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1030 1031 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1032 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1033 1034 /* 1035 * Macros to access the floating point coprocessor control registers 1036 */ 1037 #define read_32bit_cp1_register(source) \ 1038 ({ int __res; \ 1039 __asm__ __volatile__( \ 1040 ".set\tpush\n\t" \ 1041 ".set\treorder\n\t" \ 1042 /* gas fails to assemble cfc1 for some archs (octeon).*/ \ 1043 ".set\tmips1\n\t" \ 1044 "cfc1\t%0,"STR(source)"\n\t" \ 1045 ".set\tpop" \ 1046 : "=r" (__res)); \ 1047 __res;}) 1048 1049 #define rddsp(mask) \ 1050 ({ \ 1051 unsigned int __res; \ 1052 \ 1053 __asm__ __volatile__( \ 1054 " .set push \n" \ 1055 " .set noat \n" \ 1056 " # rddsp $1, %x1 \n" \ 1057 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1058 " move %0, $1 \n" \ 1059 " .set pop \n" \ 1060 : "=r" (__res) \ 1061 : "i" (mask)); \ 1062 __res; \ 1063 }) 1064 1065 #define wrdsp(val, mask) \ 1066 do { \ 1067 __asm__ __volatile__( \ 1068 " .set push \n" \ 1069 " .set noat \n" \ 1070 " move $1, %0 \n" \ 1071 " # wrdsp $1, %x1 \n" \ 1072 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1073 " .set pop \n" \ 1074 : \ 1075 : "r" (val), "i" (mask)); \ 1076 } while (0) 1077 1078 #if 0 /* Need DSP ASE capable assembler ... */ 1079 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1080 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1081 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1082 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) 1083 1084 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) 1085 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) 1086 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) 1087 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) 1088 1089 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) 1090 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) 1091 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) 1092 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) 1093 1094 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) 1095 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) 1096 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) 1097 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) 1098 1099 #else 1100 1101 #define mfhi0() \ 1102 ({ \ 1103 unsigned long __treg; \ 1104 \ 1105 __asm__ __volatile__( \ 1106 " .set push \n" \ 1107 " .set noat \n" \ 1108 " # mfhi %0, $ac0 \n" \ 1109 " .word 0x00000810 \n" \ 1110 " move %0, $1 \n" \ 1111 " .set pop \n" \ 1112 : "=r" (__treg)); \ 1113 __treg; \ 1114 }) 1115 1116 #define mfhi1() \ 1117 ({ \ 1118 unsigned long __treg; \ 1119 \ 1120 __asm__ __volatile__( \ 1121 " .set push \n" \ 1122 " .set noat \n" \ 1123 " # mfhi %0, $ac1 \n" \ 1124 " .word 0x00200810 \n" \ 1125 " move %0, $1 \n" \ 1126 " .set pop \n" \ 1127 : "=r" (__treg)); \ 1128 __treg; \ 1129 }) 1130 1131 #define mfhi2() \ 1132 ({ \ 1133 unsigned long __treg; \ 1134 \ 1135 __asm__ __volatile__( \ 1136 " .set push \n" \ 1137 " .set noat \n" \ 1138 " # mfhi %0, $ac2 \n" \ 1139 " .word 0x00400810 \n" \ 1140 " move %0, $1 \n" \ 1141 " .set pop \n" \ 1142 : "=r" (__treg)); \ 1143 __treg; \ 1144 }) 1145 1146 #define mfhi3() \ 1147 ({ \ 1148 unsigned long __treg; \ 1149 \ 1150 __asm__ __volatile__( \ 1151 " .set push \n" \ 1152 " .set noat \n" \ 1153 " # mfhi %0, $ac3 \n" \ 1154 " .word 0x00600810 \n" \ 1155 " move %0, $1 \n" \ 1156 " .set pop \n" \ 1157 : "=r" (__treg)); \ 1158 __treg; \ 1159 }) 1160 1161 #define mflo0() \ 1162 ({ \ 1163 unsigned long __treg; \ 1164 \ 1165 __asm__ __volatile__( \ 1166 " .set push \n" \ 1167 " .set noat \n" \ 1168 " # mflo %0, $ac0 \n" \ 1169 " .word 0x00000812 \n" \ 1170 " move %0, $1 \n" \ 1171 " .set pop \n" \ 1172 : "=r" (__treg)); \ 1173 __treg; \ 1174 }) 1175 1176 #define mflo1() \ 1177 ({ \ 1178 unsigned long __treg; \ 1179 \ 1180 __asm__ __volatile__( \ 1181 " .set push \n" \ 1182 " .set noat \n" \ 1183 " # mflo %0, $ac1 \n" \ 1184 " .word 0x00200812 \n" \ 1185 " move %0, $1 \n" \ 1186 " .set pop \n" \ 1187 : "=r" (__treg)); \ 1188 __treg; \ 1189 }) 1190 1191 #define mflo2() \ 1192 ({ \ 1193 unsigned long __treg; \ 1194 \ 1195 __asm__ __volatile__( \ 1196 " .set push \n" \ 1197 " .set noat \n" \ 1198 " # mflo %0, $ac2 \n" \ 1199 " .word 0x00400812 \n" \ 1200 " move %0, $1 \n" \ 1201 " .set pop \n" \ 1202 : "=r" (__treg)); \ 1203 __treg; \ 1204 }) 1205 1206 #define mflo3() \ 1207 ({ \ 1208 unsigned long __treg; \ 1209 \ 1210 __asm__ __volatile__( \ 1211 " .set push \n" \ 1212 " .set noat \n" \ 1213 " # mflo %0, $ac3 \n" \ 1214 " .word 0x00600812 \n" \ 1215 " move %0, $1 \n" \ 1216 " .set pop \n" \ 1217 : "=r" (__treg)); \ 1218 __treg; \ 1219 }) 1220 1221 #define mthi0(x) \ 1222 do { \ 1223 __asm__ __volatile__( \ 1224 " .set push \n" \ 1225 " .set noat \n" \ 1226 " move $1, %0 \n" \ 1227 " # mthi $1, $ac0 \n" \ 1228 " .word 0x00200011 \n" \ 1229 " .set pop \n" \ 1230 : \ 1231 : "r" (x)); \ 1232 } while (0) 1233 1234 #define mthi1(x) \ 1235 do { \ 1236 __asm__ __volatile__( \ 1237 " .set push \n" \ 1238 " .set noat \n" \ 1239 " move $1, %0 \n" \ 1240 " # mthi $1, $ac1 \n" \ 1241 " .word 0x00200811 \n" \ 1242 " .set pop \n" \ 1243 : \ 1244 : "r" (x)); \ 1245 } while (0) 1246 1247 #define mthi2(x) \ 1248 do { \ 1249 __asm__ __volatile__( \ 1250 " .set push \n" \ 1251 " .set noat \n" \ 1252 " move $1, %0 \n" \ 1253 " # mthi $1, $ac2 \n" \ 1254 " .word 0x00201011 \n" \ 1255 " .set pop \n" \ 1256 : \ 1257 : "r" (x)); \ 1258 } while (0) 1259 1260 #define mthi3(x) \ 1261 do { \ 1262 __asm__ __volatile__( \ 1263 " .set push \n" \ 1264 " .set noat \n" \ 1265 " move $1, %0 \n" \ 1266 " # mthi $1, $ac3 \n" \ 1267 " .word 0x00201811 \n" \ 1268 " .set pop \n" \ 1269 : \ 1270 : "r" (x)); \ 1271 } while (0) 1272 1273 #define mtlo0(x) \ 1274 do { \ 1275 __asm__ __volatile__( \ 1276 " .set push \n" \ 1277 " .set noat \n" \ 1278 " move $1, %0 \n" \ 1279 " # mtlo $1, $ac0 \n" \ 1280 " .word 0x00200013 \n" \ 1281 " .set pop \n" \ 1282 : \ 1283 : "r" (x)); \ 1284 } while (0) 1285 1286 #define mtlo1(x) \ 1287 do { \ 1288 __asm__ __volatile__( \ 1289 " .set push \n" \ 1290 " .set noat \n" \ 1291 " move $1, %0 \n" \ 1292 " # mtlo $1, $ac1 \n" \ 1293 " .word 0x00200813 \n" \ 1294 " .set pop \n" \ 1295 : \ 1296 : "r" (x)); \ 1297 } while (0) 1298 1299 #define mtlo2(x) \ 1300 do { \ 1301 __asm__ __volatile__( \ 1302 " .set push \n" \ 1303 " .set noat \n" \ 1304 " move $1, %0 \n" \ 1305 " # mtlo $1, $ac2 \n" \ 1306 " .word 0x00201013 \n" \ 1307 " .set pop \n" \ 1308 : \ 1309 : "r" (x)); \ 1310 } while (0) 1311 1312 #define mtlo3(x) \ 1313 do { \ 1314 __asm__ __volatile__( \ 1315 " .set push \n" \ 1316 " .set noat \n" \ 1317 " move $1, %0 \n" \ 1318 " # mtlo $1, $ac3 \n" \ 1319 " .word 0x00201813 \n" \ 1320 " .set pop \n" \ 1321 : \ 1322 : "r" (x)); \ 1323 } while (0) 1324 1325 #endif 1326 1327 /* 1328 * TLB operations. 1329 * 1330 * It is responsibility of the caller to take care of any TLB hazards. 1331 */ 1332 static inline void tlb_probe(void) 1333 { 1334 __asm__ __volatile__( 1335 ".set noreorder\n\t" 1336 "tlbp\n\t" 1337 ".set reorder"); 1338 } 1339 1340 static inline void tlb_read(void) 1341 { 1342 #if MIPS34K_MISSED_ITLB_WAR 1343 int res = 0; 1344 1345 __asm__ __volatile__( 1346 " .set push \n" 1347 " .set noreorder \n" 1348 " .set noat \n" 1349 " .set mips32r2 \n" 1350 " .word 0x41610001 # dvpe $1 \n" 1351 " move %0, $1 \n" 1352 " ehb \n" 1353 " .set pop \n" 1354 : "=r" (res)); 1355 1356 instruction_hazard(); 1357 #endif 1358 1359 __asm__ __volatile__( 1360 ".set noreorder\n\t" 1361 "tlbr\n\t" 1362 ".set reorder"); 1363 1364 #if MIPS34K_MISSED_ITLB_WAR 1365 if ((res & _ULCAST_(1))) 1366 __asm__ __volatile__( 1367 " .set push \n" 1368 " .set noreorder \n" 1369 " .set noat \n" 1370 " .set mips32r2 \n" 1371 " .word 0x41600021 # evpe \n" 1372 " ehb \n" 1373 " .set pop \n"); 1374 #endif 1375 } 1376 1377 static inline void tlb_write_indexed(void) 1378 { 1379 __asm__ __volatile__( 1380 ".set noreorder\n\t" 1381 "tlbwi\n\t" 1382 ".set reorder"); 1383 } 1384 1385 static inline void tlb_write_random(void) 1386 { 1387 __asm__ __volatile__( 1388 ".set noreorder\n\t" 1389 "tlbwr\n\t" 1390 ".set reorder"); 1391 } 1392 1393 /* 1394 * Manipulate bits in a c0 register. 1395 */ 1396 #ifndef CONFIG_MIPS_MT_SMTC 1397 /* 1398 * SMTC Linux requires shutting-down microthread scheduling 1399 * during CP0 register read-modify-write sequences. 1400 */ 1401 #define __BUILD_SET_C0(name) \ 1402 static inline unsigned int \ 1403 set_c0_##name(unsigned int set) \ 1404 { \ 1405 unsigned int res, new; \ 1406 \ 1407 res = read_c0_##name(); \ 1408 new = res | set; \ 1409 write_c0_##name(new); \ 1410 \ 1411 return res; \ 1412 } \ 1413 \ 1414 static inline unsigned int \ 1415 clear_c0_##name(unsigned int clear) \ 1416 { \ 1417 unsigned int res, new; \ 1418 \ 1419 res = read_c0_##name(); \ 1420 new = res & ~clear; \ 1421 write_c0_##name(new); \ 1422 \ 1423 return res; \ 1424 } \ 1425 \ 1426 static inline unsigned int \ 1427 change_c0_##name(unsigned int change, unsigned int val) \ 1428 { \ 1429 unsigned int res, new; \ 1430 \ 1431 res = read_c0_##name(); \ 1432 new = res & ~change; \ 1433 new |= (val & change); \ 1434 write_c0_##name(new); \ 1435 \ 1436 return res; \ 1437 } 1438 1439 #else /* SMTC versions that manage MT scheduling */ 1440 1441 #include <linux/irqflags.h> 1442 1443 /* 1444 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1445 * header file recursion. 1446 */ 1447 static inline unsigned int __dmt(void) 1448 { 1449 int res; 1450 1451 __asm__ __volatile__( 1452 " .set push \n" 1453 " .set mips32r2 \n" 1454 " .set noat \n" 1455 " .word 0x41610BC1 # dmt $1 \n" 1456 " ehb \n" 1457 " move %0, $1 \n" 1458 " .set pop \n" 1459 : "=r" (res)); 1460 1461 instruction_hazard(); 1462 1463 return res; 1464 } 1465 1466 #define __VPECONTROL_TE_SHIFT 15 1467 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1468 1469 #define __EMT_ENABLE __VPECONTROL_TE 1470 1471 static inline void __emt(unsigned int previous) 1472 { 1473 if ((previous & __EMT_ENABLE)) 1474 __asm__ __volatile__( 1475 " .set mips32r2 \n" 1476 " .word 0x41600be1 # emt \n" 1477 " ehb \n" 1478 " .set mips0 \n"); 1479 } 1480 1481 static inline void __ehb(void) 1482 { 1483 __asm__ __volatile__( 1484 " .set mips32r2 \n" 1485 " ehb \n" " .set mips0 \n"); 1486 } 1487 1488 /* 1489 * Note that local_irq_save/restore affect TC-specific IXMT state, 1490 * not Status.IE as in non-SMTC kernel. 1491 */ 1492 1493 #define __BUILD_SET_C0(name) \ 1494 static inline unsigned int \ 1495 set_c0_##name(unsigned int set) \ 1496 { \ 1497 unsigned int res; \ 1498 unsigned int new; \ 1499 unsigned int omt; \ 1500 unsigned long flags; \ 1501 \ 1502 local_irq_save(flags); \ 1503 omt = __dmt(); \ 1504 res = read_c0_##name(); \ 1505 new = res | set; \ 1506 write_c0_##name(new); \ 1507 __emt(omt); \ 1508 local_irq_restore(flags); \ 1509 \ 1510 return res; \ 1511 } \ 1512 \ 1513 static inline unsigned int \ 1514 clear_c0_##name(unsigned int clear) \ 1515 { \ 1516 unsigned int res; \ 1517 unsigned int new; \ 1518 unsigned int omt; \ 1519 unsigned long flags; \ 1520 \ 1521 local_irq_save(flags); \ 1522 omt = __dmt(); \ 1523 res = read_c0_##name(); \ 1524 new = res & ~clear; \ 1525 write_c0_##name(new); \ 1526 __emt(omt); \ 1527 local_irq_restore(flags); \ 1528 \ 1529 return res; \ 1530 } \ 1531 \ 1532 static inline unsigned int \ 1533 change_c0_##name(unsigned int change, unsigned int newbits) \ 1534 { \ 1535 unsigned int res; \ 1536 unsigned int new; \ 1537 unsigned int omt; \ 1538 unsigned long flags; \ 1539 \ 1540 local_irq_save(flags); \ 1541 \ 1542 omt = __dmt(); \ 1543 res = read_c0_##name(); \ 1544 new = res & ~change; \ 1545 new |= (newbits & change); \ 1546 write_c0_##name(new); \ 1547 __emt(omt); \ 1548 local_irq_restore(flags); \ 1549 \ 1550 return res; \ 1551 } 1552 #endif 1553 1554 __BUILD_SET_C0(status) 1555 __BUILD_SET_C0(cause) 1556 __BUILD_SET_C0(config) 1557 __BUILD_SET_C0(intcontrol) 1558 __BUILD_SET_C0(intctl) 1559 __BUILD_SET_C0(srsmap) 1560 1561 #endif /* !__ASSEMBLY__ */ 1562 1563 #endif /* _ASM_MIPSREGS_H */ 1564