1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 */ 13 #ifndef _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <linux/types.h> 18 #include <asm/hazards.h> 19 #include <asm/war.h> 20 21 /* 22 * The following macros are especially useful for __asm__ 23 * inline assembler. 24 */ 25 #ifndef __STR 26 #define __STR(x) #x 27 #endif 28 #ifndef STR 29 #define STR(x) __STR(x) 30 #endif 31 32 /* 33 * Configure language 34 */ 35 #ifdef __ASSEMBLY__ 36 #define _ULCAST_ 37 #else 38 #define _ULCAST_ (unsigned long) 39 #endif 40 41 /* 42 * Coprocessor 0 register names 43 */ 44 #define CP0_INDEX $0 45 #define CP0_RANDOM $1 46 #define CP0_ENTRYLO0 $2 47 #define CP0_ENTRYLO1 $3 48 #define CP0_CONF $3 49 #define CP0_CONTEXT $4 50 #define CP0_PAGEMASK $5 51 #define CP0_WIRED $6 52 #define CP0_INFO $7 53 #define CP0_HWRENA $7, 0 54 #define CP0_BADVADDR $8 55 #define CP0_BADINSTR $8, 1 56 #define CP0_COUNT $9 57 #define CP0_ENTRYHI $10 58 #define CP0_COMPARE $11 59 #define CP0_STATUS $12 60 #define CP0_CAUSE $13 61 #define CP0_EPC $14 62 #define CP0_PRID $15 63 #define CP0_EBASE $15, 1 64 #define CP0_CMGCRBASE $15, 3 65 #define CP0_CONFIG $16 66 #define CP0_CONFIG3 $16, 3 67 #define CP0_CONFIG5 $16, 5 68 #define CP0_LLADDR $17 69 #define CP0_WATCHLO $18 70 #define CP0_WATCHHI $19 71 #define CP0_XCONTEXT $20 72 #define CP0_FRAMEMASK $21 73 #define CP0_DIAGNOSTIC $22 74 #define CP0_DEBUG $23 75 #define CP0_DEPC $24 76 #define CP0_PERFORMANCE $25 77 #define CP0_ECC $26 78 #define CP0_CACHEERR $27 79 #define CP0_TAGLO $28 80 #define CP0_TAGHI $29 81 #define CP0_ERROREPC $30 82 #define CP0_DESAVE $31 83 84 /* 85 * R4640/R4650 cp0 register names. These registers are listed 86 * here only for completeness; without MMU these CPUs are not useable 87 * by Linux. A future ELKS port might take make Linux run on them 88 * though ... 89 */ 90 #define CP0_IBASE $0 91 #define CP0_IBOUND $1 92 #define CP0_DBASE $2 93 #define CP0_DBOUND $3 94 #define CP0_CALG $17 95 #define CP0_IWATCH $18 96 #define CP0_DWATCH $19 97 98 /* 99 * Coprocessor 0 Set 1 register names 100 */ 101 #define CP0_S1_DERRADDR0 $26 102 #define CP0_S1_DERRADDR1 $27 103 #define CP0_S1_INTCONTROL $20 104 105 /* 106 * Coprocessor 0 Set 2 register names 107 */ 108 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 109 110 /* 111 * Coprocessor 0 Set 3 register names 112 */ 113 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 114 115 /* 116 * TX39 Series 117 */ 118 #define CP0_TX39_CACHE $7 119 120 121 /* Generic EntryLo bit definitions */ 122 #define ENTRYLO_G (_ULCAST_(1) << 0) 123 #define ENTRYLO_V (_ULCAST_(1) << 1) 124 #define ENTRYLO_D (_ULCAST_(1) << 2) 125 #define ENTRYLO_C_SHIFT 3 126 #define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT) 127 128 /* R3000 EntryLo bit definitions */ 129 #define R3K_ENTRYLO_G (_ULCAST_(1) << 8) 130 #define R3K_ENTRYLO_V (_ULCAST_(1) << 9) 131 #define R3K_ENTRYLO_D (_ULCAST_(1) << 10) 132 #define R3K_ENTRYLO_N (_ULCAST_(1) << 11) 133 134 /* MIPS32/64 EntryLo bit definitions */ 135 #define MIPS_ENTRYLO_PFN_SHIFT 6 136 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2)) 137 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1)) 138 139 /* 140 * Values for PageMask register 141 */ 142 #ifdef CONFIG_CPU_VR41XX 143 144 /* Why doesn't stupidity hurt ... */ 145 146 #define PM_1K 0x00000000 147 #define PM_4K 0x00001800 148 #define PM_16K 0x00007800 149 #define PM_64K 0x0001f800 150 #define PM_256K 0x0007f800 151 152 #else 153 154 #define PM_4K 0x00000000 155 #define PM_8K 0x00002000 156 #define PM_16K 0x00006000 157 #define PM_32K 0x0000e000 158 #define PM_64K 0x0001e000 159 #define PM_128K 0x0003e000 160 #define PM_256K 0x0007e000 161 #define PM_512K 0x000fe000 162 #define PM_1M 0x001fe000 163 #define PM_2M 0x003fe000 164 #define PM_4M 0x007fe000 165 #define PM_8M 0x00ffe000 166 #define PM_16M 0x01ffe000 167 #define PM_32M 0x03ffe000 168 #define PM_64M 0x07ffe000 169 #define PM_256M 0x1fffe000 170 #define PM_1G 0x7fffe000 171 172 #endif 173 174 /* 175 * Default page size for a given kernel configuration 176 */ 177 #ifdef CONFIG_PAGE_SIZE_4KB 178 #define PM_DEFAULT_MASK PM_4K 179 #elif defined(CONFIG_PAGE_SIZE_8KB) 180 #define PM_DEFAULT_MASK PM_8K 181 #elif defined(CONFIG_PAGE_SIZE_16KB) 182 #define PM_DEFAULT_MASK PM_16K 183 #elif defined(CONFIG_PAGE_SIZE_32KB) 184 #define PM_DEFAULT_MASK PM_32K 185 #elif defined(CONFIG_PAGE_SIZE_64KB) 186 #define PM_DEFAULT_MASK PM_64K 187 #else 188 #error Bad page size configuration! 189 #endif 190 191 /* 192 * Default huge tlb size for a given kernel configuration 193 */ 194 #ifdef CONFIG_PAGE_SIZE_4KB 195 #define PM_HUGE_MASK PM_1M 196 #elif defined(CONFIG_PAGE_SIZE_8KB) 197 #define PM_HUGE_MASK PM_4M 198 #elif defined(CONFIG_PAGE_SIZE_16KB) 199 #define PM_HUGE_MASK PM_16M 200 #elif defined(CONFIG_PAGE_SIZE_32KB) 201 #define PM_HUGE_MASK PM_64M 202 #elif defined(CONFIG_PAGE_SIZE_64KB) 203 #define PM_HUGE_MASK PM_256M 204 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 205 #error Bad page size configuration for hugetlbfs! 206 #endif 207 208 /* 209 * Values used for computation of new tlb entries 210 */ 211 #define PL_4K 12 212 #define PL_16K 14 213 #define PL_64K 16 214 #define PL_256K 18 215 #define PL_1M 20 216 #define PL_4M 22 217 #define PL_16M 24 218 #define PL_64M 26 219 #define PL_256M 28 220 221 /* 222 * PageGrain bits 223 */ 224 #define PG_RIE (_ULCAST_(1) << 31) 225 #define PG_XIE (_ULCAST_(1) << 30) 226 #define PG_ELPA (_ULCAST_(1) << 29) 227 #define PG_ESP (_ULCAST_(1) << 28) 228 #define PG_IEC (_ULCAST_(1) << 27) 229 230 /* MIPS32/64 EntryHI bit definitions */ 231 #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 232 233 /* 234 * R4x00 interrupt enable / cause bits 235 */ 236 #define IE_SW0 (_ULCAST_(1) << 8) 237 #define IE_SW1 (_ULCAST_(1) << 9) 238 #define IE_IRQ0 (_ULCAST_(1) << 10) 239 #define IE_IRQ1 (_ULCAST_(1) << 11) 240 #define IE_IRQ2 (_ULCAST_(1) << 12) 241 #define IE_IRQ3 (_ULCAST_(1) << 13) 242 #define IE_IRQ4 (_ULCAST_(1) << 14) 243 #define IE_IRQ5 (_ULCAST_(1) << 15) 244 245 /* 246 * R4x00 interrupt cause bits 247 */ 248 #define C_SW0 (_ULCAST_(1) << 8) 249 #define C_SW1 (_ULCAST_(1) << 9) 250 #define C_IRQ0 (_ULCAST_(1) << 10) 251 #define C_IRQ1 (_ULCAST_(1) << 11) 252 #define C_IRQ2 (_ULCAST_(1) << 12) 253 #define C_IRQ3 (_ULCAST_(1) << 13) 254 #define C_IRQ4 (_ULCAST_(1) << 14) 255 #define C_IRQ5 (_ULCAST_(1) << 15) 256 257 /* 258 * Bitfields in the R4xx0 cp0 status register 259 */ 260 #define ST0_IE 0x00000001 261 #define ST0_EXL 0x00000002 262 #define ST0_ERL 0x00000004 263 #define ST0_KSU 0x00000018 264 # define KSU_USER 0x00000010 265 # define KSU_SUPERVISOR 0x00000008 266 # define KSU_KERNEL 0x00000000 267 #define ST0_UX 0x00000020 268 #define ST0_SX 0x00000040 269 #define ST0_KX 0x00000080 270 #define ST0_DE 0x00010000 271 #define ST0_CE 0x00020000 272 273 /* 274 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 275 * cacheops in userspace. This bit exists only on RM7000 and RM9000 276 * processors. 277 */ 278 #define ST0_CO 0x08000000 279 280 /* 281 * Bitfields in the R[23]000 cp0 status register. 282 */ 283 #define ST0_IEC 0x00000001 284 #define ST0_KUC 0x00000002 285 #define ST0_IEP 0x00000004 286 #define ST0_KUP 0x00000008 287 #define ST0_IEO 0x00000010 288 #define ST0_KUO 0x00000020 289 /* bits 6 & 7 are reserved on R[23]000 */ 290 #define ST0_ISC 0x00010000 291 #define ST0_SWC 0x00020000 292 #define ST0_CM 0x00080000 293 294 /* 295 * Bits specific to the R4640/R4650 296 */ 297 #define ST0_UM (_ULCAST_(1) << 4) 298 #define ST0_IL (_ULCAST_(1) << 23) 299 #define ST0_DL (_ULCAST_(1) << 24) 300 301 /* 302 * Enable the MIPS MDMX and DSP ASEs 303 */ 304 #define ST0_MX 0x01000000 305 306 /* 307 * Status register bits available in all MIPS CPUs. 308 */ 309 #define ST0_IM 0x0000ff00 310 #define STATUSB_IP0 8 311 #define STATUSF_IP0 (_ULCAST_(1) << 8) 312 #define STATUSB_IP1 9 313 #define STATUSF_IP1 (_ULCAST_(1) << 9) 314 #define STATUSB_IP2 10 315 #define STATUSF_IP2 (_ULCAST_(1) << 10) 316 #define STATUSB_IP3 11 317 #define STATUSF_IP3 (_ULCAST_(1) << 11) 318 #define STATUSB_IP4 12 319 #define STATUSF_IP4 (_ULCAST_(1) << 12) 320 #define STATUSB_IP5 13 321 #define STATUSF_IP5 (_ULCAST_(1) << 13) 322 #define STATUSB_IP6 14 323 #define STATUSF_IP6 (_ULCAST_(1) << 14) 324 #define STATUSB_IP7 15 325 #define STATUSF_IP7 (_ULCAST_(1) << 15) 326 #define STATUSB_IP8 0 327 #define STATUSF_IP8 (_ULCAST_(1) << 0) 328 #define STATUSB_IP9 1 329 #define STATUSF_IP9 (_ULCAST_(1) << 1) 330 #define STATUSB_IP10 2 331 #define STATUSF_IP10 (_ULCAST_(1) << 2) 332 #define STATUSB_IP11 3 333 #define STATUSF_IP11 (_ULCAST_(1) << 3) 334 #define STATUSB_IP12 4 335 #define STATUSF_IP12 (_ULCAST_(1) << 4) 336 #define STATUSB_IP13 5 337 #define STATUSF_IP13 (_ULCAST_(1) << 5) 338 #define STATUSB_IP14 6 339 #define STATUSF_IP14 (_ULCAST_(1) << 6) 340 #define STATUSB_IP15 7 341 #define STATUSF_IP15 (_ULCAST_(1) << 7) 342 #define ST0_CH 0x00040000 343 #define ST0_NMI 0x00080000 344 #define ST0_SR 0x00100000 345 #define ST0_TS 0x00200000 346 #define ST0_BEV 0x00400000 347 #define ST0_RE 0x02000000 348 #define ST0_FR 0x04000000 349 #define ST0_CU 0xf0000000 350 #define ST0_CU0 0x10000000 351 #define ST0_CU1 0x20000000 352 #define ST0_CU2 0x40000000 353 #define ST0_CU3 0x80000000 354 #define ST0_XX 0x80000000 /* MIPS IV naming */ 355 356 /* 357 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 358 */ 359 #define INTCTLB_IPFDC 23 360 #define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC) 361 #define INTCTLB_IPPCI 26 362 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 363 #define INTCTLB_IPTI 29 364 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 365 366 /* 367 * Bitfields and bit numbers in the coprocessor 0 cause register. 368 * 369 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 370 */ 371 #define CAUSEB_EXCCODE 2 372 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 373 #define CAUSEB_IP 8 374 #define CAUSEF_IP (_ULCAST_(255) << 8) 375 #define CAUSEB_IP0 8 376 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 377 #define CAUSEB_IP1 9 378 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 379 #define CAUSEB_IP2 10 380 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 381 #define CAUSEB_IP3 11 382 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 383 #define CAUSEB_IP4 12 384 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 385 #define CAUSEB_IP5 13 386 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 387 #define CAUSEB_IP6 14 388 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 389 #define CAUSEB_IP7 15 390 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 391 #define CAUSEB_FDCI 21 392 #define CAUSEF_FDCI (_ULCAST_(1) << 21) 393 #define CAUSEB_IV 23 394 #define CAUSEF_IV (_ULCAST_(1) << 23) 395 #define CAUSEB_PCI 26 396 #define CAUSEF_PCI (_ULCAST_(1) << 26) 397 #define CAUSEB_DC 27 398 #define CAUSEF_DC (_ULCAST_(1) << 27) 399 #define CAUSEB_CE 28 400 #define CAUSEF_CE (_ULCAST_(3) << 28) 401 #define CAUSEB_TI 30 402 #define CAUSEF_TI (_ULCAST_(1) << 30) 403 #define CAUSEB_BD 31 404 #define CAUSEF_BD (_ULCAST_(1) << 31) 405 406 /* 407 * Cause.ExcCode trap codes. 408 */ 409 #define EXCCODE_INT 0 /* Interrupt pending */ 410 #define EXCCODE_MOD 1 /* TLB modified fault */ 411 #define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */ 412 #define EXCCODE_TLBS 3 /* TLB miss on a store */ 413 #define EXCCODE_ADEL 4 /* Address error on a load or ifetch */ 414 #define EXCCODE_ADES 5 /* Address error on a store */ 415 #define EXCCODE_IBE 6 /* Bus error on an ifetch */ 416 #define EXCCODE_DBE 7 /* Bus error on a load or store */ 417 #define EXCCODE_SYS 8 /* System call */ 418 #define EXCCODE_BP 9 /* Breakpoint */ 419 #define EXCCODE_RI 10 /* Reserved instruction exception */ 420 #define EXCCODE_CPU 11 /* Coprocessor unusable */ 421 #define EXCCODE_OV 12 /* Arithmetic overflow */ 422 #define EXCCODE_TR 13 /* Trap instruction */ 423 #define EXCCODE_MSAFPE 14 /* MSA floating point exception */ 424 #define EXCCODE_FPE 15 /* Floating point exception */ 425 #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */ 426 #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */ 427 #define EXCCODE_MSADIS 21 /* MSA disabled exception */ 428 #define EXCCODE_MDMX 22 /* MDMX unusable exception */ 429 #define EXCCODE_WATCH 23 /* Watch address reference */ 430 #define EXCCODE_MCHECK 24 /* Machine check */ 431 #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */ 432 #define EXCCODE_DSPDIS 26 /* DSP disabled exception */ 433 #define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */ 434 435 /* Implementation specific trap codes used by MIPS cores */ 436 #define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */ 437 438 /* 439 * Bits in the coprocessor 0 config register. 440 */ 441 /* Generic bits. */ 442 #define CONF_CM_CACHABLE_NO_WA 0 443 #define CONF_CM_CACHABLE_WA 1 444 #define CONF_CM_UNCACHED 2 445 #define CONF_CM_CACHABLE_NONCOHERENT 3 446 #define CONF_CM_CACHABLE_CE 4 447 #define CONF_CM_CACHABLE_COW 5 448 #define CONF_CM_CACHABLE_CUW 6 449 #define CONF_CM_CACHABLE_ACCELERATED 7 450 #define CONF_CM_CMASK 7 451 #define CONF_BE (_ULCAST_(1) << 15) 452 453 /* Bits common to various processors. */ 454 #define CONF_CU (_ULCAST_(1) << 3) 455 #define CONF_DB (_ULCAST_(1) << 4) 456 #define CONF_IB (_ULCAST_(1) << 5) 457 #define CONF_DC (_ULCAST_(7) << 6) 458 #define CONF_IC (_ULCAST_(7) << 9) 459 #define CONF_EB (_ULCAST_(1) << 13) 460 #define CONF_EM (_ULCAST_(1) << 14) 461 #define CONF_SM (_ULCAST_(1) << 16) 462 #define CONF_SC (_ULCAST_(1) << 17) 463 #define CONF_EW (_ULCAST_(3) << 18) 464 #define CONF_EP (_ULCAST_(15)<< 24) 465 #define CONF_EC (_ULCAST_(7) << 28) 466 #define CONF_CM (_ULCAST_(1) << 31) 467 468 /* Bits specific to the R4xx0. */ 469 #define R4K_CONF_SW (_ULCAST_(1) << 20) 470 #define R4K_CONF_SS (_ULCAST_(1) << 21) 471 #define R4K_CONF_SB (_ULCAST_(3) << 22) 472 473 /* Bits specific to the R5000. */ 474 #define R5K_CONF_SE (_ULCAST_(1) << 12) 475 #define R5K_CONF_SS (_ULCAST_(3) << 20) 476 477 /* Bits specific to the RM7000. */ 478 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 479 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 480 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 481 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 482 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 483 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 484 485 /* Bits specific to the R10000. */ 486 #define R10K_CONF_DN (_ULCAST_(3) << 3) 487 #define R10K_CONF_CT (_ULCAST_(1) << 5) 488 #define R10K_CONF_PE (_ULCAST_(1) << 6) 489 #define R10K_CONF_PM (_ULCAST_(3) << 7) 490 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 491 #define R10K_CONF_SB (_ULCAST_(1) << 13) 492 #define R10K_CONF_SK (_ULCAST_(1) << 14) 493 #define R10K_CONF_SS (_ULCAST_(7) << 16) 494 #define R10K_CONF_SC (_ULCAST_(7) << 19) 495 #define R10K_CONF_DC (_ULCAST_(7) << 26) 496 #define R10K_CONF_IC (_ULCAST_(7) << 29) 497 498 /* Bits specific to the VR41xx. */ 499 #define VR41_CONF_CS (_ULCAST_(1) << 12) 500 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 501 #define VR41_CONF_BP (_ULCAST_(1) << 16) 502 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 503 #define VR41_CONF_AD (_ULCAST_(1) << 23) 504 505 /* Bits specific to the R30xx. */ 506 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 507 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 508 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 509 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 510 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 511 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 512 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 513 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 514 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 515 516 /* Bits specific to the TX49. */ 517 #define TX49_CONF_DC (_ULCAST_(1) << 16) 518 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 519 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 520 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 521 522 /* Bits specific to the MIPS32/64 PRA. */ 523 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 524 #define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7) 525 #define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7) 526 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 527 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 528 #define MIPS_CONF_M (_ULCAST_(1) << 31) 529 530 /* 531 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 532 */ 533 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 534 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 535 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 536 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 537 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 538 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 539 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 540 #define MIPS_CONF1_DA_SHF 7 541 #define MIPS_CONF1_DA_SZ 3 542 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 543 #define MIPS_CONF1_DL_SHF 10 544 #define MIPS_CONF1_DL_SZ 3 545 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 546 #define MIPS_CONF1_DS_SHF 13 547 #define MIPS_CONF1_DS_SZ 3 548 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 549 #define MIPS_CONF1_IA_SHF 16 550 #define MIPS_CONF1_IA_SZ 3 551 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 552 #define MIPS_CONF1_IL_SHF 19 553 #define MIPS_CONF1_IL_SZ 3 554 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 555 #define MIPS_CONF1_IS_SHF 22 556 #define MIPS_CONF1_IS_SZ 3 557 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 558 #define MIPS_CONF1_TLBS_SHIFT (25) 559 #define MIPS_CONF1_TLBS_SIZE (6) 560 #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) 561 562 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 563 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 564 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 565 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 566 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 567 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 568 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 569 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 570 571 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 572 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 573 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 574 #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) 575 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 576 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 577 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 578 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 579 #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) 580 #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 581 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 582 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 583 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 584 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 585 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 586 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 587 #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) 588 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) 589 #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) 590 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 591 #define MIPS_CONF3_PW (_ULCAST_(1) << 24) 592 #define MIPS_CONF3_SC (_ULCAST_(1) << 25) 593 #define MIPS_CONF3_BI (_ULCAST_(1) << 26) 594 #define MIPS_CONF3_BP (_ULCAST_(1) << 27) 595 #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) 596 #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) 597 #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) 598 599 #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 600 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 601 #define MIPS_CONF4_FTLBSETS_SHIFT (0) 602 #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 603 #define MIPS_CONF4_FTLBWAYS_SHIFT (4) 604 #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 605 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) 606 /* bits 10:8 in FTLB-only configurations */ 607 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 608 /* bits 12:8 in VTLB-FTLB only configurations */ 609 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 610 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 611 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 612 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) 613 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) 614 #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) 615 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) 616 #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) 617 #define MIPS_CONF4_AE (_ULCAST_(1) << 28) 618 #define MIPS_CONF4_IE (_ULCAST_(3) << 29) 619 #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) 620 621 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 622 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) 623 #define MIPS_CONF5_MRP (_ULCAST_(1) << 3) 624 #define MIPS_CONF5_LLB (_ULCAST_(1) << 4) 625 #define MIPS_CONF5_MVH (_ULCAST_(1) << 5) 626 #define MIPS_CONF5_FRE (_ULCAST_(1) << 8) 627 #define MIPS_CONF5_UFE (_ULCAST_(1) << 9) 628 #define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 629 #define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 630 #define MIPS_CONF5_CV (_ULCAST_(1) << 29) 631 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 632 633 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 634 /* proAptiv FTLB on/off bit */ 635 #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) 636 /* FTLB probability bits */ 637 #define MIPS_CONF6_FTLBP_SHIFT (16) 638 639 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 640 641 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 642 643 #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 644 #define MIPS_CONF7_AR (_ULCAST_(1) << 16) 645 /* FTLB probability bits for R6 */ 646 #define MIPS_CONF7_FTLBP_SHIFT (18) 647 648 /* MAAR bit definitions */ 649 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12) 650 #define MIPS_MAAR_ADDR_SHIFT 12 651 #define MIPS_MAAR_S (_ULCAST_(1) << 1) 652 #define MIPS_MAAR_V (_ULCAST_(1) << 0) 653 654 /* CMGCRBase bit definitions */ 655 #define MIPS_CMGCRB_BASE 11 656 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) 657 658 /* 659 * Bits in the MIPS32 Memory Segmentation registers. 660 */ 661 #define MIPS_SEGCFG_PA_SHIFT 9 662 #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) 663 #define MIPS_SEGCFG_AM_SHIFT 4 664 #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) 665 #define MIPS_SEGCFG_EU_SHIFT 3 666 #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) 667 #define MIPS_SEGCFG_C_SHIFT 0 668 #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) 669 670 #define MIPS_SEGCFG_UUSK _ULCAST_(7) 671 #define MIPS_SEGCFG_USK _ULCAST_(5) 672 #define MIPS_SEGCFG_MUSUK _ULCAST_(4) 673 #define MIPS_SEGCFG_MUSK _ULCAST_(3) 674 #define MIPS_SEGCFG_MSK _ULCAST_(2) 675 #define MIPS_SEGCFG_MK _ULCAST_(1) 676 #define MIPS_SEGCFG_UK _ULCAST_(0) 677 678 #define MIPS_PWFIELD_GDI_SHIFT 24 679 #define MIPS_PWFIELD_GDI_MASK 0x3f000000 680 #define MIPS_PWFIELD_UDI_SHIFT 18 681 #define MIPS_PWFIELD_UDI_MASK 0x00fc0000 682 #define MIPS_PWFIELD_MDI_SHIFT 12 683 #define MIPS_PWFIELD_MDI_MASK 0x0003f000 684 #define MIPS_PWFIELD_PTI_SHIFT 6 685 #define MIPS_PWFIELD_PTI_MASK 0x00000fc0 686 #define MIPS_PWFIELD_PTEI_SHIFT 0 687 #define MIPS_PWFIELD_PTEI_MASK 0x0000003f 688 689 #define MIPS_PWSIZE_GDW_SHIFT 24 690 #define MIPS_PWSIZE_GDW_MASK 0x3f000000 691 #define MIPS_PWSIZE_UDW_SHIFT 18 692 #define MIPS_PWSIZE_UDW_MASK 0x00fc0000 693 #define MIPS_PWSIZE_MDW_SHIFT 12 694 #define MIPS_PWSIZE_MDW_MASK 0x0003f000 695 #define MIPS_PWSIZE_PTW_SHIFT 6 696 #define MIPS_PWSIZE_PTW_MASK 0x00000fc0 697 #define MIPS_PWSIZE_PTEW_SHIFT 0 698 #define MIPS_PWSIZE_PTEW_MASK 0x0000003f 699 700 #define MIPS_PWCTL_PWEN_SHIFT 31 701 #define MIPS_PWCTL_PWEN_MASK 0x80000000 702 #define MIPS_PWCTL_DPH_SHIFT 7 703 #define MIPS_PWCTL_DPH_MASK 0x00000080 704 #define MIPS_PWCTL_HUGEPG_SHIFT 6 705 #define MIPS_PWCTL_HUGEPG_MASK 0x00000060 706 #define MIPS_PWCTL_PSN_SHIFT 0 707 #define MIPS_PWCTL_PSN_MASK 0x0000003f 708 709 /* CDMMBase register bit definitions */ 710 #define MIPS_CDMMBASE_SIZE_SHIFT 0 711 #define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT) 712 #define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9) 713 #define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10) 714 #define MIPS_CDMMBASE_ADDR_SHIFT 11 715 #define MIPS_CDMMBASE_ADDR_START 15 716 717 /* 718 * Bitfields in the TX39 family CP0 Configuration Register 3 719 */ 720 #define TX39_CONF_ICS_SHIFT 19 721 #define TX39_CONF_ICS_MASK 0x00380000 722 #define TX39_CONF_ICS_1KB 0x00000000 723 #define TX39_CONF_ICS_2KB 0x00080000 724 #define TX39_CONF_ICS_4KB 0x00100000 725 #define TX39_CONF_ICS_8KB 0x00180000 726 #define TX39_CONF_ICS_16KB 0x00200000 727 728 #define TX39_CONF_DCS_SHIFT 16 729 #define TX39_CONF_DCS_MASK 0x00070000 730 #define TX39_CONF_DCS_1KB 0x00000000 731 #define TX39_CONF_DCS_2KB 0x00010000 732 #define TX39_CONF_DCS_4KB 0x00020000 733 #define TX39_CONF_DCS_8KB 0x00030000 734 #define TX39_CONF_DCS_16KB 0x00040000 735 736 #define TX39_CONF_CWFON 0x00004000 737 #define TX39_CONF_WBON 0x00002000 738 #define TX39_CONF_RF_SHIFT 10 739 #define TX39_CONF_RF_MASK 0x00000c00 740 #define TX39_CONF_DOZE 0x00000200 741 #define TX39_CONF_HALT 0x00000100 742 #define TX39_CONF_LOCK 0x00000080 743 #define TX39_CONF_ICE 0x00000020 744 #define TX39_CONF_DCE 0x00000010 745 #define TX39_CONF_IRSIZE_SHIFT 2 746 #define TX39_CONF_IRSIZE_MASK 0x0000000c 747 #define TX39_CONF_DRSIZE_SHIFT 0 748 #define TX39_CONF_DRSIZE_MASK 0x00000003 749 750 /* 751 * Interesting Bits in the R10K CP0 Branch Diagnostic Register 752 */ 753 /* Disable Branch Target Address Cache */ 754 #define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27) 755 /* Enable Branch Prediction Global History */ 756 #define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26) 757 /* Disable Branch Return Cache */ 758 #define R10K_DIAG_D_BRC (_ULCAST_(1) << 22) 759 760 /* 761 * Coprocessor 1 (FPU) register names 762 */ 763 #define CP1_REVISION $0 764 #define CP1_UFR $1 765 #define CP1_UNFR $4 766 #define CP1_FCCR $25 767 #define CP1_FEXR $26 768 #define CP1_FENR $28 769 #define CP1_STATUS $31 770 771 772 /* 773 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 774 */ 775 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 776 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 777 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 778 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 779 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 780 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 781 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 782 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) 783 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) 784 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) 785 786 /* 787 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. 788 */ 789 #define MIPS_FCCR_CONDX_S 0 790 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) 791 #define MIPS_FCCR_COND0_S 0 792 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) 793 #define MIPS_FCCR_COND1_S 1 794 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) 795 #define MIPS_FCCR_COND2_S 2 796 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) 797 #define MIPS_FCCR_COND3_S 3 798 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) 799 #define MIPS_FCCR_COND4_S 4 800 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) 801 #define MIPS_FCCR_COND5_S 5 802 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) 803 #define MIPS_FCCR_COND6_S 6 804 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) 805 #define MIPS_FCCR_COND7_S 7 806 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) 807 808 /* 809 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. 810 */ 811 #define MIPS_FENR_FS_S 2 812 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) 813 814 /* 815 * FPU Status Register Values 816 */ 817 #define FPU_CSR_COND_S 23 /* $fcc0 */ 818 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) 819 820 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ 821 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) 822 823 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ 824 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) 825 #define FPU_CSR_COND1_S 25 /* $fcc1 */ 826 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) 827 #define FPU_CSR_COND2_S 26 /* $fcc2 */ 828 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) 829 #define FPU_CSR_COND3_S 27 /* $fcc3 */ 830 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) 831 #define FPU_CSR_COND4_S 28 /* $fcc4 */ 832 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) 833 #define FPU_CSR_COND5_S 29 /* $fcc5 */ 834 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) 835 #define FPU_CSR_COND6_S 30 /* $fcc6 */ 836 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) 837 #define FPU_CSR_COND7_S 31 /* $fcc7 */ 838 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) 839 840 /* 841 * Bits 22:20 of the FPU Status Register will be read as 0, 842 * and should be written as zero. 843 */ 844 #define FPU_CSR_RSVD (_ULCAST_(7) << 20) 845 846 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) 847 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) 848 849 /* 850 * X the exception cause indicator 851 * E the exception enable 852 * S the sticky/flag bit 853 */ 854 #define FPU_CSR_ALL_X 0x0003f000 855 #define FPU_CSR_UNI_X 0x00020000 856 #define FPU_CSR_INV_X 0x00010000 857 #define FPU_CSR_DIV_X 0x00008000 858 #define FPU_CSR_OVF_X 0x00004000 859 #define FPU_CSR_UDF_X 0x00002000 860 #define FPU_CSR_INE_X 0x00001000 861 862 #define FPU_CSR_ALL_E 0x00000f80 863 #define FPU_CSR_INV_E 0x00000800 864 #define FPU_CSR_DIV_E 0x00000400 865 #define FPU_CSR_OVF_E 0x00000200 866 #define FPU_CSR_UDF_E 0x00000100 867 #define FPU_CSR_INE_E 0x00000080 868 869 #define FPU_CSR_ALL_S 0x0000007c 870 #define FPU_CSR_INV_S 0x00000040 871 #define FPU_CSR_DIV_S 0x00000020 872 #define FPU_CSR_OVF_S 0x00000010 873 #define FPU_CSR_UDF_S 0x00000008 874 #define FPU_CSR_INE_S 0x00000004 875 876 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 877 #define FPU_CSR_RM 0x00000003 878 #define FPU_CSR_RN 0x0 /* nearest */ 879 #define FPU_CSR_RZ 0x1 /* towards zero */ 880 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 881 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 882 883 884 #ifndef __ASSEMBLY__ 885 886 /* 887 * Macros for handling the ISA mode bit for MIPS16 and microMIPS. 888 */ 889 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \ 890 defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 891 #define get_isa16_mode(x) ((x) & 0x1) 892 #define msk_isa16_mode(x) ((x) & ~0x1) 893 #define set_isa16_mode(x) do { (x) |= 0x1; } while(0) 894 #else 895 #define get_isa16_mode(x) 0 896 #define msk_isa16_mode(x) (x) 897 #define set_isa16_mode(x) do { } while(0) 898 #endif 899 900 /* 901 * microMIPS instructions can be 16-bit or 32-bit in length. This 902 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit. 903 */ 904 static inline int mm_insn_16bit(u16 insn) 905 { 906 u16 opcode = (insn >> 10) & 0x7; 907 908 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 909 } 910 911 /* 912 * TLB Invalidate Flush 913 */ 914 static inline void tlbinvf(void) 915 { 916 __asm__ __volatile__( 917 ".set push\n\t" 918 ".set noreorder\n\t" 919 ".word 0x42000004\n\t" /* tlbinvf */ 920 ".set pop"); 921 } 922 923 924 /* 925 * Functions to access the R10000 performance counters. These are basically 926 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 927 * performance counter number encoded into bits 1 ... 5 of the instruction. 928 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 929 * disassembler these will look like an access to sel 0 or 1. 930 */ 931 #define read_r10k_perf_cntr(counter) \ 932 ({ \ 933 unsigned int __res; \ 934 __asm__ __volatile__( \ 935 "mfpc\t%0, %1" \ 936 : "=r" (__res) \ 937 : "i" (counter)); \ 938 \ 939 __res; \ 940 }) 941 942 #define write_r10k_perf_cntr(counter,val) \ 943 do { \ 944 __asm__ __volatile__( \ 945 "mtpc\t%0, %1" \ 946 : \ 947 : "r" (val), "i" (counter)); \ 948 } while (0) 949 950 #define read_r10k_perf_event(counter) \ 951 ({ \ 952 unsigned int __res; \ 953 __asm__ __volatile__( \ 954 "mfps\t%0, %1" \ 955 : "=r" (__res) \ 956 : "i" (counter)); \ 957 \ 958 __res; \ 959 }) 960 961 #define write_r10k_perf_cntl(counter,val) \ 962 do { \ 963 __asm__ __volatile__( \ 964 "mtps\t%0, %1" \ 965 : \ 966 : "r" (val), "i" (counter)); \ 967 } while (0) 968 969 970 /* 971 * Macros to access the system control coprocessor 972 */ 973 974 #define __read_32bit_c0_register(source, sel) \ 975 ({ unsigned int __res; \ 976 if (sel == 0) \ 977 __asm__ __volatile__( \ 978 "mfc0\t%0, " #source "\n\t" \ 979 : "=r" (__res)); \ 980 else \ 981 __asm__ __volatile__( \ 982 ".set\tmips32\n\t" \ 983 "mfc0\t%0, " #source ", " #sel "\n\t" \ 984 ".set\tmips0\n\t" \ 985 : "=r" (__res)); \ 986 __res; \ 987 }) 988 989 #define __read_64bit_c0_register(source, sel) \ 990 ({ unsigned long long __res; \ 991 if (sizeof(unsigned long) == 4) \ 992 __res = __read_64bit_c0_split(source, sel); \ 993 else if (sel == 0) \ 994 __asm__ __volatile__( \ 995 ".set\tmips3\n\t" \ 996 "dmfc0\t%0, " #source "\n\t" \ 997 ".set\tmips0" \ 998 : "=r" (__res)); \ 999 else \ 1000 __asm__ __volatile__( \ 1001 ".set\tmips64\n\t" \ 1002 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 1003 ".set\tmips0" \ 1004 : "=r" (__res)); \ 1005 __res; \ 1006 }) 1007 1008 #define __write_32bit_c0_register(register, sel, value) \ 1009 do { \ 1010 if (sel == 0) \ 1011 __asm__ __volatile__( \ 1012 "mtc0\t%z0, " #register "\n\t" \ 1013 : : "Jr" ((unsigned int)(value))); \ 1014 else \ 1015 __asm__ __volatile__( \ 1016 ".set\tmips32\n\t" \ 1017 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 1018 ".set\tmips0" \ 1019 : : "Jr" ((unsigned int)(value))); \ 1020 } while (0) 1021 1022 #define __write_64bit_c0_register(register, sel, value) \ 1023 do { \ 1024 if (sizeof(unsigned long) == 4) \ 1025 __write_64bit_c0_split(register, sel, value); \ 1026 else if (sel == 0) \ 1027 __asm__ __volatile__( \ 1028 ".set\tmips3\n\t" \ 1029 "dmtc0\t%z0, " #register "\n\t" \ 1030 ".set\tmips0" \ 1031 : : "Jr" (value)); \ 1032 else \ 1033 __asm__ __volatile__( \ 1034 ".set\tmips64\n\t" \ 1035 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 1036 ".set\tmips0" \ 1037 : : "Jr" (value)); \ 1038 } while (0) 1039 1040 #define __read_ulong_c0_register(reg, sel) \ 1041 ((sizeof(unsigned long) == 4) ? \ 1042 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 1043 (unsigned long) __read_64bit_c0_register(reg, sel)) 1044 1045 #define __write_ulong_c0_register(reg, sel, val) \ 1046 do { \ 1047 if (sizeof(unsigned long) == 4) \ 1048 __write_32bit_c0_register(reg, sel, val); \ 1049 else \ 1050 __write_64bit_c0_register(reg, sel, val); \ 1051 } while (0) 1052 1053 /* 1054 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 1055 */ 1056 #define __read_32bit_c0_ctrl_register(source) \ 1057 ({ unsigned int __res; \ 1058 __asm__ __volatile__( \ 1059 "cfc0\t%0, " #source "\n\t" \ 1060 : "=r" (__res)); \ 1061 __res; \ 1062 }) 1063 1064 #define __write_32bit_c0_ctrl_register(register, value) \ 1065 do { \ 1066 __asm__ __volatile__( \ 1067 "ctc0\t%z0, " #register "\n\t" \ 1068 : : "Jr" ((unsigned int)(value))); \ 1069 } while (0) 1070 1071 /* 1072 * These versions are only needed for systems with more than 38 bits of 1073 * physical address space running the 32-bit kernel. That's none atm :-) 1074 */ 1075 #define __read_64bit_c0_split(source, sel) \ 1076 ({ \ 1077 unsigned long long __val; \ 1078 unsigned long __flags; \ 1079 \ 1080 local_irq_save(__flags); \ 1081 if (sel == 0) \ 1082 __asm__ __volatile__( \ 1083 ".set\tmips64\n\t" \ 1084 "dmfc0\t%M0, " #source "\n\t" \ 1085 "dsll\t%L0, %M0, 32\n\t" \ 1086 "dsra\t%M0, %M0, 32\n\t" \ 1087 "dsra\t%L0, %L0, 32\n\t" \ 1088 ".set\tmips0" \ 1089 : "=r" (__val)); \ 1090 else \ 1091 __asm__ __volatile__( \ 1092 ".set\tmips64\n\t" \ 1093 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 1094 "dsll\t%L0, %M0, 32\n\t" \ 1095 "dsra\t%M0, %M0, 32\n\t" \ 1096 "dsra\t%L0, %L0, 32\n\t" \ 1097 ".set\tmips0" \ 1098 : "=r" (__val)); \ 1099 local_irq_restore(__flags); \ 1100 \ 1101 __val; \ 1102 }) 1103 1104 #define __write_64bit_c0_split(source, sel, val) \ 1105 do { \ 1106 unsigned long __flags; \ 1107 \ 1108 local_irq_save(__flags); \ 1109 if (sel == 0) \ 1110 __asm__ __volatile__( \ 1111 ".set\tmips64\n\t" \ 1112 "dsll\t%L0, %L0, 32\n\t" \ 1113 "dsrl\t%L0, %L0, 32\n\t" \ 1114 "dsll\t%M0, %M0, 32\n\t" \ 1115 "or\t%L0, %L0, %M0\n\t" \ 1116 "dmtc0\t%L0, " #source "\n\t" \ 1117 ".set\tmips0" \ 1118 : : "r" (val)); \ 1119 else \ 1120 __asm__ __volatile__( \ 1121 ".set\tmips64\n\t" \ 1122 "dsll\t%L0, %L0, 32\n\t" \ 1123 "dsrl\t%L0, %L0, 32\n\t" \ 1124 "dsll\t%M0, %M0, 32\n\t" \ 1125 "or\t%L0, %L0, %M0\n\t" \ 1126 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 1127 ".set\tmips0" \ 1128 : : "r" (val)); \ 1129 local_irq_restore(__flags); \ 1130 } while (0) 1131 1132 #define __readx_32bit_c0_register(source) \ 1133 ({ \ 1134 unsigned int __res; \ 1135 \ 1136 __asm__ __volatile__( \ 1137 " .set push \n" \ 1138 " .set noat \n" \ 1139 " .set mips32r2 \n" \ 1140 " .insn \n" \ 1141 " # mfhc0 $1, %1 \n" \ 1142 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \ 1143 " move %0, $1 \n" \ 1144 " .set pop \n" \ 1145 : "=r" (__res) \ 1146 : "i" (source)); \ 1147 __res; \ 1148 }) 1149 1150 #define __writex_32bit_c0_register(register, value) \ 1151 do { \ 1152 __asm__ __volatile__( \ 1153 " .set push \n" \ 1154 " .set noat \n" \ 1155 " .set mips32r2 \n" \ 1156 " move $1, %0 \n" \ 1157 " # mthc0 $1, %1 \n" \ 1158 " .insn \n" \ 1159 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \ 1160 " .set pop \n" \ 1161 : \ 1162 : "r" (value), "i" (register)); \ 1163 } while (0) 1164 1165 #define read_c0_index() __read_32bit_c0_register($0, 0) 1166 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 1167 1168 #define read_c0_random() __read_32bit_c0_register($1, 0) 1169 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 1170 1171 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 1172 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 1173 1174 #define readx_c0_entrylo0() __readx_32bit_c0_register(2) 1175 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val) 1176 1177 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 1178 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 1179 1180 #define readx_c0_entrylo1() __readx_32bit_c0_register(3) 1181 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val) 1182 1183 #define read_c0_conf() __read_32bit_c0_register($3, 0) 1184 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 1185 1186 #define read_c0_context() __read_ulong_c0_register($4, 0) 1187 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 1188 1189 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 1190 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 1191 1192 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 1193 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 1194 1195 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 1196 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 1197 1198 #define read_c0_wired() __read_32bit_c0_register($6, 0) 1199 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 1200 1201 #define read_c0_info() __read_32bit_c0_register($7, 0) 1202 1203 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 1204 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 1205 1206 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 1207 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 1208 1209 #define read_c0_count() __read_32bit_c0_register($9, 0) 1210 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 1211 1212 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 1213 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 1214 1215 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 1216 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 1217 1218 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 1219 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 1220 1221 #define read_c0_compare() __read_32bit_c0_register($11, 0) 1222 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 1223 1224 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 1225 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 1226 1227 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 1228 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 1229 1230 #define read_c0_status() __read_32bit_c0_register($12, 0) 1231 1232 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 1233 1234 #define read_c0_cause() __read_32bit_c0_register($13, 0) 1235 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 1236 1237 #define read_c0_epc() __read_ulong_c0_register($14, 0) 1238 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 1239 1240 #define read_c0_prid() __read_32bit_c0_register($15, 0) 1241 1242 #define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) 1243 1244 #define read_c0_config() __read_32bit_c0_register($16, 0) 1245 #define read_c0_config1() __read_32bit_c0_register($16, 1) 1246 #define read_c0_config2() __read_32bit_c0_register($16, 2) 1247 #define read_c0_config3() __read_32bit_c0_register($16, 3) 1248 #define read_c0_config4() __read_32bit_c0_register($16, 4) 1249 #define read_c0_config5() __read_32bit_c0_register($16, 5) 1250 #define read_c0_config6() __read_32bit_c0_register($16, 6) 1251 #define read_c0_config7() __read_32bit_c0_register($16, 7) 1252 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 1253 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 1254 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 1255 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 1256 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 1257 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 1258 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 1259 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 1260 1261 #define read_c0_lladdr() __read_ulong_c0_register($17, 0) 1262 #define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) 1263 #define read_c0_maar() __read_ulong_c0_register($17, 1) 1264 #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) 1265 #define read_c0_maari() __read_32bit_c0_register($17, 2) 1266 #define write_c0_maari(val) __write_32bit_c0_register($17, 2, val) 1267 1268 /* 1269 * The WatchLo register. There may be up to 8 of them. 1270 */ 1271 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 1272 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 1273 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 1274 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 1275 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 1276 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 1277 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 1278 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 1279 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 1280 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 1281 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 1282 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 1283 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 1284 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 1285 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 1286 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 1287 1288 /* 1289 * The WatchHi register. There may be up to 8 of them. 1290 */ 1291 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 1292 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 1293 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 1294 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 1295 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 1296 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 1297 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 1298 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 1299 1300 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 1301 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 1302 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 1303 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 1304 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 1305 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 1306 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 1307 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 1308 1309 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 1310 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 1311 1312 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 1313 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 1314 1315 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 1316 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 1317 1318 #define read_c0_diag() __read_32bit_c0_register($22, 0) 1319 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 1320 1321 /* R10K CP0 Branch Diagnostic register is 64bits wide */ 1322 #define read_c0_r10k_diag() __read_64bit_c0_register($22, 0) 1323 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val) 1324 1325 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 1326 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 1327 1328 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 1329 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 1330 1331 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 1332 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 1333 1334 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 1335 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 1336 1337 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 1338 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 1339 1340 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1341 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1342 1343 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1344 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1345 1346 /* 1347 * MIPS32 / MIPS64 performance counters 1348 */ 1349 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1350 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1351 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1352 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1353 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1354 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1355 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1356 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1357 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1358 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1359 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1360 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1361 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1362 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1363 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1364 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1365 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1366 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1367 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1368 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1369 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1370 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1371 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1372 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1373 1374 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1375 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1376 1377 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1378 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1379 1380 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1381 1382 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1383 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1384 1385 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1386 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1387 1388 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1389 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1390 1391 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1392 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1393 1394 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1395 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1396 1397 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1398 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1399 1400 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1401 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1402 1403 /* MIPSR2 */ 1404 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1405 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1406 1407 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1408 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1409 1410 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1411 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1412 1413 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1414 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1415 1416 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1417 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1418 1419 #define read_c0_cdmmbase() __read_ulong_c0_register($15, 2) 1420 #define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val) 1421 1422 /* MIPSR3 */ 1423 #define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1424 #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1425 1426 #define read_c0_segctl1() __read_32bit_c0_register($5, 3) 1427 #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) 1428 1429 #define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1430 #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1431 1432 /* Hardware Page Table Walker */ 1433 #define read_c0_pwbase() __read_ulong_c0_register($5, 5) 1434 #define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val) 1435 1436 #define read_c0_pwfield() __read_ulong_c0_register($5, 6) 1437 #define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val) 1438 1439 #define read_c0_pwsize() __read_ulong_c0_register($5, 7) 1440 #define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val) 1441 1442 #define read_c0_pwctl() __read_32bit_c0_register($6, 6) 1443 #define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val) 1444 1445 /* Cavium OCTEON (cnMIPS) */ 1446 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1447 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1448 1449 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1450 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1451 1452 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1453 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1454 /* 1455 * The cacheerr registers are not standardized. On OCTEON, they are 1456 * 64 bits wide. 1457 */ 1458 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1459 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1460 1461 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1462 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1463 1464 /* BMIPS3300 */ 1465 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1466 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1467 1468 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1469 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1470 1471 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1472 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1473 1474 /* BMIPS43xx */ 1475 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1476 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1477 1478 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1479 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1480 1481 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1482 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1483 1484 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1485 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1486 1487 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1488 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1489 1490 /* BMIPS5000 */ 1491 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1492 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1493 1494 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1495 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1496 1497 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1498 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1499 1500 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1501 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1502 1503 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1504 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1505 1506 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1507 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1508 1509 /* 1510 * Macros to access the floating point coprocessor control registers 1511 */ 1512 #define _read_32bit_cp1_register(source, gas_hardfloat) \ 1513 ({ \ 1514 unsigned int __res; \ 1515 \ 1516 __asm__ __volatile__( \ 1517 " .set push \n" \ 1518 " .set reorder \n" \ 1519 " # gas fails to assemble cfc1 for some archs, \n" \ 1520 " # like Octeon. \n" \ 1521 " .set mips1 \n" \ 1522 " "STR(gas_hardfloat)" \n" \ 1523 " cfc1 %0,"STR(source)" \n" \ 1524 " .set pop \n" \ 1525 : "=r" (__res)); \ 1526 __res; \ 1527 }) 1528 1529 #define _write_32bit_cp1_register(dest, val, gas_hardfloat) \ 1530 do { \ 1531 __asm__ __volatile__( \ 1532 " .set push \n" \ 1533 " .set reorder \n" \ 1534 " "STR(gas_hardfloat)" \n" \ 1535 " ctc1 %0,"STR(dest)" \n" \ 1536 " .set pop \n" \ 1537 : : "r" (val)); \ 1538 } while (0) 1539 1540 #ifdef GAS_HAS_SET_HARDFLOAT 1541 #define read_32bit_cp1_register(source) \ 1542 _read_32bit_cp1_register(source, .set hardfloat) 1543 #define write_32bit_cp1_register(dest, val) \ 1544 _write_32bit_cp1_register(dest, val, .set hardfloat) 1545 #else 1546 #define read_32bit_cp1_register(source) \ 1547 _read_32bit_cp1_register(source, ) 1548 #define write_32bit_cp1_register(dest, val) \ 1549 _write_32bit_cp1_register(dest, val, ) 1550 #endif 1551 1552 #ifdef HAVE_AS_DSP 1553 #define rddsp(mask) \ 1554 ({ \ 1555 unsigned int __dspctl; \ 1556 \ 1557 __asm__ __volatile__( \ 1558 " .set push \n" \ 1559 " .set dsp \n" \ 1560 " rddsp %0, %x1 \n" \ 1561 " .set pop \n" \ 1562 : "=r" (__dspctl) \ 1563 : "i" (mask)); \ 1564 __dspctl; \ 1565 }) 1566 1567 #define wrdsp(val, mask) \ 1568 do { \ 1569 __asm__ __volatile__( \ 1570 " .set push \n" \ 1571 " .set dsp \n" \ 1572 " wrdsp %0, %x1 \n" \ 1573 " .set pop \n" \ 1574 : \ 1575 : "r" (val), "i" (mask)); \ 1576 } while (0) 1577 1578 #define mflo0() \ 1579 ({ \ 1580 long mflo0; \ 1581 __asm__( \ 1582 " .set push \n" \ 1583 " .set dsp \n" \ 1584 " mflo %0, $ac0 \n" \ 1585 " .set pop \n" \ 1586 : "=r" (mflo0)); \ 1587 mflo0; \ 1588 }) 1589 1590 #define mflo1() \ 1591 ({ \ 1592 long mflo1; \ 1593 __asm__( \ 1594 " .set push \n" \ 1595 " .set dsp \n" \ 1596 " mflo %0, $ac1 \n" \ 1597 " .set pop \n" \ 1598 : "=r" (mflo1)); \ 1599 mflo1; \ 1600 }) 1601 1602 #define mflo2() \ 1603 ({ \ 1604 long mflo2; \ 1605 __asm__( \ 1606 " .set push \n" \ 1607 " .set dsp \n" \ 1608 " mflo %0, $ac2 \n" \ 1609 " .set pop \n" \ 1610 : "=r" (mflo2)); \ 1611 mflo2; \ 1612 }) 1613 1614 #define mflo3() \ 1615 ({ \ 1616 long mflo3; \ 1617 __asm__( \ 1618 " .set push \n" \ 1619 " .set dsp \n" \ 1620 " mflo %0, $ac3 \n" \ 1621 " .set pop \n" \ 1622 : "=r" (mflo3)); \ 1623 mflo3; \ 1624 }) 1625 1626 #define mfhi0() \ 1627 ({ \ 1628 long mfhi0; \ 1629 __asm__( \ 1630 " .set push \n" \ 1631 " .set dsp \n" \ 1632 " mfhi %0, $ac0 \n" \ 1633 " .set pop \n" \ 1634 : "=r" (mfhi0)); \ 1635 mfhi0; \ 1636 }) 1637 1638 #define mfhi1() \ 1639 ({ \ 1640 long mfhi1; \ 1641 __asm__( \ 1642 " .set push \n" \ 1643 " .set dsp \n" \ 1644 " mfhi %0, $ac1 \n" \ 1645 " .set pop \n" \ 1646 : "=r" (mfhi1)); \ 1647 mfhi1; \ 1648 }) 1649 1650 #define mfhi2() \ 1651 ({ \ 1652 long mfhi2; \ 1653 __asm__( \ 1654 " .set push \n" \ 1655 " .set dsp \n" \ 1656 " mfhi %0, $ac2 \n" \ 1657 " .set pop \n" \ 1658 : "=r" (mfhi2)); \ 1659 mfhi2; \ 1660 }) 1661 1662 #define mfhi3() \ 1663 ({ \ 1664 long mfhi3; \ 1665 __asm__( \ 1666 " .set push \n" \ 1667 " .set dsp \n" \ 1668 " mfhi %0, $ac3 \n" \ 1669 " .set pop \n" \ 1670 : "=r" (mfhi3)); \ 1671 mfhi3; \ 1672 }) 1673 1674 1675 #define mtlo0(x) \ 1676 ({ \ 1677 __asm__( \ 1678 " .set push \n" \ 1679 " .set dsp \n" \ 1680 " mtlo %0, $ac0 \n" \ 1681 " .set pop \n" \ 1682 : \ 1683 : "r" (x)); \ 1684 }) 1685 1686 #define mtlo1(x) \ 1687 ({ \ 1688 __asm__( \ 1689 " .set push \n" \ 1690 " .set dsp \n" \ 1691 " mtlo %0, $ac1 \n" \ 1692 " .set pop \n" \ 1693 : \ 1694 : "r" (x)); \ 1695 }) 1696 1697 #define mtlo2(x) \ 1698 ({ \ 1699 __asm__( \ 1700 " .set push \n" \ 1701 " .set dsp \n" \ 1702 " mtlo %0, $ac2 \n" \ 1703 " .set pop \n" \ 1704 : \ 1705 : "r" (x)); \ 1706 }) 1707 1708 #define mtlo3(x) \ 1709 ({ \ 1710 __asm__( \ 1711 " .set push \n" \ 1712 " .set dsp \n" \ 1713 " mtlo %0, $ac3 \n" \ 1714 " .set pop \n" \ 1715 : \ 1716 : "r" (x)); \ 1717 }) 1718 1719 #define mthi0(x) \ 1720 ({ \ 1721 __asm__( \ 1722 " .set push \n" \ 1723 " .set dsp \n" \ 1724 " mthi %0, $ac0 \n" \ 1725 " .set pop \n" \ 1726 : \ 1727 : "r" (x)); \ 1728 }) 1729 1730 #define mthi1(x) \ 1731 ({ \ 1732 __asm__( \ 1733 " .set push \n" \ 1734 " .set dsp \n" \ 1735 " mthi %0, $ac1 \n" \ 1736 " .set pop \n" \ 1737 : \ 1738 : "r" (x)); \ 1739 }) 1740 1741 #define mthi2(x) \ 1742 ({ \ 1743 __asm__( \ 1744 " .set push \n" \ 1745 " .set dsp \n" \ 1746 " mthi %0, $ac2 \n" \ 1747 " .set pop \n" \ 1748 : \ 1749 : "r" (x)); \ 1750 }) 1751 1752 #define mthi3(x) \ 1753 ({ \ 1754 __asm__( \ 1755 " .set push \n" \ 1756 " .set dsp \n" \ 1757 " mthi %0, $ac3 \n" \ 1758 " .set pop \n" \ 1759 : \ 1760 : "r" (x)); \ 1761 }) 1762 1763 #else 1764 1765 #ifdef CONFIG_CPU_MICROMIPS 1766 #define rddsp(mask) \ 1767 ({ \ 1768 unsigned int __res; \ 1769 \ 1770 __asm__ __volatile__( \ 1771 " .set push \n" \ 1772 " .set noat \n" \ 1773 " # rddsp $1, %x1 \n" \ 1774 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1775 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1776 " move %0, $1 \n" \ 1777 " .set pop \n" \ 1778 : "=r" (__res) \ 1779 : "i" (mask)); \ 1780 __res; \ 1781 }) 1782 1783 #define wrdsp(val, mask) \ 1784 do { \ 1785 __asm__ __volatile__( \ 1786 " .set push \n" \ 1787 " .set noat \n" \ 1788 " move $1, %0 \n" \ 1789 " # wrdsp $1, %x1 \n" \ 1790 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1791 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1792 " .set pop \n" \ 1793 : \ 1794 : "r" (val), "i" (mask)); \ 1795 } while (0) 1796 1797 #define _umips_dsp_mfxxx(ins) \ 1798 ({ \ 1799 unsigned long __treg; \ 1800 \ 1801 __asm__ __volatile__( \ 1802 " .set push \n" \ 1803 " .set noat \n" \ 1804 " .hword 0x0001 \n" \ 1805 " .hword %x1 \n" \ 1806 " move %0, $1 \n" \ 1807 " .set pop \n" \ 1808 : "=r" (__treg) \ 1809 : "i" (ins)); \ 1810 __treg; \ 1811 }) 1812 1813 #define _umips_dsp_mtxxx(val, ins) \ 1814 do { \ 1815 __asm__ __volatile__( \ 1816 " .set push \n" \ 1817 " .set noat \n" \ 1818 " move $1, %0 \n" \ 1819 " .hword 0x0001 \n" \ 1820 " .hword %x1 \n" \ 1821 " .set pop \n" \ 1822 : \ 1823 : "r" (val), "i" (ins)); \ 1824 } while (0) 1825 1826 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1827 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1828 1829 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1830 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1831 1832 #define mflo0() _umips_dsp_mflo(0) 1833 #define mflo1() _umips_dsp_mflo(1) 1834 #define mflo2() _umips_dsp_mflo(2) 1835 #define mflo3() _umips_dsp_mflo(3) 1836 1837 #define mfhi0() _umips_dsp_mfhi(0) 1838 #define mfhi1() _umips_dsp_mfhi(1) 1839 #define mfhi2() _umips_dsp_mfhi(2) 1840 #define mfhi3() _umips_dsp_mfhi(3) 1841 1842 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1843 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1844 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1845 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1846 1847 #define mthi0(x) _umips_dsp_mthi(x, 0) 1848 #define mthi1(x) _umips_dsp_mthi(x, 1) 1849 #define mthi2(x) _umips_dsp_mthi(x, 2) 1850 #define mthi3(x) _umips_dsp_mthi(x, 3) 1851 1852 #else /* !CONFIG_CPU_MICROMIPS */ 1853 #define rddsp(mask) \ 1854 ({ \ 1855 unsigned int __res; \ 1856 \ 1857 __asm__ __volatile__( \ 1858 " .set push \n" \ 1859 " .set noat \n" \ 1860 " # rddsp $1, %x1 \n" \ 1861 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1862 " move %0, $1 \n" \ 1863 " .set pop \n" \ 1864 : "=r" (__res) \ 1865 : "i" (mask)); \ 1866 __res; \ 1867 }) 1868 1869 #define wrdsp(val, mask) \ 1870 do { \ 1871 __asm__ __volatile__( \ 1872 " .set push \n" \ 1873 " .set noat \n" \ 1874 " move $1, %0 \n" \ 1875 " # wrdsp $1, %x1 \n" \ 1876 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1877 " .set pop \n" \ 1878 : \ 1879 : "r" (val), "i" (mask)); \ 1880 } while (0) 1881 1882 #define _dsp_mfxxx(ins) \ 1883 ({ \ 1884 unsigned long __treg; \ 1885 \ 1886 __asm__ __volatile__( \ 1887 " .set push \n" \ 1888 " .set noat \n" \ 1889 " .word (0x00000810 | %1) \n" \ 1890 " move %0, $1 \n" \ 1891 " .set pop \n" \ 1892 : "=r" (__treg) \ 1893 : "i" (ins)); \ 1894 __treg; \ 1895 }) 1896 1897 #define _dsp_mtxxx(val, ins) \ 1898 do { \ 1899 __asm__ __volatile__( \ 1900 " .set push \n" \ 1901 " .set noat \n" \ 1902 " move $1, %0 \n" \ 1903 " .word (0x00200011 | %1) \n" \ 1904 " .set pop \n" \ 1905 : \ 1906 : "r" (val), "i" (ins)); \ 1907 } while (0) 1908 1909 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1910 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1911 1912 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1913 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1914 1915 #define mflo0() _dsp_mflo(0) 1916 #define mflo1() _dsp_mflo(1) 1917 #define mflo2() _dsp_mflo(2) 1918 #define mflo3() _dsp_mflo(3) 1919 1920 #define mfhi0() _dsp_mfhi(0) 1921 #define mfhi1() _dsp_mfhi(1) 1922 #define mfhi2() _dsp_mfhi(2) 1923 #define mfhi3() _dsp_mfhi(3) 1924 1925 #define mtlo0(x) _dsp_mtlo(x, 0) 1926 #define mtlo1(x) _dsp_mtlo(x, 1) 1927 #define mtlo2(x) _dsp_mtlo(x, 2) 1928 #define mtlo3(x) _dsp_mtlo(x, 3) 1929 1930 #define mthi0(x) _dsp_mthi(x, 0) 1931 #define mthi1(x) _dsp_mthi(x, 1) 1932 #define mthi2(x) _dsp_mthi(x, 2) 1933 #define mthi3(x) _dsp_mthi(x, 3) 1934 1935 #endif /* CONFIG_CPU_MICROMIPS */ 1936 #endif 1937 1938 /* 1939 * TLB operations. 1940 * 1941 * It is responsibility of the caller to take care of any TLB hazards. 1942 */ 1943 static inline void tlb_probe(void) 1944 { 1945 __asm__ __volatile__( 1946 ".set noreorder\n\t" 1947 "tlbp\n\t" 1948 ".set reorder"); 1949 } 1950 1951 static inline void tlb_read(void) 1952 { 1953 #if MIPS34K_MISSED_ITLB_WAR 1954 int res = 0; 1955 1956 __asm__ __volatile__( 1957 " .set push \n" 1958 " .set noreorder \n" 1959 " .set noat \n" 1960 " .set mips32r2 \n" 1961 " .word 0x41610001 # dvpe $1 \n" 1962 " move %0, $1 \n" 1963 " ehb \n" 1964 " .set pop \n" 1965 : "=r" (res)); 1966 1967 instruction_hazard(); 1968 #endif 1969 1970 __asm__ __volatile__( 1971 ".set noreorder\n\t" 1972 "tlbr\n\t" 1973 ".set reorder"); 1974 1975 #if MIPS34K_MISSED_ITLB_WAR 1976 if ((res & _ULCAST_(1))) 1977 __asm__ __volatile__( 1978 " .set push \n" 1979 " .set noreorder \n" 1980 " .set noat \n" 1981 " .set mips32r2 \n" 1982 " .word 0x41600021 # evpe \n" 1983 " ehb \n" 1984 " .set pop \n"); 1985 #endif 1986 } 1987 1988 static inline void tlb_write_indexed(void) 1989 { 1990 __asm__ __volatile__( 1991 ".set noreorder\n\t" 1992 "tlbwi\n\t" 1993 ".set reorder"); 1994 } 1995 1996 static inline void tlb_write_random(void) 1997 { 1998 __asm__ __volatile__( 1999 ".set noreorder\n\t" 2000 "tlbwr\n\t" 2001 ".set reorder"); 2002 } 2003 2004 /* 2005 * Manipulate bits in a c0 register. 2006 */ 2007 #define __BUILD_SET_C0(name) \ 2008 static inline unsigned int \ 2009 set_c0_##name(unsigned int set) \ 2010 { \ 2011 unsigned int res, new; \ 2012 \ 2013 res = read_c0_##name(); \ 2014 new = res | set; \ 2015 write_c0_##name(new); \ 2016 \ 2017 return res; \ 2018 } \ 2019 \ 2020 static inline unsigned int \ 2021 clear_c0_##name(unsigned int clear) \ 2022 { \ 2023 unsigned int res, new; \ 2024 \ 2025 res = read_c0_##name(); \ 2026 new = res & ~clear; \ 2027 write_c0_##name(new); \ 2028 \ 2029 return res; \ 2030 } \ 2031 \ 2032 static inline unsigned int \ 2033 change_c0_##name(unsigned int change, unsigned int val) \ 2034 { \ 2035 unsigned int res, new; \ 2036 \ 2037 res = read_c0_##name(); \ 2038 new = res & ~change; \ 2039 new |= (val & change); \ 2040 write_c0_##name(new); \ 2041 \ 2042 return res; \ 2043 } 2044 2045 __BUILD_SET_C0(status) 2046 __BUILD_SET_C0(cause) 2047 __BUILD_SET_C0(config) 2048 __BUILD_SET_C0(config5) 2049 __BUILD_SET_C0(intcontrol) 2050 __BUILD_SET_C0(intctl) 2051 __BUILD_SET_C0(srsmap) 2052 __BUILD_SET_C0(pagegrain) 2053 __BUILD_SET_C0(brcm_config_0) 2054 __BUILD_SET_C0(brcm_bus_pll) 2055 __BUILD_SET_C0(brcm_reset) 2056 __BUILD_SET_C0(brcm_cmt_intr) 2057 __BUILD_SET_C0(brcm_cmt_ctrl) 2058 __BUILD_SET_C0(brcm_config) 2059 __BUILD_SET_C0(brcm_mode) 2060 2061 /* 2062 * Return low 10 bits of ebase. 2063 * Note that under KVM (MIPSVZ) this returns vcpu id. 2064 */ 2065 static inline unsigned int get_ebase_cpunum(void) 2066 { 2067 return read_c0_ebase() & 0x3ff; 2068 } 2069 2070 #endif /* !__ASSEMBLY__ */ 2071 2072 #endif /* _ASM_MIPSREGS_H */ 2073