1b0a668fbSLeonid Yegoshin /*
2b0a668fbSLeonid Yegoshin * This file is subject to the terms and conditions of the GNU General Public
3b0a668fbSLeonid Yegoshin * License. See the file "COPYING" in the main directory of this archive
4b0a668fbSLeonid Yegoshin * for more details.
5b0a668fbSLeonid Yegoshin *
6b0a668fbSLeonid Yegoshin * Copyright (c) 2014 Imagination Technologies Ltd.
7b0a668fbSLeonid Yegoshin * Author: Markos Chandras <markos.chandras@imgtec.com>
8b0a668fbSLeonid Yegoshin */
9b0a668fbSLeonid Yegoshin
10b0a668fbSLeonid Yegoshin #ifndef __ASM_MIPS_R2_TO_R6_EMUL_H
11b0a668fbSLeonid Yegoshin #define __ASM_MIPS_R2_TO_R6_EMUL_H
12b0a668fbSLeonid Yegoshin
13b0a668fbSLeonid Yegoshin struct mips_r2_emulator_stats {
14b0a668fbSLeonid Yegoshin u64 movs;
15b0a668fbSLeonid Yegoshin u64 hilo;
16b0a668fbSLeonid Yegoshin u64 muls;
17b0a668fbSLeonid Yegoshin u64 divs;
18b0a668fbSLeonid Yegoshin u64 dsps;
19b0a668fbSLeonid Yegoshin u64 bops;
20b0a668fbSLeonid Yegoshin u64 traps;
21b0a668fbSLeonid Yegoshin u64 fpus;
22b0a668fbSLeonid Yegoshin u64 loads;
23b0a668fbSLeonid Yegoshin u64 stores;
24b0a668fbSLeonid Yegoshin u64 llsc;
25b0a668fbSLeonid Yegoshin u64 dsemul;
26b0a668fbSLeonid Yegoshin };
27b0a668fbSLeonid Yegoshin
28b0a668fbSLeonid Yegoshin struct mips_r2br_emulator_stats {
29b0a668fbSLeonid Yegoshin u64 jrs;
30b0a668fbSLeonid Yegoshin u64 bltzl;
31b0a668fbSLeonid Yegoshin u64 bgezl;
32b0a668fbSLeonid Yegoshin u64 bltzll;
33b0a668fbSLeonid Yegoshin u64 bgezll;
34b0a668fbSLeonid Yegoshin u64 bltzall;
35b0a668fbSLeonid Yegoshin u64 bgezall;
36b0a668fbSLeonid Yegoshin u64 bltzal;
37b0a668fbSLeonid Yegoshin u64 bgezal;
38b0a668fbSLeonid Yegoshin u64 beql;
39b0a668fbSLeonid Yegoshin u64 bnel;
40b0a668fbSLeonid Yegoshin u64 blezl;
41b0a668fbSLeonid Yegoshin u64 bgtzl;
42b0a668fbSLeonid Yegoshin };
43b0a668fbSLeonid Yegoshin
44b0a668fbSLeonid Yegoshin #ifdef CONFIG_DEBUG_FS
45b0a668fbSLeonid Yegoshin
46b0a668fbSLeonid Yegoshin #define MIPS_R2_STATS(M) \
47b0a668fbSLeonid Yegoshin do { \
48b0a668fbSLeonid Yegoshin u32 nir; \
49b0a668fbSLeonid Yegoshin int err; \
50b0a668fbSLeonid Yegoshin \
51b0a668fbSLeonid Yegoshin preempt_disable(); \
52b0a668fbSLeonid Yegoshin __this_cpu_inc(mipsr2emustats.M); \
53b0a668fbSLeonid Yegoshin err = __get_user(nir, (u32 __user *)regs->cp0_epc); \
54b0a668fbSLeonid Yegoshin if (!err) { \
55733b8bc1SMaciej W. Rozycki if (nir == BREAK_MATH(0)) \
56b0a668fbSLeonid Yegoshin __this_cpu_inc(mipsr2bdemustats.M); \
57b0a668fbSLeonid Yegoshin } \
58b0a668fbSLeonid Yegoshin preempt_enable(); \
59b0a668fbSLeonid Yegoshin } while (0)
60b0a668fbSLeonid Yegoshin
61b0a668fbSLeonid Yegoshin #define MIPS_R2BR_STATS(M) \
62b0a668fbSLeonid Yegoshin do { \
63b0a668fbSLeonid Yegoshin preempt_disable(); \
64b0a668fbSLeonid Yegoshin __this_cpu_inc(mipsr2bremustats.M); \
65b0a668fbSLeonid Yegoshin preempt_enable(); \
66b0a668fbSLeonid Yegoshin } while (0)
67b0a668fbSLeonid Yegoshin
68b0a668fbSLeonid Yegoshin #else
69b0a668fbSLeonid Yegoshin
70b0a668fbSLeonid Yegoshin #define MIPS_R2_STATS(M) do { } while (0)
71b0a668fbSLeonid Yegoshin #define MIPS_R2BR_STATS(M) do { } while (0)
72b0a668fbSLeonid Yegoshin
73b0a668fbSLeonid Yegoshin #endif /* CONFIG_DEBUG_FS */
74b0a668fbSLeonid Yegoshin
75b0a668fbSLeonid Yegoshin struct r2_decoder_table {
76b0a668fbSLeonid Yegoshin u32 mask;
77b0a668fbSLeonid Yegoshin u32 code;
78b0a668fbSLeonid Yegoshin int (*func)(struct pt_regs *regs, u32 inst);
79b0a668fbSLeonid Yegoshin };
80b0a668fbSLeonid Yegoshin
81b0a668fbSLeonid Yegoshin
823b143ccaSMaciej W. Rozycki extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
83b0a668fbSLeonid Yegoshin const char *str);
84b0a668fbSLeonid Yegoshin
85b0a668fbSLeonid Yegoshin #ifndef CONFIG_MIPSR2_TO_R6_EMULATOR
86b0a668fbSLeonid Yegoshin static int mipsr2_emulation;
mipsr2_decoder(struct pt_regs * regs,u32 inst,unsigned long * fcr31)87304acb71SMaciej W. Rozycki static inline int mipsr2_decoder(struct pt_regs *regs, u32 inst,
88304acb71SMaciej W. Rozycki unsigned long *fcr31)
89304acb71SMaciej W. Rozycki {
90304acb71SMaciej W. Rozycki return 0;
91304acb71SMaciej W. Rozycki };
92b0a668fbSLeonid Yegoshin #else
93b0a668fbSLeonid Yegoshin /* MIPS R2 Emulator ON/OFF */
94b0a668fbSLeonid Yegoshin extern int mipsr2_emulation;
95304acb71SMaciej W. Rozycki extern int mipsr2_decoder(struct pt_regs *regs, u32 inst,
96304acb71SMaciej W. Rozycki unsigned long *fcr31);
97b0a668fbSLeonid Yegoshin #endif /* CONFIG_MIPSR2_TO_R6_EMULATOR */
98b0a668fbSLeonid Yegoshin
99b0a668fbSLeonid Yegoshin #define NO_R6EMU (cpu_has_mips_r6 && !mipsr2_emulation)
100b0a668fbSLeonid Yegoshin
101b0a668fbSLeonid Yegoshin #endif /* __ASM_MIPS_R2_TO_R6_EMUL_H */
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