1 /* 2 * Copyright (C) 2013 Imagination Technologies 3 * Author: Paul Burton <paul.burton@imgtec.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #ifndef __MIPS_ASM_MIPS_CM_H__ 12 #define __MIPS_ASM_MIPS_CM_H__ 13 14 #include <linux/errno.h> 15 #include <linux/io.h> 16 #include <linux/types.h> 17 18 /* The base address of the CM GCR block */ 19 extern void __iomem *mips_cm_base; 20 21 /* The base address of the CM L2-only sync region */ 22 extern void __iomem *mips_cm_l2sync_base; 23 24 /** 25 * __mips_cm_phys_base - retrieve the physical base address of the CM 26 * 27 * This function returns the physical base address of the Coherence Manager 28 * global control block, or 0 if no Coherence Manager is present. It provides 29 * a default implementation which reads the CMGCRBase register where available, 30 * and may be overriden by platforms which determine this address in a 31 * different way by defining a function with the same prototype except for the 32 * name mips_cm_phys_base (without underscores). 33 */ 34 extern phys_addr_t __mips_cm_phys_base(void); 35 36 /** 37 * mips_cm_probe - probe for a Coherence Manager 38 * 39 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM 40 * is successfully detected, else -errno. 41 */ 42 #ifdef CONFIG_MIPS_CM 43 extern int mips_cm_probe(void); 44 #else 45 static inline int mips_cm_probe(void) 46 { 47 return -ENODEV; 48 } 49 #endif 50 51 /** 52 * mips_cm_present - determine whether a Coherence Manager is present 53 * 54 * Returns true if a CM is present in the system, else false. 55 */ 56 static inline bool mips_cm_present(void) 57 { 58 #ifdef CONFIG_MIPS_CM 59 return mips_cm_base != NULL; 60 #else 61 return false; 62 #endif 63 } 64 65 /** 66 * mips_cm_has_l2sync - determine whether an L2-only sync region is present 67 * 68 * Returns true if the system implements an L2-only sync region, else false. 69 */ 70 static inline bool mips_cm_has_l2sync(void) 71 { 72 #ifdef CONFIG_MIPS_CM 73 return mips_cm_l2sync_base != NULL; 74 #else 75 return false; 76 #endif 77 } 78 79 /* Offsets to register blocks from the CM base address */ 80 #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ 81 #define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */ 82 #define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */ 83 #define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */ 84 85 /* Total size of the CM memory mapped registers */ 86 #define MIPS_CM_GCR_SIZE 0x8000 87 88 /* Size of the L2-only sync region */ 89 #define MIPS_CM_L2SYNC_SIZE 0x1000 90 91 /* Macros to ease the creation of register access functions */ 92 #define BUILD_CM_R_(name, off) \ 93 static inline u32 __iomem *addr_gcr_##name(void) \ 94 { \ 95 return (u32 __iomem *)(mips_cm_base + (off)); \ 96 } \ 97 \ 98 static inline u32 read_gcr_##name(void) \ 99 { \ 100 return __raw_readl(addr_gcr_##name()); \ 101 } 102 103 #define BUILD_CM__W(name, off) \ 104 static inline void write_gcr_##name(u32 value) \ 105 { \ 106 __raw_writel(value, addr_gcr_##name()); \ 107 } 108 109 #define BUILD_CM_RW(name, off) \ 110 BUILD_CM_R_(name, off) \ 111 BUILD_CM__W(name, off) 112 113 #define BUILD_CM_Cx_R_(name, off) \ 114 BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ 115 BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off)) 116 117 #define BUILD_CM_Cx__W(name, off) \ 118 BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ 119 BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off)) 120 121 #define BUILD_CM_Cx_RW(name, off) \ 122 BUILD_CM_Cx_R_(name, off) \ 123 BUILD_CM_Cx__W(name, off) 124 125 /* GCB register accessor functions */ 126 BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00) 127 BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08) 128 BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20) 129 BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30) 130 BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40) 131 BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48) 132 BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50) 133 BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58) 134 BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70) 135 BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80) 136 BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88) 137 BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90) 138 BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98) 139 BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0) 140 BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8) 141 BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0) 142 BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8) 143 BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0) 144 BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8) 145 BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0) 146 BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0) 147 148 /* Core Local & Core Other register accessor functions */ 149 BUILD_CM_Cx_RW(reset_release, 0x00) 150 BUILD_CM_Cx_RW(coherence, 0x08) 151 BUILD_CM_Cx_R_(config, 0x10) 152 BUILD_CM_Cx_RW(other, 0x18) 153 BUILD_CM_Cx_RW(reset_base, 0x20) 154 BUILD_CM_Cx_R_(id, 0x28) 155 BUILD_CM_Cx_RW(reset_ext_base, 0x30) 156 BUILD_CM_Cx_R_(tcid_0_priority, 0x40) 157 BUILD_CM_Cx_R_(tcid_1_priority, 0x48) 158 BUILD_CM_Cx_R_(tcid_2_priority, 0x50) 159 BUILD_CM_Cx_R_(tcid_3_priority, 0x58) 160 BUILD_CM_Cx_R_(tcid_4_priority, 0x60) 161 BUILD_CM_Cx_R_(tcid_5_priority, 0x68) 162 BUILD_CM_Cx_R_(tcid_6_priority, 0x70) 163 BUILD_CM_Cx_R_(tcid_7_priority, 0x78) 164 BUILD_CM_Cx_R_(tcid_8_priority, 0x80) 165 166 /* GCR_CONFIG register fields */ 167 #define CM_GCR_CONFIG_NUMIOCU_SHF 8 168 #define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8) 169 #define CM_GCR_CONFIG_PCORES_SHF 0 170 #define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0) 171 172 /* GCR_BASE register fields */ 173 #define CM_GCR_BASE_GCRBASE_SHF 15 174 #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15) 175 #define CM_GCR_BASE_CMDEFTGT_SHF 0 176 #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0) 177 #define CM_GCR_BASE_CMDEFTGT_DISABLED 0 178 #define CM_GCR_BASE_CMDEFTGT_MEM 1 179 #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 180 #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 181 182 /* GCR_ACCESS register fields */ 183 #define CM_GCR_ACCESS_ACCESSEN_SHF 0 184 #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0) 185 186 /* GCR_REV register fields */ 187 #define CM_GCR_REV_MAJOR_SHF 8 188 #define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8) 189 #define CM_GCR_REV_MINOR_SHF 0 190 #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0) 191 192 /* GCR_ERROR_CAUSE register fields */ 193 #define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27 194 #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27) 195 #define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0 196 #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0) 197 198 /* GCR_ERROR_MULT register fields */ 199 #define CM_GCR_ERROR_MULT_ERR2ND_SHF 0 200 #define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0) 201 202 /* GCR_L2_ONLY_SYNC_BASE register fields */ 203 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12 204 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12) 205 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0 206 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0) 207 208 /* GCR_GIC_BASE register fields */ 209 #define CM_GCR_GIC_BASE_GICBASE_SHF 17 210 #define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17) 211 #define CM_GCR_GIC_BASE_GICEN_SHF 0 212 #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) 213 214 /* GCR_CPC_BASE register fields */ 215 #define CM_GCR_CPC_BASE_CPCBASE_SHF 17 216 #define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) 217 #define CM_GCR_CPC_BASE_CPCEN_SHF 0 218 #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) 219 220 /* GCR_GIC_STATUS register fields */ 221 #define CM_GCR_GIC_STATUS_GICEX_SHF 0 222 #define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0) 223 224 /* GCR_REGn_BASE register fields */ 225 #define CM_GCR_REGn_BASE_BASEADDR_SHF 16 226 #define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16) 227 228 /* GCR_REGn_MASK register fields */ 229 #define CM_GCR_REGn_MASK_ADDRMASK_SHF 16 230 #define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16) 231 #define CM_GCR_REGn_MASK_CCAOVR_SHF 5 232 #define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5) 233 #define CM_GCR_REGn_MASK_CCAOVREN_SHF 4 234 #define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4) 235 #define CM_GCR_REGn_MASK_DROPL2_SHF 2 236 #define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2) 237 #define CM_GCR_REGn_MASK_CMTGT_SHF 0 238 #define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0) 239 #define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0) 240 #define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0) 241 #define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0) 242 #define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0) 243 244 /* GCR_GIC_STATUS register fields */ 245 #define CM_GCR_GIC_STATUS_EX_SHF 0 246 #define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) 247 248 /* GCR_CPC_STATUS register fields */ 249 #define CM_GCR_CPC_STATUS_EX_SHF 0 250 #define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) 251 252 /* GCR_Cx_COHERENCE register fields */ 253 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0 254 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0) 255 256 /* GCR_Cx_CONFIG register fields */ 257 #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 258 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10) 259 #define CM_GCR_Cx_CONFIG_PVPE_SHF 0 260 #define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0) 261 262 /* GCR_Cx_OTHER register fields */ 263 #define CM_GCR_Cx_OTHER_CORENUM_SHF 16 264 #define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16) 265 266 /* GCR_Cx_RESET_BASE register fields */ 267 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12 268 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12) 269 270 /* GCR_Cx_RESET_EXT_BASE register fields */ 271 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31 272 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31) 273 #define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30 274 #define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30) 275 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20 276 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20) 277 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1 278 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1) 279 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0 280 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0) 281 282 /** 283 * mips_cm_numcores - return the number of cores present in the system 284 * 285 * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or 286 * zero if no Coherence Manager is present. 287 */ 288 static inline unsigned mips_cm_numcores(void) 289 { 290 if (!mips_cm_present()) 291 return 0; 292 293 return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK) 294 >> CM_GCR_CONFIG_PCORES_SHF) + 1; 295 } 296 297 /** 298 * mips_cm_numiocu - return the number of IOCUs present in the system 299 * 300 * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero 301 * if no Coherence Manager is present. 302 */ 303 static inline unsigned mips_cm_numiocu(void) 304 { 305 if (!mips_cm_present()) 306 return 0; 307 308 return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK) 309 >> CM_GCR_CONFIG_NUMIOCU_SHF; 310 } 311 312 /** 313 * mips_cm_l2sync - perform an L2-only sync operation 314 * 315 * If an L2-only sync region is present in the system then this function 316 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV. 317 */ 318 static inline int mips_cm_l2sync(void) 319 { 320 if (!mips_cm_has_l2sync()) 321 return -ENODEV; 322 323 writel(0, mips_cm_l2sync_base); 324 return 0; 325 } 326 327 #endif /* __MIPS_ASM_MIPS_CM_H__ */ 328