1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2013 Imagination Technologies 4 * Author: Paul Burton <paul.burton@mips.com> 5 */ 6 7 #ifndef __MIPS_ASM_MIPS_CPS_H__ 8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h 9 #endif 10 11 #ifndef __MIPS_ASM_MIPS_CM_H__ 12 #define __MIPS_ASM_MIPS_CM_H__ 13 14 #include <linux/bitfield.h> 15 #include <linux/bitops.h> 16 #include <linux/errno.h> 17 18 /* The base address of the CM GCR block */ 19 extern void __iomem *mips_gcr_base; 20 21 /* The base address of the CM L2-only sync region */ 22 extern void __iomem *mips_cm_l2sync_base; 23 24 /** 25 * __mips_cm_phys_base - retrieve the physical base address of the CM 26 * 27 * This function returns the physical base address of the Coherence Manager 28 * global control block, or 0 if no Coherence Manager is present. It provides 29 * a default implementation which reads the CMGCRBase register where available, 30 * and may be overridden by platforms which determine this address in a 31 * different way by defining a function with the same prototype except for the 32 * name mips_cm_phys_base (without underscores). 33 */ 34 extern phys_addr_t __mips_cm_phys_base(void); 35 36 /* 37 * mips_cm_is64 - determine CM register width 38 * 39 * The CM register width is determined by the version of the CM, with CM3 40 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs. 41 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs, 42 * or vice-versa. This variable indicates the width of the memory accesses 43 * that the kernel will perform to GCRs, which may differ from the actual 44 * width of the GCRs. 45 * 46 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses. 47 */ 48 extern int mips_cm_is64; 49 50 /** 51 * mips_cm_error_report - Report CM cache errors 52 */ 53 #ifdef CONFIG_MIPS_CM 54 extern void mips_cm_error_report(void); 55 #else 56 static inline void mips_cm_error_report(void) {} 57 #endif 58 59 /** 60 * mips_cm_probe - probe for a Coherence Manager 61 * 62 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM 63 * is successfully detected, else -errno. 64 */ 65 #ifdef CONFIG_MIPS_CM 66 extern int mips_cm_probe(void); 67 #else 68 static inline int mips_cm_probe(void) 69 { 70 return -ENODEV; 71 } 72 #endif 73 74 /** 75 * mips_cm_present - determine whether a Coherence Manager is present 76 * 77 * Returns true if a CM is present in the system, else false. 78 */ 79 static inline bool mips_cm_present(void) 80 { 81 #ifdef CONFIG_MIPS_CM 82 return mips_gcr_base != NULL; 83 #else 84 return false; 85 #endif 86 } 87 88 /** 89 * mips_cm_has_l2sync - determine whether an L2-only sync region is present 90 * 91 * Returns true if the system implements an L2-only sync region, else false. 92 */ 93 static inline bool mips_cm_has_l2sync(void) 94 { 95 #ifdef CONFIG_MIPS_CM 96 return mips_cm_l2sync_base != NULL; 97 #else 98 return false; 99 #endif 100 } 101 102 /* Offsets to register blocks from the CM base address */ 103 #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ 104 #define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */ 105 #define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */ 106 #define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */ 107 108 /* Total size of the CM memory mapped registers */ 109 #define MIPS_CM_GCR_SIZE 0x8000 110 111 /* Size of the L2-only sync region */ 112 #define MIPS_CM_L2SYNC_SIZE 0x1000 113 114 #define GCR_ACCESSOR_RO(sz, off, name) \ 115 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \ 116 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name) 117 118 #define GCR_ACCESSOR_RW(sz, off, name) \ 119 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \ 120 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name) 121 122 #define GCR_CX_ACCESSOR_RO(sz, off, name) \ 123 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \ 124 CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name) 125 126 #define GCR_CX_ACCESSOR_RW(sz, off, name) \ 127 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \ 128 CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name) 129 130 /* GCR_CONFIG - Information about the system */ 131 GCR_ACCESSOR_RO(64, 0x000, config) 132 #define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE BIT_ULL(43) 133 #define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32) 134 #define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23) 135 #define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8) 136 #define CM_GCR_CONFIG_PCORES GENMASK(7, 0) 137 138 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */ 139 GCR_ACCESSOR_RW(64, 0x008, base) 140 #define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15) 141 #define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0) 142 #define CM_GCR_BASE_CMDEFTGT_MEM 0 143 #define CM_GCR_BASE_CMDEFTGT_RESERVED 1 144 #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 145 #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 146 147 /* GCR_ACCESS - Controls core/IOCU access to GCRs */ 148 GCR_ACCESSOR_RW(32, 0x020, access) 149 #define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0) 150 151 /* GCR_REV - Indicates the Coherence Manager revision */ 152 GCR_ACCESSOR_RO(32, 0x030, rev) 153 #define CM_GCR_REV_MAJOR GENMASK(15, 8) 154 #define CM_GCR_REV_MINOR GENMASK(7, 0) 155 156 #define CM_ENCODE_REV(major, minor) \ 157 (FIELD_PREP(CM_GCR_REV_MAJOR, major) | \ 158 FIELD_PREP(CM_GCR_REV_MINOR, minor)) 159 160 #define CM_REV_CM2 CM_ENCODE_REV(6, 0) 161 #define CM_REV_CM2_5 CM_ENCODE_REV(7, 0) 162 #define CM_REV_CM3 CM_ENCODE_REV(8, 0) 163 #define CM_REV_CM3_5 CM_ENCODE_REV(9, 0) 164 165 /* GCR_ERR_CONTROL - Control error checking logic */ 166 GCR_ACCESSOR_RW(32, 0x038, err_control) 167 #define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1) 168 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0) 169 170 /* GCR_ERR_MASK - Control which errors are reported as interrupts */ 171 GCR_ACCESSOR_RW(64, 0x040, error_mask) 172 173 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */ 174 GCR_ACCESSOR_RW(64, 0x048, error_cause) 175 #define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27) 176 #define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58) 177 #define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0) 178 179 /* GCR_ERR_ADDR - Indicates the address associated with an error */ 180 GCR_ACCESSOR_RW(64, 0x050, error_addr) 181 182 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */ 183 GCR_ACCESSOR_RW(64, 0x058, error_mult) 184 #define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0) 185 186 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */ 187 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base) 188 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12) 189 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0) 190 191 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */ 192 GCR_ACCESSOR_RW(64, 0x080, gic_base) 193 #define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17) 194 #define CM_GCR_GIC_BASE_GICEN BIT(0) 195 196 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */ 197 GCR_ACCESSOR_RW(64, 0x088, cpc_base) 198 #define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15) 199 #define CM_GCR_CPC_BASE_CPCEN BIT(0) 200 201 /* GCR_REGn_BASE - Base addresses of CM address regions */ 202 GCR_ACCESSOR_RW(64, 0x090, reg0_base) 203 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base) 204 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base) 205 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base) 206 #define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16) 207 208 /* GCR_REGn_MASK - Size & destination of CM address regions */ 209 GCR_ACCESSOR_RW(64, 0x098, reg0_mask) 210 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask) 211 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask) 212 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask) 213 #define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16) 214 #define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5) 215 #define CM_GCR_REGn_MASK_CCAOVREN BIT(4) 216 #define CM_GCR_REGn_MASK_DROPL2 BIT(2) 217 #define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0) 218 #define CM_GCR_REGn_MASK_CMTGT_DISABLED 0x0 219 #define CM_GCR_REGn_MASK_CMTGT_MEM 0x1 220 #define CM_GCR_REGn_MASK_CMTGT_IOCU0 0x2 221 #define CM_GCR_REGn_MASK_CMTGT_IOCU1 0x3 222 223 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */ 224 GCR_ACCESSOR_RO(32, 0x0d0, gic_status) 225 #define CM_GCR_GIC_STATUS_EX BIT(0) 226 227 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */ 228 GCR_ACCESSOR_RO(32, 0x0f0, cpc_status) 229 #define CM_GCR_CPC_STATUS_EX BIT(0) 230 231 /* GCR_ACCESS - Controls core/IOCU access to GCRs */ 232 GCR_ACCESSOR_RW(32, 0x120, access_cm3) 233 #define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0) 234 235 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */ 236 GCR_ACCESSOR_RW(32, 0x130, l2_config) 237 #define CM_GCR_L2_CONFIG_BYPASS BIT(20) 238 #define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12) 239 #define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8) 240 #define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0) 241 242 /* GCR_SYS_CONFIG2 - Further information about the system */ 243 GCR_ACCESSOR_RO(32, 0x150, sys_config2) 244 #define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0) 245 246 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */ 247 GCR_ACCESSOR_RW(32, 0x300, l2_pft_control) 248 #define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12) 249 #define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8) 250 #define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0) 251 252 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */ 253 GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b) 254 #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8) 255 #define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0) 256 257 /* GCR_L2SM_COP - L2 cache op state machine control */ 258 GCR_ACCESSOR_RW(32, 0x620, l2sm_cop) 259 #define CM_GCR_L2SM_COP_PRESENT BIT(31) 260 #define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6) 261 #define CM_GCR_L2SM_COP_RESULT_DONTCARE 0 262 #define CM_GCR_L2SM_COP_RESULT_DONE_OK 1 263 #define CM_GCR_L2SM_COP_RESULT_DONE_ERROR 2 264 #define CM_GCR_L2SM_COP_RESULT_ABORT_OK 3 265 #define CM_GCR_L2SM_COP_RESULT_ABORT_ERROR 4 266 #define CM_GCR_L2SM_COP_RUNNING BIT(5) 267 #define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2) 268 #define CM_GCR_L2SM_COP_TYPE_IDX_WBINV 0 269 #define CM_GCR_L2SM_COP_TYPE_IDX_STORETAG 1 270 #define CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA 2 271 #define CM_GCR_L2SM_COP_TYPE_HIT_INV 4 272 #define CM_GCR_L2SM_COP_TYPE_HIT_WBINV 5 273 #define CM_GCR_L2SM_COP_TYPE_HIT_WB 6 274 #define CM_GCR_L2SM_COP_TYPE_FETCHLOCK 7 275 #define CM_GCR_L2SM_COP_CMD GENMASK(1, 0) 276 #define CM_GCR_L2SM_COP_CMD_START 1 /* only when idle */ 277 #define CM_GCR_L2SM_COP_CMD_ABORT 3 /* only when running */ 278 279 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */ 280 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop) 281 #define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48) 282 #define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6) 283 284 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */ 285 GCR_ACCESSOR_RW(64, 0x680, bev_base) 286 287 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */ 288 GCR_CX_ACCESSOR_RW(32, 0x000, reset_release) 289 290 /* GCR_Cx_COHERENCE - Controls core coherence */ 291 GCR_CX_ACCESSOR_RW(32, 0x008, coherence) 292 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0) 293 #define CM3_GCR_Cx_COHERENCE_COHEN BIT(0) 294 295 /* GCR_Cx_CONFIG - Information about a core's configuration */ 296 GCR_CX_ACCESSOR_RO(32, 0x010, config) 297 #define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10) 298 #define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0) 299 300 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */ 301 GCR_CX_ACCESSOR_RW(32, 0x018, other) 302 #define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16) /* CM < 3 */ 303 #define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */ 304 #define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */ 305 #define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24) /* CM >= 3.5 */ 306 #define CM_GCR_Cx_OTHER_BLOCK_LOCAL 0 307 #define CM_GCR_Cx_OTHER_BLOCK_GLOBAL 1 308 #define CM_GCR_Cx_OTHER_BLOCK_USER 2 309 #define CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH 3 310 #define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16) /* CM >= 3.5 */ 311 #define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8) /* CM >= 3 */ 312 #define CM_GCR_Cx_OTHER_CORE_CM 32 313 #define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0) /* CM >= 3 */ 314 315 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ 316 GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) 317 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) 318 319 /* GCR_Cx_ID - Identify the current core */ 320 GCR_CX_ACCESSOR_RO(32, 0x028, id) 321 #define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8) 322 #define CM_GCR_Cx_ID_CORE GENMASK(7, 0) 323 324 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */ 325 GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base) 326 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31) 327 #define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30) 328 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20) 329 #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1) 330 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0) 331 332 /** 333 * mips_cm_l2sync - perform an L2-only sync operation 334 * 335 * If an L2-only sync region is present in the system then this function 336 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV. 337 */ 338 static inline int mips_cm_l2sync(void) 339 { 340 if (!mips_cm_has_l2sync()) 341 return -ENODEV; 342 343 writel(0, mips_cm_l2sync_base); 344 return 0; 345 } 346 347 /** 348 * mips_cm_revision() - return CM revision 349 * 350 * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The 351 * return value should be checked against the CM_REV_* macros. 352 */ 353 static inline int mips_cm_revision(void) 354 { 355 if (!mips_cm_present()) 356 return 0; 357 358 return read_gcr_rev(); 359 } 360 361 /** 362 * mips_cm_max_vp_width() - return the width in bits of VP indices 363 * 364 * Return: the width, in bits, of VP indices in fields that combine core & VP 365 * indices. 366 */ 367 static inline unsigned int mips_cm_max_vp_width(void) 368 { 369 extern int smp_num_siblings; 370 371 if (mips_cm_revision() >= CM_REV_CM3) 372 return FIELD_GET(CM_GCR_SYS_CONFIG2_MAXVPW, 373 read_gcr_sys_config2()); 374 375 if (mips_cm_present()) { 376 /* 377 * We presume that all cores in the system will have the same 378 * number of VP(E)s, and if that ever changes then this will 379 * need revisiting. 380 */ 381 return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, read_gcr_cl_config()) + 1; 382 } 383 384 if (IS_ENABLED(CONFIG_SMP)) 385 return smp_num_siblings; 386 387 return 1; 388 } 389 390 /** 391 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU 392 * @cpu: the CPU whose VP ID to calculate 393 * 394 * Hardware such as the GIC uses identifiers for VPs which may not match the 395 * CPU numbers used by Linux. This function calculates the hardware VP 396 * identifier corresponding to a given CPU. 397 * 398 * Return: the VP ID for the CPU. 399 */ 400 static inline unsigned int mips_cm_vp_id(unsigned int cpu) 401 { 402 unsigned int core = cpu_core(&cpu_data[cpu]); 403 unsigned int vp = cpu_vpe_id(&cpu_data[cpu]); 404 405 return (core * mips_cm_max_vp_width()) + vp; 406 } 407 408 #ifdef CONFIG_MIPS_CM 409 410 /** 411 * mips_cm_lock_other - lock access to redirect/other region 412 * @cluster: the other cluster to be accessed 413 * @core: the other core to be accessed 414 * @vp: the VP within the other core to be accessed 415 * @block: the register block to be accessed 416 * 417 * Configure the redirect/other region for the local core/VP (depending upon 418 * the CM revision) to target the specified @cluster, @core, @vp & register 419 * @block. Must be called before using the redirect/other region, and followed 420 * by a call to mips_cm_unlock_other() when access to the redirect/other region 421 * is complete. 422 * 423 * This function acquires a spinlock such that code between it & 424 * mips_cm_unlock_other() calls cannot be pre-empted by anything which may 425 * reconfigure the redirect/other region, and cannot be interfered with by 426 * another VP in the core. As such calls to this function should not be nested. 427 */ 428 extern void mips_cm_lock_other(unsigned int cluster, unsigned int core, 429 unsigned int vp, unsigned int block); 430 431 /** 432 * mips_cm_unlock_other - unlock access to redirect/other region 433 * 434 * Must be called after mips_cm_lock_other() once all required access to the 435 * redirect/other region has been completed. 436 */ 437 extern void mips_cm_unlock_other(void); 438 439 #else /* !CONFIG_MIPS_CM */ 440 441 static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core, 442 unsigned int vp, unsigned int block) { } 443 static inline void mips_cm_unlock_other(void) { } 444 445 #endif /* !CONFIG_MIPS_CM */ 446 447 /** 448 * mips_cm_lock_other_cpu - lock access to redirect/other region 449 * @cpu: the other CPU whose register we want to access 450 * 451 * Configure the redirect/other region for the local core/VP (depending upon 452 * the CM revision) to target the specified @cpu & register @block. This is 453 * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number 454 * for convenience. 455 */ 456 static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block) 457 { 458 struct cpuinfo_mips *d = &cpu_data[cpu]; 459 460 mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block); 461 } 462 463 #endif /* __MIPS_ASM_MIPS_CM_H__ */ 464