1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved. 7 * Carsten Langgaard <carstenl@mips.com> 8 * Steven J. Hill <sjhill@mips.com> 9 */ 10 #ifndef _MIPS_MALTAINT_H 11 #define _MIPS_MALTAINT_H 12 13 #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) 14 15 /* 16 * Interrupts 0..15 are used for Malta ISA compatible interrupts 17 */ 18 #define MALTA_INT_BASE 0 19 20 /* CPU interrupt offsets */ 21 #define MIPSCPU_INT_SW0 0 22 #define MIPSCPU_INT_SW1 1 23 #define MIPSCPU_INT_MB0 2 24 #define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0 25 #define MIPSCPU_INT_MB1 3 26 #define MIPSCPU_INT_SMI MIPSCPU_INT_MB1 27 #define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */ 28 #define MIPSCPU_INT_MB2 4 29 #define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */ 30 #define MIPSCPU_INT_MB3 5 31 #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 32 #define MIPSCPU_INT_MB4 6 33 #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 34 35 /* 36 * Interrupts 64..127 are used for Soc-it Classic interrupts 37 */ 38 #define MSC01C_INT_BASE 64 39 40 /* SOC-it Classic interrupt offsets */ 41 #define MSC01C_INT_TMR 0 42 #define MSC01C_INT_PCI 1 43 44 /* 45 * Interrupts 64..127 are used for Soc-it EIC interrupts 46 */ 47 #define MSC01E_INT_BASE 64 48 49 /* SOC-it EIC interrupt offsets */ 50 #define MSC01E_INT_SW0 1 51 #define MSC01E_INT_SW1 2 52 #define MSC01E_INT_MB0 3 53 #define MSC01E_INT_I8259A MSC01E_INT_MB0 54 #define MSC01E_INT_MB1 4 55 #define MSC01E_INT_SMI MSC01E_INT_MB1 56 #define MSC01E_INT_MB2 5 57 #define MSC01E_INT_MB3 6 58 #define MSC01E_INT_COREHI MSC01E_INT_MB3 59 #define MSC01E_INT_MB4 7 60 #define MSC01E_INT_CORELO MSC01E_INT_MB4 61 #define MSC01E_INT_TMR 8 62 #define MSC01E_INT_PCI 9 63 #define MSC01E_INT_PERFCTR 10 64 #define MSC01E_INT_CPUCTR 11 65 66 /* External Interrupts used for IPI */ 67 #define GIC_IPI_EXT_INTR_RESCHED_VPE0 16 68 #define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17 69 #define GIC_IPI_EXT_INTR_RESCHED_VPE1 18 70 #define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19 71 #define GIC_IPI_EXT_INTR_RESCHED_VPE2 20 72 #define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21 73 #define GIC_IPI_EXT_INTR_RESCHED_VPE3 22 74 #define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23 75 76 #endif /* !(_MIPS_MALTAINT_H) */ 77