1 /*
2  * Carsten Langgaard, carstenl@mips.com
3  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
4  *
5  *  This program is free software; you can distribute it and/or modify it
6  *  under the terms of the GNU General Public License (Version 2) as
7  *  published by the Free Software Foundation.
8  *
9  *  This program is distributed in the hope it will be useful, but WITHOUT
10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  *  for more details.
13  *
14  *  You should have received a copy of the GNU General Public License along
15  *  with this program; if not, write to the Free Software Foundation, Inc.,
16  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17  *
18  * Defines of the Malta board specific address-MAP, registers, etc.
19  */
20 #ifndef __ASM_MIPS_BOARDS_MALTA_H
21 #define __ASM_MIPS_BOARDS_MALTA_H
22 
23 #include <asm/addrspace.h>
24 #include <asm/io.h>
25 #include <asm/mips-boards/msc01_pci.h>
26 #include <asm/gt64120.h>
27 
28 /* Mips interrupt controller found in SOCit variations */
29 #define MIPS_MSC01_IC_REG_BASE		0x1bc40000
30 #define MIPS_SOCITSC_IC_REG_BASE	0x1ffa0000
31 
32 /*
33  * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
34  * Bonito system controllers.
35  */
36 #define MALTA_GT_PORT_BASE	get_gt_port_base(GT_PCI0IOLD_OFS)
37 #define MALTA_BONITO_PORT_BASE	((unsigned long)ioremap (0x1fd00000, 0x10000))
38 #define MALTA_MSC_PORT_BASE	get_msc_port_base(MSC01_PCI_SC2PIOBASL)
39 
40 static inline unsigned long get_gt_port_base(unsigned long reg)
41 {
42 	unsigned long addr;
43 	addr = GT_READ(reg);
44 	return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
45 }
46 
47 static inline unsigned long get_msc_port_base(unsigned long reg)
48 {
49 	unsigned long addr;
50 	MSC_READ(reg, addr);
51 	return (unsigned long) ioremap(addr, 0x10000);
52 }
53 
54 /*
55  * GCMP Specific definitions
56  */
57 #define GCMP_BASE_ADDR			0x1fbf8000
58 #define GCMP_ADDRSPACE_SZ		(256 * 1024)
59 
60 /*
61  * GIC Specific definitions
62  */
63 #define GIC_BASE_ADDR			0x1bdc0000
64 #define GIC_ADDRSPACE_SZ		(128 * 1024)
65 
66 /*
67  * CPC Specific definitions
68  */
69 #define CPC_BASE_ADDR			0x1bde0000
70 
71 /*
72  * MSC01 BIU Specific definitions
73  * FIXME : These should be elsewhere ?
74  */
75 #define MSC01_BIU_REG_BASE		0x1bc80000
76 #define MSC01_BIU_ADDRSPACE_SZ		(256 * 1024)
77 #define MSC01_SC_CFG_OFS		0x0110
78 #define MSC01_SC_CFG_GICPRES_MSK	0x00000004
79 #define MSC01_SC_CFG_GICPRES_SHF	2
80 #define MSC01_SC_CFG_GICENA_SHF		3
81 
82 /*
83  * Malta RTC-device indirect register access.
84  */
85 #define MALTA_RTC_ADR_REG	0x70
86 #define MALTA_RTC_DAT_REG	0x71
87 
88 /*
89  * Malta SMSC FDC37M817 Super I/O Controller register.
90  */
91 #define SMSC_CONFIG_REG		0x3f0
92 #define SMSC_DATA_REG		0x3f1
93 
94 #define SMSC_CONFIG_DEVNUM	0x7
95 #define SMSC_CONFIG_ACTIVATE	0x30
96 #define SMSC_CONFIG_ENTER	0x55
97 #define SMSC_CONFIG_EXIT	0xaa
98 
99 #define SMSC_CONFIG_DEVNUM_FLOPPY     0
100 
101 #define SMSC_CONFIG_ACTIVATE_ENABLE   1
102 
103 #define SMSC_WRITE(x, a)     outb(x, a)
104 
105 #define MALTA_JMPRS_REG		0x1f000210
106 
107 #endif /* __ASM_MIPS_BOARDS_MALTA_H */
108