1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2384740dcSRalf Baechle /* 3384740dcSRalf Baechle * 4384740dcSRalf Baechle */ 5384740dcSRalf Baechle 6*6855adc2SRandy Dunlap #ifndef _ASM_MIPS_BOARDS_LAUNCH_H 7*6855adc2SRandy Dunlap #define _ASM_MIPS_BOARDS_LAUNCH_H 8*6855adc2SRandy Dunlap 9384740dcSRalf Baechle #ifndef _ASSEMBLER_ 10384740dcSRalf Baechle 11384740dcSRalf Baechle struct cpulaunch { 12384740dcSRalf Baechle unsigned long pc; 13384740dcSRalf Baechle unsigned long gp; 14384740dcSRalf Baechle unsigned long sp; 15384740dcSRalf Baechle unsigned long a0; 16384740dcSRalf Baechle unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */ 17384740dcSRalf Baechle unsigned long flags; 18384740dcSRalf Baechle }; 19384740dcSRalf Baechle 20384740dcSRalf Baechle #else 21384740dcSRalf Baechle 22384740dcSRalf Baechle #define LOG2CPULAUNCH 5 23384740dcSRalf Baechle #define LAUNCH_PC 0 24384740dcSRalf Baechle #define LAUNCH_GP 4 25384740dcSRalf Baechle #define LAUNCH_SP 8 26384740dcSRalf Baechle #define LAUNCH_A0 12 27384740dcSRalf Baechle #define LAUNCH_FLAGS 28 28384740dcSRalf Baechle 29384740dcSRalf Baechle #endif 30384740dcSRalf Baechle 31384740dcSRalf Baechle #define LAUNCH_FREADY 1 32384740dcSRalf Baechle #define LAUNCH_FGO 2 33384740dcSRalf Baechle #define LAUNCH_FGONE 4 34384740dcSRalf Baechle 35384740dcSRalf Baechle #define CPULAUNCH 0x00000f00 36384740dcSRalf Baechle #define NCPULAUNCH 8 37384740dcSRalf Baechle 38384740dcSRalf Baechle /* Polling period in count cycles for secondary CPU's */ 39384740dcSRalf Baechle #define LAUNCHPERIOD 10000 40*6855adc2SRandy Dunlap 41*6855adc2SRandy Dunlap #endif /* _ASM_MIPS_BOARDS_LAUNCH_H */ 42