1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Defines of the MIPS boards specific address-MAP, registers, etc. 7 * 8 * Copyright (C) 2000,2012 MIPS Technologies, Inc. 9 * All rights reserved. 10 * Authors: Carsten Langgaard <carstenl@mips.com> 11 * Steven J. Hill <sjhill@mips.com> 12 */ 13 #ifndef __ASM_MIPS_BOARDS_GENERIC_H 14 #define __ASM_MIPS_BOARDS_GENERIC_H 15 16 #include <asm/addrspace.h> 17 #include <asm/byteorder.h> 18 #include <asm/mips-boards/bonito64.h> 19 20 /* 21 * Display register base. 22 */ 23 #define ASCII_DISPLAY_WORD_BASE 0x1f000410 24 #define ASCII_DISPLAY_POS_BASE 0x1f000418 25 26 /* 27 * Reset register. 28 */ 29 #define SOFTRES_REG 0x1f000500 30 #define GORESET 0x42 31 32 /* 33 * Revision register. 34 */ 35 #define MIPS_REVISION_REG 0x1fc00010 36 #define MIPS_REVISION_CORID_QED_RM5261 0 37 #define MIPS_REVISION_CORID_CORE_LV 1 38 #define MIPS_REVISION_CORID_BONITO64 2 39 #define MIPS_REVISION_CORID_CORE_20K 3 40 #define MIPS_REVISION_CORID_CORE_FPGA 4 41 #define MIPS_REVISION_CORID_CORE_MSC 5 42 #define MIPS_REVISION_CORID_CORE_EMUL 6 43 #define MIPS_REVISION_CORID_CORE_FPGA2 7 44 #define MIPS_REVISION_CORID_CORE_FPGAR2 8 45 #define MIPS_REVISION_CORID_CORE_FPGA3 9 46 #define MIPS_REVISION_CORID_CORE_24K 10 47 #define MIPS_REVISION_CORID_CORE_FPGA4 11 48 #define MIPS_REVISION_CORID_CORE_FPGA5 12 49 50 /**** Artificial corid defines ****/ 51 /* 52 * CoreEMUL with Bonito System Controller is treated like a Core20K 53 * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC 54 */ 55 #define MIPS_REVISION_CORID_CORE_EMUL_BON -1 56 #define MIPS_REVISION_CORID_CORE_EMUL_MSC -2 57 58 #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 59 60 #define MIPS_REVISION_SCON_OTHER 0 61 #define MIPS_REVISION_SCON_SOCITSC 1 62 #define MIPS_REVISION_SCON_SOCITSCP 2 63 64 /* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */ 65 #define MIPS_REVISION_SCON_UNKNOWN -1 66 #define MIPS_REVISION_SCON_GT64120 -2 67 #define MIPS_REVISION_SCON_BONITO -3 68 #define MIPS_REVISION_SCON_BRTL -4 69 #define MIPS_REVISION_SCON_SOCIT -5 70 #define MIPS_REVISION_SCON_ROCIT -6 71 72 #define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff) 73 74 extern int mips_revision_sconid; 75 76 #ifdef CONFIG_OF 77 extern struct boot_param_header __dtb_start; 78 #endif 79 80 #ifdef CONFIG_PCI 81 extern void mips_pcibios_init(void); 82 #else 83 #define mips_pcibios_init() do { } while (0) 84 #endif 85 86 extern void mips_scroll_message(void); 87 extern void mips_display_message(const char *str); 88 89 #endif /* __ASM_MIPS_BOARDS_GENERIC_H */ 90