1384740dcSRalf Baechle /* 2384740dcSRalf Baechle * This program is free software; you can redistribute it and/or modify it 3384740dcSRalf Baechle * under the terms of the GNU General Public License as published by the 4384740dcSRalf Baechle * Free Software Foundation; either version 2 of the License, or (at your 5384740dcSRalf Baechle * option) any later version. 6384740dcSRalf Baechle * 7384740dcSRalf Baechle * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 8384740dcSRalf Baechle * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 9384740dcSRalf Baechle * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 10384740dcSRalf Baechle * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 11384740dcSRalf Baechle * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 12384740dcSRalf Baechle * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 13384740dcSRalf Baechle * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 14384740dcSRalf Baechle * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 15384740dcSRalf Baechle * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 16384740dcSRalf Baechle * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 17384740dcSRalf Baechle * 18384740dcSRalf Baechle * You should have received a copy of the GNU General Public License along 19384740dcSRalf Baechle * with this program; if not, write to the Free Software Foundation, Inc., 20384740dcSRalf Baechle * 675 Mass Ave, Cambridge, MA 02139, USA. 21384740dcSRalf Baechle * 22384740dcSRalf Baechle * Copyright 2004 IDT Inc. (rischelp@idt.com) 23384740dcSRalf Baechle * 24384740dcSRalf Baechle * Initial Release 25384740dcSRalf Baechle */ 26384740dcSRalf Baechle 27384740dcSRalf Baechle #ifndef _ASM_RC32434_PCI_H_ 28384740dcSRalf Baechle #define _ASM_RC32434_PCI_H_ 29384740dcSRalf Baechle 30384740dcSRalf Baechle #define epld_mask ((volatile unsigned char *)0xB900000d) 31384740dcSRalf Baechle 32384740dcSRalf Baechle #define PCI0_BASE_ADDR 0x18080000 33384740dcSRalf Baechle #define PCI_LBA_COUNT 4 34384740dcSRalf Baechle 35384740dcSRalf Baechle struct pci_map { 36384740dcSRalf Baechle u32 address; /* Address. */ 37384740dcSRalf Baechle u32 control; /* Control. */ 38384740dcSRalf Baechle u32 mapping; /* mapping. */ 39384740dcSRalf Baechle }; 40384740dcSRalf Baechle 41384740dcSRalf Baechle struct pci_reg { 42384740dcSRalf Baechle u32 pcic; 43384740dcSRalf Baechle u32 pcis; 44384740dcSRalf Baechle u32 pcism; 45384740dcSRalf Baechle u32 pcicfga; 46384740dcSRalf Baechle u32 pcicfgd; 47384740dcSRalf Baechle volatile struct pci_map pcilba[PCI_LBA_COUNT]; 48384740dcSRalf Baechle u32 pcidac; 49384740dcSRalf Baechle u32 pcidas; 50384740dcSRalf Baechle u32 pcidasm; 51384740dcSRalf Baechle u32 pcidad; 52384740dcSRalf Baechle u32 pcidma8c; 53384740dcSRalf Baechle u32 pcidma9c; 54384740dcSRalf Baechle u32 pcitc; 55384740dcSRalf Baechle }; 56384740dcSRalf Baechle 57384740dcSRalf Baechle #define PCI_MSU_COUNT 2 58384740dcSRalf Baechle 59384740dcSRalf Baechle struct pci_msu { 60384740dcSRalf Baechle u32 pciim[PCI_MSU_COUNT]; 61384740dcSRalf Baechle u32 pciom[PCI_MSU_COUNT]; 62384740dcSRalf Baechle u32 pciid; 63384740dcSRalf Baechle u32 pciiic; 64384740dcSRalf Baechle u32 pciiim; 65384740dcSRalf Baechle u32 pciiod; 66384740dcSRalf Baechle u32 pciioic; 67384740dcSRalf Baechle u32 pciioim; 68384740dcSRalf Baechle }; 69384740dcSRalf Baechle 70384740dcSRalf Baechle /* 71384740dcSRalf Baechle * PCI Control Register 72384740dcSRalf Baechle */ 73384740dcSRalf Baechle 74384740dcSRalf Baechle #define PCI_CTL_EN (1 << 0) 75384740dcSRalf Baechle #define PCI_CTL_TNR (1 << 1) 76384740dcSRalf Baechle #define PCI_CTL_SCE (1 << 2) 77384740dcSRalf Baechle #define PCI_CTL_IEN (1 << 3) 78384740dcSRalf Baechle #define PCI_CTL_AAA (1 << 4) 79384740dcSRalf Baechle #define PCI_CTL_EAP (1 << 5) 80384740dcSRalf Baechle #define PCI_CTL_PCIM_BIT 6 81384740dcSRalf Baechle #define PCI_CTL_PCIM 0x000001c0 82384740dcSRalf Baechle 83384740dcSRalf Baechle #define PCI_CTL_PCIM_DIS 0 84384740dcSRalf Baechle #define PCI_CTL_PCIM_TNR 1 /* Satellite - target not ready */ 85384740dcSRalf Baechle #define PCI_CTL_PCIM_SUS 2 /* Satellite - suspended CPU. */ 86384740dcSRalf Baechle #define PCI_CTL_PCIM_EXT 3 /* Host - external arbiter. */ 87384740dcSRalf Baechle #define PCI_CTL PCIM_PRIO 4 /* Host - fixed priority arb. */ 88384740dcSRalf Baechle #define PCI_CTL_PCIM_RR 5 /* Host - round robin priority. */ 89384740dcSRalf Baechle #define PCI_CTL_PCIM_RSVD6 6 90384740dcSRalf Baechle #define PCI_CTL_PCIM_RSVD7 7 91384740dcSRalf Baechle 92384740dcSRalf Baechle #define PCI_CTL_IGM (1 << 9) 93384740dcSRalf Baechle 94384740dcSRalf Baechle /* 95384740dcSRalf Baechle * PCI Status Register 96384740dcSRalf Baechle */ 97384740dcSRalf Baechle 98384740dcSRalf Baechle #define PCI_STAT_EED (1 << 0) 99384740dcSRalf Baechle #define PCI_STAT_WR (1 << 1) 100384740dcSRalf Baechle #define PCI_STAT_NMI (1 << 2) 101384740dcSRalf Baechle #define PCI_STAT_II (1 << 3) 102384740dcSRalf Baechle #define PCI_STAT_CWE (1 << 4) 103384740dcSRalf Baechle #define PCI_STAT_CRE (1 << 5) 104384740dcSRalf Baechle #define PCI_STAT_MDPE (1 << 6) 105384740dcSRalf Baechle #define PCI_STAT_STA (1 << 7) 106384740dcSRalf Baechle #define PCI_STAT_RTA (1 << 8) 107384740dcSRalf Baechle #define PCI_STAT_RMA (1 << 9) 108384740dcSRalf Baechle #define PCI_STAT_SSE (1 << 10) 109384740dcSRalf Baechle #define PCI_STAT_OSE (1 << 11) 110384740dcSRalf Baechle #define PCI_STAT_PE (1 << 12) 111384740dcSRalf Baechle #define PCI_STAT_TAE (1 << 13) 112384740dcSRalf Baechle #define PCI_STAT_RLE (1 << 14) 113384740dcSRalf Baechle #define PCI_STAT_BME (1 << 15) 114384740dcSRalf Baechle #define PCI_STAT_PRD (1 << 16) 115384740dcSRalf Baechle #define PCI_STAT_RIP (1 << 17) 116384740dcSRalf Baechle 117384740dcSRalf Baechle /* 118384740dcSRalf Baechle * PCI Status Mask Register 119384740dcSRalf Baechle */ 120384740dcSRalf Baechle 121384740dcSRalf Baechle #define PCI_STATM_EED PCI_STAT_EED 122384740dcSRalf Baechle #define PCI_STATM_WR PCI_STAT_WR 123384740dcSRalf Baechle #define PCI_STATM_NMI PCI_STAT_NMI 124384740dcSRalf Baechle #define PCI_STATM_II PCI_STAT_II 125384740dcSRalf Baechle #define PCI_STATM_CWE PCI_STAT_CWE 126384740dcSRalf Baechle #define PCI_STATM_CRE PCI_STAT_CRE 127384740dcSRalf Baechle #define PCI_STATM_MDPE PCI_STAT_MDPE 128384740dcSRalf Baechle #define PCI_STATM_STA PCI_STAT_STA 129384740dcSRalf Baechle #define PCI_STATM_RTA PCI_STAT_RTA 130384740dcSRalf Baechle #define PCI_STATM_RMA PCI_STAT_RMA 131384740dcSRalf Baechle #define PCI_STATM_SSE PCI_STAT_SSE 132384740dcSRalf Baechle #define PCI_STATM_OSE PCI_STAT_OSE 133384740dcSRalf Baechle #define PCI_STATM_PE PCI_STAT_PE 134384740dcSRalf Baechle #define PCI_STATM_TAE PCI_STAT_TAE 135384740dcSRalf Baechle #define PCI_STATM_RLE PCI_STAT_RLE 136384740dcSRalf Baechle #define PCI_STATM_BME PCI_STAT_BME 137384740dcSRalf Baechle #define PCI_STATM_PRD PCI_STAT_PRD 138384740dcSRalf Baechle #define PCI_STATM_RIP PCI_STAT_RIP 139384740dcSRalf Baechle 140384740dcSRalf Baechle /* 141384740dcSRalf Baechle * PCI Configuration Address Register 142384740dcSRalf Baechle */ 143384740dcSRalf Baechle #define PCI_CFGA_REG_BIT 2 144384740dcSRalf Baechle #define PCI_CFGA_REG 0x000000fc 145384740dcSRalf Baechle #define PCI_CFGA_REG_ID (0x00 >> 2) /* use PCFGID */ 146384740dcSRalf Baechle #define PCI_CFGA_REG_04 (0x04 >> 2) /* use PCFG04_ */ 147384740dcSRalf Baechle #define PCI_CFGA_REG_08 (0x08 >> 2) /* use PCFG08_ */ 148384740dcSRalf Baechle #define PCI_CFGA_REG_0C (0x0C >> 2) /* use PCFG0C_ */ 149384740dcSRalf Baechle #define PCI_CFGA_REG_PBA0 (0x10 >> 2) /* use PCIPBA_ */ 150384740dcSRalf Baechle #define PCI_CFGA_REG_PBA1 (0x14 >> 2) /* use PCIPBA_ */ 151384740dcSRalf Baechle #define PCI_CFGA_REG_PBA2 (0x18 >> 2) /* use PCIPBA_ */ 152384740dcSRalf Baechle #define PCI_CFGA_REG_PBA3 (0x1c >> 2) /* use PCIPBA_ */ 153384740dcSRalf Baechle #define PCI_CFGA_REG_SUBSYS (0x2c >> 2) /* use PCFGSS_ */ 154384740dcSRalf Baechle #define PCI_CFGA_REG_3C (0x3C >> 2) /* use PCFG3C_ */ 155384740dcSRalf Baechle #define PCI_CFGA_REG_PBBA0C (0x44 >> 2) /* use PCIPBAC_ */ 156384740dcSRalf Baechle #define PCI_CFGA_REG_PBA0M (0x48 >> 2) 157384740dcSRalf Baechle #define PCI_CFGA_REG_PBA1C (0x4c >> 2) /* use PCIPBAC_ */ 158384740dcSRalf Baechle #define PCI_CFGA_REG_PBA1M (0x50 >> 2) 159384740dcSRalf Baechle #define PCI_CFGA_REG_PBA2C (0x54 >> 2) /* use PCIPBAC_ */ 160384740dcSRalf Baechle #define PCI_CFGA_REG_PBA2M (0x58 >> 2) 161384740dcSRalf Baechle #define PCI_CFGA_REG_PBA3C (0x5c >> 2) /* use PCIPBAC_ */ 162384740dcSRalf Baechle #define PCI_CFGA_REG_PBA3M (0x60 >> 2) 163384740dcSRalf Baechle #define PCI_CFGA_REG_PMGT (0x64 >> 2) 164384740dcSRalf Baechle #define PCI_CFGA_FUNC_BIT 8 165384740dcSRalf Baechle #define PCI_CFGA_FUNC 0x00000700 166384740dcSRalf Baechle #define PCI_CFGA_DEV_BIT 11 167384740dcSRalf Baechle #define PCI_CFGA_DEV 0x0000f800 168384740dcSRalf Baechle #define PCI_CFGA_DEV_INTERN 0 169384740dcSRalf Baechle #define PCI_CFGA_BUS_BIT 16 170384740dcSRalf Baechle #define PCI CFGA_BUS 0x00ff0000 171384740dcSRalf Baechle #define PCI_CFGA_BUS_TYPE0 0 172384740dcSRalf Baechle #define PCI_CFGA_EN (1 << 31) 173384740dcSRalf Baechle 174384740dcSRalf Baechle /* PCI CFG04 commands */ 175384740dcSRalf Baechle #define PCI_CFG04_CMD_IO_ENA (1 << 0) 176384740dcSRalf Baechle #define PCI_CFG04_CMD_MEM_ENA (1 << 1) 177384740dcSRalf Baechle #define PCI_CFG04_CMD_BM_ENA (1 << 2) 178384740dcSRalf Baechle #define PCI_CFG04_CMD_MW_INV (1 << 4) 179384740dcSRalf Baechle #define PCI_CFG04_CMD_PAR_ENA (1 << 6) 180384740dcSRalf Baechle #define PCI_CFG04_CMD_SER_ENA (1 << 8) 181384740dcSRalf Baechle #define PCI_CFG04_CMD_FAST_ENA (1 << 9) 182384740dcSRalf Baechle 183384740dcSRalf Baechle /* PCI CFG04 status fields */ 184384740dcSRalf Baechle #define PCI_CFG04_STAT_BIT 16 185384740dcSRalf Baechle #define PCI_CFG04_STAT 0xffff0000 186384740dcSRalf Baechle #define PCI_CFG04_STAT_66_MHZ (1 << 21) 187384740dcSRalf Baechle #define PCI_CFG04_STAT_FBB (1 << 23) 188384740dcSRalf Baechle #define PCI_CFG04_STAT_MDPE (1 << 24) 189384740dcSRalf Baechle #define PCI_CFG04_STAT_DST (1 << 25) 190384740dcSRalf Baechle #define PCI_CFG04_STAT_STA (1 << 27) 191384740dcSRalf Baechle #define PCI_CFG04_STAT_RTA (1 << 28) 192384740dcSRalf Baechle #define PCI_CFG04_STAT_RMA (1 << 29) 193384740dcSRalf Baechle #define PCI_CFG04_STAT_SSE (1 << 30) 194384740dcSRalf Baechle #define PCI_CFG04_STAT_PE (1 << 31) 195384740dcSRalf Baechle 196384740dcSRalf Baechle #define PCI_PBA_MSI (1 << 0) 197384740dcSRalf Baechle #define PCI_PBA_P (1 << 2) 198384740dcSRalf Baechle 199384740dcSRalf Baechle /* PCI PBAC registers */ 200384740dcSRalf Baechle #define PCI_PBAC_MSI (1 << 0) 201384740dcSRalf Baechle #define PCI_PBAC_P (1 << 1) 202384740dcSRalf Baechle #define PCI_PBAC_SIZE_BIT 2 203384740dcSRalf Baechle #define PCI_PBAC_SIZE 0x0000007c 204384740dcSRalf Baechle #define PCI_PBAC_SB (1 << 7) 205384740dcSRalf Baechle #define PCI_PBAC_PP (1 << 8) 206384740dcSRalf Baechle #define PCI_PBAC_MR_BIT 9 207384740dcSRalf Baechle #define PCI_PBAC_MR 0x00000600 208384740dcSRalf Baechle #define PCI_PBAC_MR_RD 0 209384740dcSRalf Baechle #define PCI_PBAC_MR_RD_LINE 1 210384740dcSRalf Baechle #define PCI_PBAC_MR_RD_MULT 2 211384740dcSRalf Baechle #define PCI_PBAC_MRL (1 << 11) 212384740dcSRalf Baechle #define PCI_PBAC_MRM (1 << 12) 213384740dcSRalf Baechle #define PCI_PBAC_TRP (1 << 13) 214384740dcSRalf Baechle 215384740dcSRalf Baechle #define PCI_CFG40_TRDY_TIM 0x000000ff 216384740dcSRalf Baechle #define PCI_CFG40_RET_LIM 0x0000ff00 217384740dcSRalf Baechle 218384740dcSRalf Baechle /* 219384740dcSRalf Baechle * PCI Local Base Address [0|1|2|3] Register 220384740dcSRalf Baechle */ 221384740dcSRalf Baechle 222384740dcSRalf Baechle #define PCI_LBA_BADDR_BIT 0 223384740dcSRalf Baechle #define PCI_LBA_BADDR 0xffffff00 224384740dcSRalf Baechle 225384740dcSRalf Baechle /* 226384740dcSRalf Baechle * PCI Local Base Address Control Register 227384740dcSRalf Baechle */ 228384740dcSRalf Baechle 229384740dcSRalf Baechle #define PCI_LBAC_MSI (1 << 0) 230384740dcSRalf Baechle #define PCI_LBAC_MSI_MEM 0 231384740dcSRalf Baechle #define PCI_LBAC_MSI_IO 1 232384740dcSRalf Baechle #define PCI_LBAC_SIZE_BIT 2 233384740dcSRalf Baechle #define PCI_LBAC_SIZE 0x0000007c 234384740dcSRalf Baechle #define PCI_LBAC_SB (1 << 7) 235384740dcSRalf Baechle #define PCI_LBAC_RT (1 << 8) 236384740dcSRalf Baechle #define PCI_LBAC_RT_NO_PREF 0 237384740dcSRalf Baechle #define PCI_LBAC_RT_PREF 1 238384740dcSRalf Baechle 239384740dcSRalf Baechle /* 240384740dcSRalf Baechle * PCI Local Base Address [0|1|2|3] Mapping Register 241384740dcSRalf Baechle */ 242384740dcSRalf Baechle #define PCI_LBAM_MADDR_BIT 8 243384740dcSRalf Baechle #define PCI_LBAM_MADDR 0xffffff00 244384740dcSRalf Baechle 245384740dcSRalf Baechle /* 246384740dcSRalf Baechle * PCI Decoupled Access Control Register 247384740dcSRalf Baechle */ 248384740dcSRalf Baechle #define PCI_DAC_DEN (1 << 0) 249384740dcSRalf Baechle 250384740dcSRalf Baechle /* 251384740dcSRalf Baechle * PCI Decoupled Access Status Register 252384740dcSRalf Baechle */ 253384740dcSRalf Baechle #define PCI_DAS_D (1 << 0) 254384740dcSRalf Baechle #define PCI_DAS_B (1 << 1) 255384740dcSRalf Baechle #define PCI_DAS_E (1 << 2) 256384740dcSRalf Baechle #define PCI_DAS_OFE (1 << 3) 257384740dcSRalf Baechle #define PCI_DAS_OFF (1 << 4) 258384740dcSRalf Baechle #define PCI_DAS_IFE (1 << 5) 259384740dcSRalf Baechle #define PCI_DAS_IFF (1 << 6) 260384740dcSRalf Baechle 261384740dcSRalf Baechle /* 262384740dcSRalf Baechle * PCI DMA Channel 8 Configuration Register 263384740dcSRalf Baechle */ 264384740dcSRalf Baechle #define PCI_DMA8C_MBS_BIT 0 265384740dcSRalf Baechle #define PCI_DMA8C_MBS 0x00000fff /* Maximum Burst Size. */ 266384740dcSRalf Baechle #define PCI_DMA8C_OUR (1 << 12) 267384740dcSRalf Baechle 268384740dcSRalf Baechle /* 269384740dcSRalf Baechle * PCI DMA Channel 9 Configuration Register 270384740dcSRalf Baechle */ 271384740dcSRalf Baechle #define PCI_DMA9C_MBS_BIT 0 /* Maximum Burst Size. */ 272384740dcSRalf Baechle #define PCI_DMA9C_MBS 0x00000fff 273384740dcSRalf Baechle 274384740dcSRalf Baechle /* 275384740dcSRalf Baechle * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors 276384740dcSRalf Baechle */ 277384740dcSRalf Baechle 278384740dcSRalf Baechle #define PCI_DMAD_PT_BIT 22 /* in DEVCMD field (descriptor) */ 279384740dcSRalf Baechle #define PCI_DMAD_PT 0x00c00000 /* preferred transaction field */ 280384740dcSRalf Baechle /* These are for reads (DMA channel 8) */ 281384740dcSRalf Baechle #define PCI_DMAD_DEVCMD_MR 0 /* memory read */ 282384740dcSRalf Baechle #define PCI_DMAD_DEVCMD_MRL 1 /* memory read line */ 283384740dcSRalf Baechle #define PCI_DMAD_DEVCMD_MRM 2 /* memory read multiple */ 284384740dcSRalf Baechle #define PCI_DMAD_DEVCMD_IOR 3 /* I/O read */ 285384740dcSRalf Baechle /* These are for writes (DMA channel 9) */ 286384740dcSRalf Baechle #define PCI_DMAD_DEVCMD_MW 0 /* memory write */ 287384740dcSRalf Baechle #define PCI_DMAD_DEVCMD_MWI 1 /* memory write invalidate */ 288384740dcSRalf Baechle #define PCI_DMAD_DEVCMD_IOW 3 /* I/O write */ 289384740dcSRalf Baechle 290384740dcSRalf Baechle /* Swap byte field applies to both DMA channel 8 and 9 */ 291384740dcSRalf Baechle #define PCI_DMAD_SB (1 << 24) /* swap byte field */ 292384740dcSRalf Baechle 293384740dcSRalf Baechle 294384740dcSRalf Baechle /* 295384740dcSRalf Baechle * PCI Target Control Register 296384740dcSRalf Baechle */ 297384740dcSRalf Baechle 298384740dcSRalf Baechle #define PCI_TC_RTIMER_BIT 0 299384740dcSRalf Baechle #define PCI_TC_RTIMER 0x000000ff 300384740dcSRalf Baechle #define PCI_TC_DTIMER_BIT 8 301384740dcSRalf Baechle #define PCI_TC_DTIMER 0x0000ff00 302384740dcSRalf Baechle #define PCI_TC_RDR (1 << 18) 303384740dcSRalf Baechle #define PCI_TC_DDT (1 << 19) 304384740dcSRalf Baechle 305384740dcSRalf Baechle /* 306384740dcSRalf Baechle * PCI messaging unit [applies to both inbound and outbound registers ] 307384740dcSRalf Baechle */ 308384740dcSRalf Baechle #define PCI_MSU_M0 (1 << 0) 309384740dcSRalf Baechle #define PCI_MSU_M1 (1 << 1) 310384740dcSRalf Baechle #define PCI_MSU_DB (1 << 2) 311384740dcSRalf Baechle 312384740dcSRalf Baechle #define PCI_MSG_ADDR 0xB8088010 313384740dcSRalf Baechle #define PCI0_ADDR 0xB8080000 314384740dcSRalf Baechle #define rc32434_pci ((struct pci_reg *) PCI0_ADDR) 315384740dcSRalf Baechle #define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR) 316384740dcSRalf Baechle 317384740dcSRalf Baechle #define PCIM_SHFT 0x6 318384740dcSRalf Baechle #define PCIM_BIT_LEN 0x7 319384740dcSRalf Baechle #define PCIM_H_EA 0x3 320384740dcSRalf Baechle #define PCIM_H_IA_FIX 0x4 321384740dcSRalf Baechle #define PCIM_H_IA_RR 0x5 322384740dcSRalf Baechle 323384740dcSRalf Baechle #define PCI_ADDR_START 0x50000000 324384740dcSRalf Baechle 325384740dcSRalf Baechle #define CPUTOPCI_MEM_WIN 0x02000000 326384740dcSRalf Baechle #define CPUTOPCI_IO_WIN 0x00100000 327384740dcSRalf Baechle #define PCILBA_SIZE_SHFT 2 328384740dcSRalf Baechle #define PCILBA_SIZE_MASK 0x1F 329384740dcSRalf Baechle #define SIZE_256MB 0x1C 330384740dcSRalf Baechle #define SIZE_128MB 0x1B 331384740dcSRalf Baechle #define SIZE_64MB 0x1A 332384740dcSRalf Baechle #define SIZE_32MB 0x19 333384740dcSRalf Baechle #define SIZE_16MB 0x18 334384740dcSRalf Baechle #define SIZE_4MB 0x16 335384740dcSRalf Baechle #define SIZE_2MB 0x15 336384740dcSRalf Baechle #define SIZE_1MB 0x14 337384740dcSRalf Baechle #define KORINA_CONFIG0_ADDR 0x80000000 338384740dcSRalf Baechle #define KORINA_CONFIG1_ADDR 0x80000004 339384740dcSRalf Baechle #define KORINA_CONFIG2_ADDR 0x80000008 340384740dcSRalf Baechle #define KORINA_CONFIG3_ADDR 0x8000000C 341384740dcSRalf Baechle #define KORINA_CONFIG4_ADDR 0x80000010 342384740dcSRalf Baechle #define KORINA_CONFIG5_ADDR 0x80000014 343384740dcSRalf Baechle #define KORINA_CONFIG6_ADDR 0x80000018 344384740dcSRalf Baechle #define KORINA_CONFIG7_ADDR 0x8000001C 345384740dcSRalf Baechle #define KORINA_CONFIG8_ADDR 0x80000020 346384740dcSRalf Baechle #define KORINA_CONFIG9_ADDR 0x80000024 347384740dcSRalf Baechle #define KORINA_CONFIG10_ADDR 0x80000028 348384740dcSRalf Baechle #define KORINA_CONFIG11_ADDR 0x8000002C 349384740dcSRalf Baechle #define KORINA_CONFIG12_ADDR 0x80000030 350384740dcSRalf Baechle #define KORINA_CONFIG13_ADDR 0x80000034 351384740dcSRalf Baechle #define KORINA_CONFIG14_ADDR 0x80000038 352384740dcSRalf Baechle #define KORINA_CONFIG15_ADDR 0x8000003C 353384740dcSRalf Baechle #define KORINA_CONFIG16_ADDR 0x80000040 354384740dcSRalf Baechle #define KORINA_CONFIG17_ADDR 0x80000044 355384740dcSRalf Baechle #define KORINA_CONFIG18_ADDR 0x80000048 356384740dcSRalf Baechle #define KORINA_CONFIG19_ADDR 0x8000004C 357384740dcSRalf Baechle #define KORINA_CONFIG20_ADDR 0x80000050 358384740dcSRalf Baechle #define KORINA_CONFIG21_ADDR 0x80000054 359384740dcSRalf Baechle #define KORINA_CONFIG22_ADDR 0x80000058 360384740dcSRalf Baechle #define KORINA_CONFIG23_ADDR 0x8000005C 361384740dcSRalf Baechle #define KORINA_CONFIG24_ADDR 0x80000060 362384740dcSRalf Baechle #define KORINA_CONFIG25_ADDR 0x80000064 363384740dcSRalf Baechle #define KORINA_CMD (PCI_CFG04_CMD_IO_ENA | \ 364384740dcSRalf Baechle PCI_CFG04_CMD_MEM_ENA | \ 365384740dcSRalf Baechle PCI_CFG04_CMD_BM_ENA | \ 366384740dcSRalf Baechle PCI_CFG04_CMD_MW_INV | \ 367384740dcSRalf Baechle PCI_CFG04_CMD_PAR_ENA | \ 368384740dcSRalf Baechle PCI_CFG04_CMD_SER_ENA) 369384740dcSRalf Baechle 370384740dcSRalf Baechle #define KORINA_STAT (PCI_CFG04_STAT_MDPE | \ 371384740dcSRalf Baechle PCI_CFG04_STAT_STA | \ 372384740dcSRalf Baechle PCI_CFG04_STAT_RTA | \ 373384740dcSRalf Baechle PCI_CFG04_STAT_RMA | \ 374384740dcSRalf Baechle PCI_CFG04_STAT_SSE | \ 375384740dcSRalf Baechle PCI_CFG04_STAT_PE) 376384740dcSRalf Baechle 377*109d587aSxurui #define KORINA_CNFG1 (KORINA_STAT | KORINA_CMD) 378384740dcSRalf Baechle 379384740dcSRalf Baechle #define KORINA_REVID 0 380384740dcSRalf Baechle #define KORINA_CLASS_CODE 0 381384740dcSRalf Baechle #define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \ 382384740dcSRalf Baechle KORINA_REVID) 383384740dcSRalf Baechle 384384740dcSRalf Baechle #define KORINA_CACHE_LINE_SIZE 4 385384740dcSRalf Baechle #define KORINA_MASTER_LAT 0x3c 386384740dcSRalf Baechle #define KORINA_HEADER_TYPE 0 387384740dcSRalf Baechle #define KORINA_BIST 0 388384740dcSRalf Baechle 389384740dcSRalf Baechle #define KORINA_CNFG3 ((KORINA_BIST << 24) | \ 390384740dcSRalf Baechle (KORINA_HEADER_TYPE<<16) | \ 391384740dcSRalf Baechle (KORINA_MASTER_LAT<<8) | \ 392384740dcSRalf Baechle KORINA_CACHE_LINE_SIZE) 393384740dcSRalf Baechle 394384740dcSRalf Baechle #define KORINA_BAR0 0x00000008 /* 128 MB Memory */ 395384740dcSRalf Baechle #define KORINA_BAR1 0x18800001 /* 1 MB IO */ 396384740dcSRalf Baechle #define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina 397384740dcSRalf Baechle internal Registers */ 398384740dcSRalf Baechle #define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */ 399384740dcSRalf Baechle 400384740dcSRalf Baechle #define KORINA_CNFG4 KORINA_BAR0 401384740dcSRalf Baechle #define KORINA_CNFG5 KORINA_BAR1 402384740dcSRalf Baechle #define KORINA_CNFG6 KORINA_BAR2 403384740dcSRalf Baechle #define KORINA_CNFG7 KORINA_BAR3 404384740dcSRalf Baechle 405384740dcSRalf Baechle #define KORINA_SUBSYS_VENDOR_ID 0x011d 406384740dcSRalf Baechle #define KORINA_SUBSYSTEM_ID 0x0214 407384740dcSRalf Baechle #define KORINA_CNFG8 0 408384740dcSRalf Baechle #define KORINA_CNFG9 0 409384740dcSRalf Baechle #define KORINA_CNFG10 0 410384740dcSRalf Baechle #define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ 411384740dcSRalf Baechle KORINA_SUBSYSTEM_ID) 412384740dcSRalf Baechle #define KORINA_INT_LINE 1 413384740dcSRalf Baechle #define KORINA_INT_PIN 1 414384740dcSRalf Baechle #define KORINA_MIN_GNT 8 415384740dcSRalf Baechle #define KORINA_MAX_LAT 0x38 416384740dcSRalf Baechle #define KORINA_CNFG12 0 417384740dcSRalf Baechle #define KORINA_CNFG13 0 418384740dcSRalf Baechle #define KORINA_CNFG14 0 419384740dcSRalf Baechle #define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \ 420384740dcSRalf Baechle (KORINA_MIN_GNT<<16) | \ 421384740dcSRalf Baechle (KORINA_INT_PIN<<8) | \ 422384740dcSRalf Baechle KORINA_INT_LINE) 423384740dcSRalf Baechle #define KORINA_RETRY_LIMIT 0x80 424384740dcSRalf Baechle #define KORINA_TRDY_LIMIT 0x80 425384740dcSRalf Baechle #define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \ 426384740dcSRalf Baechle KORINA_TRDY_LIMIT) 427384740dcSRalf Baechle #define PCI_PBAxC_R 0x0 428384740dcSRalf Baechle #define PCI_PBAxC_RL 0x1 429384740dcSRalf Baechle #define PCI_PBAxC_RM 0x2 430384740dcSRalf Baechle #define SIZE_SHFT 2 431384740dcSRalf Baechle 432384740dcSRalf Baechle #if defined(__MIPSEB__) 433384740dcSRalf Baechle #define KORINA_PBA0C (PCI_PBAC_MRL | PCI_PBAC_SB | \ 434384740dcSRalf Baechle ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \ 435384740dcSRalf Baechle PCI_PBAC_PP | \ 436384740dcSRalf Baechle (SIZE_128MB<<SIZE_SHFT) | \ 437384740dcSRalf Baechle PCI_PBAC_P) 438384740dcSRalf Baechle #else 439384740dcSRalf Baechle #define KORINA_PBA0C (PCI_PBAC_MRL | \ 440384740dcSRalf Baechle ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \ 441384740dcSRalf Baechle PCI_PBAC_PP | \ 442384740dcSRalf Baechle (SIZE_128MB<<SIZE_SHFT) | \ 443384740dcSRalf Baechle PCI_PBAC_P) 444384740dcSRalf Baechle #endif 445384740dcSRalf Baechle #define KORINA_CNFG17 KORINA_PBA0C 446384740dcSRalf Baechle #define KORINA_PBA0M 0x0 447384740dcSRalf Baechle #define KORINA_CNFG18 KORINA_PBA0M 448384740dcSRalf Baechle 449384740dcSRalf Baechle #if defined(__MIPSEB__) 450384740dcSRalf Baechle #define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \ 451384740dcSRalf Baechle PCI_PBAC_MSI) 452384740dcSRalf Baechle #else 453384740dcSRalf Baechle #define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \ 454384740dcSRalf Baechle PCI_PBAC_MSI) 455384740dcSRalf Baechle #endif 456384740dcSRalf Baechle #define KORINA_CNFG19 KORINA_PBA1C 457384740dcSRalf Baechle #define KORINA_PBA1M 0x0 458384740dcSRalf Baechle #define KORINA_CNFG20 KORINA_PBA1M 459384740dcSRalf Baechle 460384740dcSRalf Baechle #if defined(__MIPSEB__) 461384740dcSRalf Baechle #define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \ 462384740dcSRalf Baechle PCI_PBAC_MSI) 463384740dcSRalf Baechle #else 464384740dcSRalf Baechle #define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \ 465384740dcSRalf Baechle PCI_PBAC_MSI) 466384740dcSRalf Baechle #endif 467384740dcSRalf Baechle #define KORINA_CNFG21 KORINA_PBA2C 468384740dcSRalf Baechle #define KORINA_PBA2M 0x18000000 469384740dcSRalf Baechle #define KORINA_CNFG22 KORINA_PBA2M 470384740dcSRalf Baechle #define KORINA_PBA3C 0 471384740dcSRalf Baechle #define KORINA_CNFG23 KORINA_PBA3C 472384740dcSRalf Baechle #define KORINA_PBA3M 0 473384740dcSRalf Baechle #define KORINA_CNFG24 KORINA_PBA3M 474384740dcSRalf Baechle 475384740dcSRalf Baechle #define PCITC_DTIMER_VAL 8 476384740dcSRalf Baechle #define PCITC_RTIMER_VAL 0x10 477384740dcSRalf Baechle 478384740dcSRalf Baechle #endif /* __ASM_RC32434_PCI_H */ 479