1 /*
2  *  IDT RC32434 specific CPU feature overrides
3  *
4  *  Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
5  *
6  *  This file was derived from: include/asm-mips/cpu-features.h
7  *	Copyright (C) 2003, 2004 Ralf Baechle
8  *	Copyright (C) 2004 Maciej W. Rozycki
9  *
10  *  This program is free software; you can redistribute it and/or
11  *  modify it under the terms of the GNU General Public License
12  *  as published by the Free Software Foundation; either version 2
13  *  of the License, or (at your option) any later version.
14  *
15  *  This program is distributed in the hope that it will be useful,
16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *  GNU General Public License for more details.
19  *
20  *  You should have received a copy of the GNU General Public License
21  *  along with this program; if not, write to the
22  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
23  *  Boston, MA  02110-1301, USA.
24  */
25 #ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
26 #define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
27 
28 /*
29  * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
30  */
31 #define cpu_has_tlb			1
32 #define cpu_has_4kex			1
33 #define cpu_has_3k_cache		0
34 #define cpu_has_4k_cache		1
35 #define cpu_has_tx39_cache		0
36 #define cpu_has_sb1_cache		0
37 #define cpu_has_fpu			0
38 #define cpu_has_32fpr			0
39 #define cpu_has_counter			1
40 #define cpu_has_watch			1
41 #define cpu_has_divec			1
42 #define cpu_has_vce			0
43 #define cpu_has_cache_cdex_p		0
44 #define cpu_has_cache_cdex_s		0
45 #define cpu_has_prefetch		1
46 #define cpu_has_mcheck			1
47 #define cpu_has_ejtag			1
48 #define cpu_has_llsc			1
49 
50 #define cpu_has_mips16			0
51 #define cpu_has_mdmx			0
52 #define cpu_has_mips3d			0
53 #define cpu_has_smartmips		0
54 
55 #define cpu_has_vtag_icache		0
56 /* #define cpu_has_dc_aliases		? */
57 /* #define cpu_has_ic_fills_f_dc	? */
58 /* #define cpu_has_pindexed_dcache	? */
59 
60 /* #define cpu_icache_snoops_remote_store	? */
61 
62 #define cpu_has_mips32r1		1
63 #define cpu_has_mips32r2		0
64 #define cpu_has_mips64r1		0
65 #define cpu_has_mips64r2		0
66 
67 #define cpu_has_dsp			0
68 #define cpu_has_mipsmt			0
69 
70 /* #define cpu_has_nofpuex		? */
71 #define cpu_has_64bits			0
72 #define cpu_has_64bit_zero_reg		0
73 #define cpu_has_64bit_gp_regs		0
74 #define cpu_has_64bit_addresses		0
75 
76 #define cpu_has_inclusive_pcaches	0
77 
78 #define cpu_dcache_line_size()		16
79 #define cpu_icache_line_size()		16
80 
81 #endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
82