1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  *  IDT RC32434 specific CPU feature overrides
4  *
5  *  Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
6  *
7  *  This file was derived from: include/asm-mips/cpu-features.h
8  *	Copyright (C) 2003, 2004 Ralf Baechle
9  *	Copyright (C) 2004 Maciej W. Rozycki
10  */
11 #ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
12 #define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
13 
14 /*
15  * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
16  */
17 #define cpu_has_tlb			1
18 #define cpu_has_4kex			1
19 #define cpu_has_3k_cache		0
20 #define cpu_has_4k_cache		1
21 #define cpu_has_tx39_cache		0
22 #define cpu_has_sb1_cache		0
23 #define cpu_has_fpu			0
24 #define cpu_has_32fpr			0
25 #define cpu_has_counter			1
26 #define cpu_has_watch			1
27 #define cpu_has_divec			1
28 #define cpu_has_vce			0
29 #define cpu_has_cache_cdex_p		0
30 #define cpu_has_cache_cdex_s		0
31 #define cpu_has_prefetch		1
32 #define cpu_has_mcheck			1
33 #define cpu_has_ejtag			1
34 #define cpu_has_llsc			1
35 
36 #define cpu_has_mips16			0
37 #define cpu_has_mips16e2		0
38 #define cpu_has_mdmx			0
39 #define cpu_has_mips3d			0
40 #define cpu_has_smartmips		0
41 
42 #define cpu_has_vtag_icache		0
43 
44 #define cpu_has_mips32r1		1
45 #define cpu_has_mips32r2		0
46 #define cpu_has_mips64r1		0
47 #define cpu_has_mips64r2		0
48 
49 #define cpu_has_dsp			0
50 #define cpu_has_dsp2			0
51 #define cpu_has_mipsmt			0
52 
53 /* #define cpu_has_nofpuex		? */
54 #define cpu_has_64bits			0
55 #define cpu_has_64bit_zero_reg		0
56 #define cpu_has_64bit_gp_regs		0
57 #define cpu_has_64bit_addresses		0
58 
59 #define cpu_has_inclusive_pcaches	0
60 
61 #define cpu_dcache_line_size()		16
62 #define cpu_icache_line_size()		16
63 
64 #endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
65