116216333SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2384740dcSRalf Baechle /* 3384740dcSRalf Baechle * IDT RC32434 specific CPU feature overrides 4384740dcSRalf Baechle * 5384740dcSRalf Baechle * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> 6384740dcSRalf Baechle * 7384740dcSRalf Baechle * This file was derived from: include/asm-mips/cpu-features.h 8384740dcSRalf Baechle * Copyright (C) 2003, 2004 Ralf Baechle 9384740dcSRalf Baechle * Copyright (C) 2004 Maciej W. Rozycki 10384740dcSRalf Baechle */ 11384740dcSRalf Baechle #ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H 12384740dcSRalf Baechle #define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H 13384740dcSRalf Baechle 14384740dcSRalf Baechle /* 15384740dcSRalf Baechle * The IDT RC32434 SOC has a built-in MIPS 4Kc core. 16384740dcSRalf Baechle */ 17384740dcSRalf Baechle #define cpu_has_tlb 1 18384740dcSRalf Baechle #define cpu_has_4kex 1 19384740dcSRalf Baechle #define cpu_has_3k_cache 0 20384740dcSRalf Baechle #define cpu_has_4k_cache 1 21384740dcSRalf Baechle #define cpu_has_sb1_cache 0 22384740dcSRalf Baechle #define cpu_has_fpu 0 23384740dcSRalf Baechle #define cpu_has_32fpr 0 24384740dcSRalf Baechle #define cpu_has_counter 1 25384740dcSRalf Baechle #define cpu_has_watch 1 26384740dcSRalf Baechle #define cpu_has_divec 1 27384740dcSRalf Baechle #define cpu_has_vce 0 28384740dcSRalf Baechle #define cpu_has_cache_cdex_p 0 29384740dcSRalf Baechle #define cpu_has_cache_cdex_s 0 30384740dcSRalf Baechle #define cpu_has_prefetch 1 31384740dcSRalf Baechle #define cpu_has_mcheck 1 32384740dcSRalf Baechle #define cpu_has_ejtag 1 33384740dcSRalf Baechle #define cpu_has_llsc 1 34384740dcSRalf Baechle 35384740dcSRalf Baechle #define cpu_has_mips16 0 3665ae8d26SMaciej W. Rozycki #define cpu_has_mips16e2 0 37384740dcSRalf Baechle #define cpu_has_mdmx 0 38384740dcSRalf Baechle #define cpu_has_mips3d 0 39384740dcSRalf Baechle #define cpu_has_smartmips 0 40384740dcSRalf Baechle 41384740dcSRalf Baechle #define cpu_has_vtag_icache 0 42384740dcSRalf Baechle 43384740dcSRalf Baechle #define cpu_has_mips32r1 1 44384740dcSRalf Baechle #define cpu_has_mips32r2 0 45384740dcSRalf Baechle #define cpu_has_mips64r1 0 46384740dcSRalf Baechle #define cpu_has_mips64r2 0 47384740dcSRalf Baechle 48384740dcSRalf Baechle #define cpu_has_dsp 0 4947503256SRalf Baechle #define cpu_has_dsp2 0 50384740dcSRalf Baechle #define cpu_has_mipsmt 0 51384740dcSRalf Baechle 52384740dcSRalf Baechle /* #define cpu_has_nofpuex ? */ 53384740dcSRalf Baechle #define cpu_has_64bits 0 54384740dcSRalf Baechle #define cpu_has_64bit_zero_reg 0 55384740dcSRalf Baechle #define cpu_has_64bit_gp_regs 0 56384740dcSRalf Baechle 57384740dcSRalf Baechle #define cpu_has_inclusive_pcaches 0 58384740dcSRalf Baechle 59384740dcSRalf Baechle #define cpu_dcache_line_size() 16 60384740dcSRalf Baechle #define cpu_icache_line_size() 16 61384740dcSRalf Baechle 62384740dcSRalf Baechle #endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */ 63