1 /*
2  * Ralink RT3662/RT3883 SoC register definitions
3  *
4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation.
9  */
10 
11 #ifndef _RT3883_REGS_H_
12 #define _RT3883_REGS_H_
13 
14 #include <linux/bitops.h>
15 
16 #define RT3883_SDRAM_BASE	0x00000000
17 #define RT3883_SYSC_BASE	0x10000000
18 #define RT3883_TIMER_BASE	0x10000100
19 #define RT3883_INTC_BASE	0x10000200
20 #define RT3883_MEMC_BASE	0x10000300
21 #define RT3883_UART0_BASE	0x10000500
22 #define RT3883_PIO_BASE		0x10000600
23 #define RT3883_FSCC_BASE	0x10000700
24 #define RT3883_NANDC_BASE	0x10000810
25 #define RT3883_I2C_BASE		0x10000900
26 #define RT3883_I2S_BASE		0x10000a00
27 #define RT3883_SPI_BASE		0x10000b00
28 #define RT3883_UART1_BASE	0x10000c00
29 #define RT3883_PCM_BASE		0x10002000
30 #define RT3883_GDMA_BASE	0x10002800
31 #define RT3883_CODEC1_BASE	0x10003000
32 #define RT3883_CODEC2_BASE	0x10003800
33 #define RT3883_FE_BASE		0x10100000
34 #define RT3883_ROM_BASE		0x10118000
35 #define RT3883_USBDEV_BASE	0x10112000
36 #define RT3883_PCI_BASE		0x10140000
37 #define RT3883_WLAN_BASE	0x10180000
38 #define RT3883_USBHOST_BASE	0x101c0000
39 #define RT3883_BOOT_BASE	0x1c000000
40 #define RT3883_SRAM_BASE	0x1e000000
41 #define RT3883_PCIMEM_BASE	0x20000000
42 
43 #define RT3883_EHCI_BASE	(RT3883_USBHOST_BASE)
44 #define RT3883_OHCI_BASE	(RT3883_USBHOST_BASE + 0x1000)
45 
46 #define RT3883_SYSC_SIZE	0x100
47 #define RT3883_TIMER_SIZE	0x100
48 #define RT3883_INTC_SIZE	0x100
49 #define RT3883_MEMC_SIZE	0x100
50 #define RT3883_UART0_SIZE	0x100
51 #define RT3883_UART1_SIZE	0x100
52 #define RT3883_PIO_SIZE		0x100
53 #define RT3883_FSCC_SIZE	0x100
54 #define RT3883_NANDC_SIZE	0x0f0
55 #define RT3883_I2C_SIZE		0x100
56 #define RT3883_I2S_SIZE		0x100
57 #define RT3883_SPI_SIZE		0x100
58 #define RT3883_PCM_SIZE		0x800
59 #define RT3883_GDMA_SIZE	0x800
60 #define RT3883_CODEC1_SIZE	0x800
61 #define RT3883_CODEC2_SIZE	0x800
62 #define RT3883_FE_SIZE		0x10000
63 #define RT3883_ROM_SIZE		0x4000
64 #define RT3883_USBDEV_SIZE	0x4000
65 #define RT3883_PCI_SIZE		0x40000
66 #define RT3883_WLAN_SIZE	0x40000
67 #define RT3883_USBHOST_SIZE	0x40000
68 #define RT3883_BOOT_SIZE	(32 * 1024 * 1024)
69 #define RT3883_SRAM_SIZE	(32 * 1024 * 1024)
70 
71 /* SYSC registers */
72 #define RT3883_SYSC_REG_CHIPID0_3	0x00	/* Chip ID 0 */
73 #define RT3883_SYSC_REG_CHIPID4_7	0x04	/* Chip ID 1 */
74 #define RT3883_SYSC_REG_REVID		0x0c	/* Chip Revision Identification */
75 #define RT3883_SYSC_REG_SYSCFG0		0x10	/* System Configuration 0 */
76 #define RT3883_SYSC_REG_SYSCFG1		0x14	/* System Configuration 1 */
77 #define RT3883_SYSC_REG_CLKCFG0		0x2c	/* Clock Configuration 0 */
78 #define RT3883_SYSC_REG_CLKCFG1		0x30	/* Clock Configuration 1 */
79 #define RT3883_SYSC_REG_RSTCTRL		0x34	/* Reset Control*/
80 #define RT3883_SYSC_REG_RSTSTAT		0x38	/* Reset Status*/
81 #define RT3883_SYSC_REG_USB_PS		0x5c	/* USB Power saving control */
82 #define RT3883_SYSC_REG_GPIO_MODE	0x60	/* GPIO Purpose Select */
83 #define RT3883_SYSC_REG_PCIE_CLK_GEN0	0x7c
84 #define RT3883_SYSC_REG_PCIE_CLK_GEN1	0x80
85 #define RT3883_SYSC_REG_PCIE_CLK_GEN2	0x84
86 #define RT3883_SYSC_REG_PMU		0x88
87 #define RT3883_SYSC_REG_PMU1		0x8c
88 
89 #define RT3883_CHIP_NAME0		0x38335452
90 #define RT3883_CHIP_NAME1		0x20203338
91 
92 #define RT3883_REVID_VER_ID_MASK	0x0f
93 #define RT3883_REVID_VER_ID_SHIFT	8
94 #define RT3883_REVID_ECO_ID_MASK	0x0f
95 
96 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2	BIT(17)
97 #define RT3883_SYSCFG0_CPUCLK_SHIFT	8
98 #define RT3883_SYSCFG0_CPUCLK_MASK	0x3
99 #define RT3883_SYSCFG0_CPUCLK_250	0x0
100 #define RT3883_SYSCFG0_CPUCLK_384	0x1
101 #define RT3883_SYSCFG0_CPUCLK_480	0x2
102 #define RT3883_SYSCFG0_CPUCLK_500	0x3
103 
104 #define RT3883_SYSCFG1_USB0_HOST_MODE	BIT(10)
105 #define RT3883_SYSCFG1_PCIE_RC_MODE	BIT(8)
106 #define RT3883_SYSCFG1_PCI_HOST_MODE	BIT(7)
107 #define RT3883_SYSCFG1_PCI_66M_MODE	BIT(6)
108 #define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT	BIT(2)
109 
110 #define RT3883_CLKCFG1_PCIE_CLK_EN	BIT(21)
111 #define RT3883_CLKCFG1_UPHY1_CLK_EN	BIT(20)
112 #define RT3883_CLKCFG1_PCI_CLK_EN	BIT(19)
113 #define RT3883_CLKCFG1_UPHY0_CLK_EN	BIT(18)
114 
115 #define RT3883_GPIO_MODE_I2C		BIT(0)
116 #define RT3883_GPIO_MODE_SPI		BIT(1)
117 #define RT3883_GPIO_MODE_UART0_SHIFT	2
118 #define RT3883_GPIO_MODE_UART0_MASK	0x7
119 #define RT3883_GPIO_MODE_UART0(x)	((x) << RT3883_GPIO_MODE_UART0_SHIFT)
120 #define RT3883_GPIO_MODE_UARTF		0x0
121 #define RT3883_GPIO_MODE_PCM_UARTF	0x1
122 #define RT3883_GPIO_MODE_PCM_I2S	0x2
123 #define RT3883_GPIO_MODE_I2S_UARTF	0x3
124 #define RT3883_GPIO_MODE_PCM_GPIO	0x4
125 #define RT3883_GPIO_MODE_GPIO_UARTF	0x5
126 #define RT3883_GPIO_MODE_GPIO_I2S	0x6
127 #define RT3883_GPIO_MODE_GPIO		0x7
128 #define RT3883_GPIO_MODE_UART1		BIT(5)
129 #define RT3883_GPIO_MODE_JTAG		BIT(6)
130 #define RT3883_GPIO_MODE_MDIO		BIT(7)
131 #define RT3883_GPIO_MODE_GE1		BIT(9)
132 #define RT3883_GPIO_MODE_GE2		BIT(10)
133 #define RT3883_GPIO_MODE_PCI_SHIFT	11
134 #define RT3883_GPIO_MODE_PCI_MASK	0x7
135 #define RT3883_GPIO_MODE_PCI		(RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
136 #define RT3883_GPIO_MODE_LNA_A_SHIFT	16
137 #define RT3883_GPIO_MODE_LNA_A_MASK	0x3
138 #define _RT3883_GPIO_MODE_LNA_A(_x)	((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT)
139 #define RT3883_GPIO_MODE_LNA_A_GPIO	0x3
140 #define RT3883_GPIO_MODE_LNA_A		_RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK)
141 #define RT3883_GPIO_MODE_LNA_G_SHIFT	18
142 #define RT3883_GPIO_MODE_LNA_G_MASK	0x3
143 #define _RT3883_GPIO_MODE_LNA_G(_x)	((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT)
144 #define RT3883_GPIO_MODE_LNA_G_GPIO	0x3
145 #define RT3883_GPIO_MODE_LNA_G		_RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK)
146 
147 #define RT3883_GPIO_I2C_SD		1
148 #define RT3883_GPIO_I2C_SCLK		2
149 #define RT3883_GPIO_SPI_CS0		3
150 #define RT3883_GPIO_SPI_CLK		4
151 #define RT3883_GPIO_SPI_MOSI		5
152 #define RT3883_GPIO_SPI_MISO		6
153 #define RT3883_GPIO_7			7
154 #define RT3883_GPIO_10			10
155 #define RT3883_GPIO_11			11
156 #define RT3883_GPIO_14			14
157 #define RT3883_GPIO_UART1_TXD		15
158 #define RT3883_GPIO_UART1_RXD		16
159 #define RT3883_GPIO_JTAG_TDO		17
160 #define RT3883_GPIO_JTAG_TDI		18
161 #define RT3883_GPIO_JTAG_TMS		19
162 #define RT3883_GPIO_JTAG_TCLK		20
163 #define RT3883_GPIO_JTAG_TRST_N		21
164 #define RT3883_GPIO_MDIO_MDC		22
165 #define RT3883_GPIO_MDIO_MDIO		23
166 #define RT3883_GPIO_LNA_PE_A0		32
167 #define RT3883_GPIO_LNA_PE_A1		33
168 #define RT3883_GPIO_LNA_PE_A2		34
169 #define RT3883_GPIO_LNA_PE_G0		35
170 #define RT3883_GPIO_LNA_PE_G1		36
171 #define RT3883_GPIO_LNA_PE_G2		37
172 #define RT3883_GPIO_PCI_AD0		40
173 #define RT3883_GPIO_PCI_AD31		71
174 #define RT3883_GPIO_GE2_TXD0		72
175 #define RT3883_GPIO_GE2_TXD1		73
176 #define RT3883_GPIO_GE2_TXD2		74
177 #define RT3883_GPIO_GE2_TXD3		75
178 #define RT3883_GPIO_GE2_TXEN		76
179 #define RT3883_GPIO_GE2_TXCLK		77
180 #define RT3883_GPIO_GE2_RXD0		78
181 #define RT3883_GPIO_GE2_RXD1		79
182 #define RT3883_GPIO_GE2_RXD2		80
183 #define RT3883_GPIO_GE2_RXD3		81
184 #define RT3883_GPIO_GE2_RXDV		82
185 #define RT3883_GPIO_GE2_RXCLK		83
186 #define RT3883_GPIO_GE1_TXD0		84
187 #define RT3883_GPIO_GE1_TXD1		85
188 #define RT3883_GPIO_GE1_TXD2		86
189 #define RT3883_GPIO_GE1_TXD3		87
190 #define RT3883_GPIO_GE1_TXEN		88
191 #define RT3883_GPIO_GE1_TXCLK		89
192 #define RT3883_GPIO_GE1_RXD0		90
193 #define RT3883_GPIO_GE1_RXD1		91
194 #define RT3883_GPIO_GE1_RXD2		92
195 #define RT3883_GPIO_GE1_RXD3		93
196 #define RT3883_GPIO_GE1_RXDV		94
197 #define RT3883_GPIO_GE1_RXCLK	95
198 
199 #define RT3883_RSTCTRL_PCIE_PCI_PDM	BIT(27)
200 #define RT3883_RSTCTRL_FLASH		BIT(26)
201 #define RT3883_RSTCTRL_UDEV		BIT(25)
202 #define RT3883_RSTCTRL_PCI		BIT(24)
203 #define RT3883_RSTCTRL_PCIE		BIT(23)
204 #define RT3883_RSTCTRL_UHST		BIT(22)
205 #define RT3883_RSTCTRL_FE		BIT(21)
206 #define RT3883_RSTCTRL_WLAN		BIT(20)
207 #define RT3883_RSTCTRL_UART1		BIT(29)
208 #define RT3883_RSTCTRL_SPI		BIT(18)
209 #define RT3883_RSTCTRL_I2S		BIT(17)
210 #define RT3883_RSTCTRL_I2C		BIT(16)
211 #define RT3883_RSTCTRL_NAND		BIT(15)
212 #define RT3883_RSTCTRL_DMA		BIT(14)
213 #define RT3883_RSTCTRL_PIO		BIT(13)
214 #define RT3883_RSTCTRL_UART		BIT(12)
215 #define RT3883_RSTCTRL_PCM		BIT(11)
216 #define RT3883_RSTCTRL_MC		BIT(10)
217 #define RT3883_RSTCTRL_INTC		BIT(9)
218 #define RT3883_RSTCTRL_TIMER		BIT(8)
219 #define RT3883_RSTCTRL_SYS		BIT(0)
220 
221 #define RT3883_INTC_INT_SYSCTL	BIT(0)
222 #define RT3883_INTC_INT_TIMER0	BIT(1)
223 #define RT3883_INTC_INT_TIMER1	BIT(2)
224 #define RT3883_INTC_INT_IA	BIT(3)
225 #define RT3883_INTC_INT_PCM	BIT(4)
226 #define RT3883_INTC_INT_UART0	BIT(5)
227 #define RT3883_INTC_INT_PIO	BIT(6)
228 #define RT3883_INTC_INT_DMA	BIT(7)
229 #define RT3883_INTC_INT_NAND	BIT(8)
230 #define RT3883_INTC_INT_PERFC	BIT(9)
231 #define RT3883_INTC_INT_I2S	BIT(10)
232 #define RT3883_INTC_INT_UART1	BIT(12)
233 #define RT3883_INTC_INT_UHST	BIT(18)
234 #define RT3883_INTC_INT_UDEV	BIT(19)
235 
236 /* FLASH/SRAM/Codec Controller registers */
237 #define RT3883_FSCC_REG_FLASH_CFG0	0x00
238 #define RT3883_FSCC_REG_FLASH_CFG1	0x04
239 #define RT3883_FSCC_REG_CODEC_CFG0	0x40
240 #define RT3883_FSCC_REG_CODEC_CFG1	0x44
241 
242 #define RT3883_FLASH_CFG_WIDTH_SHIFT	26
243 #define RT3883_FLASH_CFG_WIDTH_MASK	0x3
244 #define RT3883_FLASH_CFG_WIDTH_8BIT	0x0
245 #define RT3883_FLASH_CFG_WIDTH_16BIT	0x1
246 #define RT3883_FLASH_CFG_WIDTH_32BIT	0x2
247 
248 #define RT3883_SDRAM_BASE		0x00000000
249 #define RT3883_MEM_SIZE_MIN		2
250 #define RT3883_MEM_SIZE_MAX		256
251 
252 #endif /* _RT3883_REGS_H_ */
253