1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 22809b317SJohn Crispin /* 32809b317SJohn Crispin * 42809b317SJohn Crispin * Parts of this file are based on Ralink's 2.6.21 BSP 52809b317SJohn Crispin * 62809b317SJohn Crispin * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 72809b317SJohn Crispin * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 897b92108SJohn Crispin * Copyright (C) 2013 John Crispin <john@phrozen.org> 92809b317SJohn Crispin */ 102809b317SJohn Crispin 112809b317SJohn Crispin #ifndef _RT305X_REGS_H_ 122809b317SJohn Crispin #define _RT305X_REGS_H_ 132809b317SJohn Crispin 14418d29c8SJohn Crispin extern enum ralink_soc_type ralink_soc; 152809b317SJohn Crispin 162809b317SJohn Crispin static inline int soc_is_rt3050(void) 172809b317SJohn Crispin { 18418d29c8SJohn Crispin return ralink_soc == RT305X_SOC_RT3050; 192809b317SJohn Crispin } 202809b317SJohn Crispin 212809b317SJohn Crispin static inline int soc_is_rt3052(void) 222809b317SJohn Crispin { 23418d29c8SJohn Crispin return ralink_soc == RT305X_SOC_RT3052; 242809b317SJohn Crispin } 252809b317SJohn Crispin 262809b317SJohn Crispin static inline int soc_is_rt305x(void) 272809b317SJohn Crispin { 282809b317SJohn Crispin return soc_is_rt3050() || soc_is_rt3052(); 292809b317SJohn Crispin } 302809b317SJohn Crispin 312809b317SJohn Crispin static inline int soc_is_rt3350(void) 322809b317SJohn Crispin { 33418d29c8SJohn Crispin return ralink_soc == RT305X_SOC_RT3350; 342809b317SJohn Crispin } 352809b317SJohn Crispin 362809b317SJohn Crispin static inline int soc_is_rt3352(void) 372809b317SJohn Crispin { 38418d29c8SJohn Crispin return ralink_soc == RT305X_SOC_RT3352; 392809b317SJohn Crispin } 402809b317SJohn Crispin 412809b317SJohn Crispin static inline int soc_is_rt5350(void) 422809b317SJohn Crispin { 43418d29c8SJohn Crispin return ralink_soc == RT305X_SOC_RT5350; 442809b317SJohn Crispin } 452809b317SJohn Crispin 46*13a9d0beSSergio Paracuellos #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) 47*13a9d0beSSergio Paracuellos #define RT305X_SYSC_BASE IOMEM(0x10000000) 482809b317SJohn Crispin 492809b317SJohn Crispin #define SYSC_REG_CHIP_NAME0 0x00 502809b317SJohn Crispin #define SYSC_REG_CHIP_NAME1 0x04 512809b317SJohn Crispin #define SYSC_REG_CHIP_ID 0x0c 522809b317SJohn Crispin #define SYSC_REG_SYSTEM_CONFIG 0x10 532809b317SJohn Crispin 542809b317SJohn Crispin #define RT3052_CHIP_NAME0 0x30335452 552809b317SJohn Crispin #define RT3052_CHIP_NAME1 0x20203235 562809b317SJohn Crispin 572809b317SJohn Crispin #define RT3350_CHIP_NAME0 0x33335452 582809b317SJohn Crispin #define RT3350_CHIP_NAME1 0x20203035 592809b317SJohn Crispin 602809b317SJohn Crispin #define RT3352_CHIP_NAME0 0x33335452 612809b317SJohn Crispin #define RT3352_CHIP_NAME1 0x20203235 622809b317SJohn Crispin 632809b317SJohn Crispin #define RT5350_CHIP_NAME0 0x33355452 642809b317SJohn Crispin #define RT5350_CHIP_NAME1 0x20203035 652809b317SJohn Crispin 662809b317SJohn Crispin #define CHIP_ID_ID_MASK 0xff 672809b317SJohn Crispin #define CHIP_ID_ID_SHIFT 8 682809b317SJohn Crispin #define CHIP_ID_REV_MASK 0xff 692809b317SJohn Crispin 702809b317SJohn Crispin #define RT305X_SYSCFG_CPUCLK_SHIFT 18 712809b317SJohn Crispin #define RT305X_SYSCFG_CPUCLK_MASK 0x1 722809b317SJohn Crispin #define RT305X_SYSCFG_CPUCLK_LOW 0x0 732809b317SJohn Crispin #define RT305X_SYSCFG_CPUCLK_HIGH 0x1 742809b317SJohn Crispin 752809b317SJohn Crispin #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2 762809b317SJohn Crispin #define RT305X_SYSCFG_CPUCLK_MASK 0x1 772809b317SJohn Crispin #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1 782809b317SJohn Crispin 792809b317SJohn Crispin #define RT3352_SYSCFG0_CPUCLK_SHIFT 8 802809b317SJohn Crispin #define RT3352_SYSCFG0_CPUCLK_MASK 0x1 812809b317SJohn Crispin #define RT3352_SYSCFG0_CPUCLK_LOW 0x0 822809b317SJohn Crispin #define RT3352_SYSCFG0_CPUCLK_HIGH 0x1 832809b317SJohn Crispin 842809b317SJohn Crispin #define RT5350_SYSCFG0_CPUCLK_SHIFT 8 852809b317SJohn Crispin #define RT5350_SYSCFG0_CPUCLK_MASK 0x3 862809b317SJohn Crispin #define RT5350_SYSCFG0_CPUCLK_360 0x0 872809b317SJohn Crispin #define RT5350_SYSCFG0_CPUCLK_320 0x2 882809b317SJohn Crispin #define RT5350_SYSCFG0_CPUCLK_300 0x3 892809b317SJohn Crispin 908ddc2513SJohn Crispin #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12 918ddc2513SJohn Crispin #define RT5350_SYSCFG0_DRAM_SIZE_MASK 7 928ddc2513SJohn Crispin #define RT5350_SYSCFG0_DRAM_SIZE_2M 0 938ddc2513SJohn Crispin #define RT5350_SYSCFG0_DRAM_SIZE_8M 1 948ddc2513SJohn Crispin #define RT5350_SYSCFG0_DRAM_SIZE_16M 2 958ddc2513SJohn Crispin #define RT5350_SYSCFG0_DRAM_SIZE_32M 3 968ddc2513SJohn Crispin #define RT5350_SYSCFG0_DRAM_SIZE_64M 4 978ddc2513SJohn Crispin 982809b317SJohn Crispin /* multi function gpio pins */ 992809b317SJohn Crispin #define RT305X_GPIO_I2C_SD 1 1002809b317SJohn Crispin #define RT305X_GPIO_I2C_SCLK 2 1012809b317SJohn Crispin #define RT305X_GPIO_SPI_EN 3 1022809b317SJohn Crispin #define RT305X_GPIO_SPI_CLK 4 1032809b317SJohn Crispin /* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */ 1042809b317SJohn Crispin #define RT305X_GPIO_7 7 1052809b317SJohn Crispin #define RT305X_GPIO_10 10 1062809b317SJohn Crispin #define RT305X_GPIO_14 14 1072809b317SJohn Crispin #define RT305X_GPIO_UART1_TXD 15 1082809b317SJohn Crispin #define RT305X_GPIO_UART1_RXD 16 1092809b317SJohn Crispin #define RT305X_GPIO_JTAG_TDO 17 1102809b317SJohn Crispin #define RT305X_GPIO_JTAG_TDI 18 1112809b317SJohn Crispin #define RT305X_GPIO_MDIO_MDC 22 1122809b317SJohn Crispin #define RT305X_GPIO_MDIO_MDIO 23 1132809b317SJohn Crispin #define RT305X_GPIO_SDRAM_MD16 24 1142809b317SJohn Crispin #define RT305X_GPIO_SDRAM_MD31 39 1152809b317SJohn Crispin #define RT305X_GPIO_GE0_TXD0 40 1162809b317SJohn Crispin #define RT305X_GPIO_GE0_RXCLK 51 1172809b317SJohn Crispin 118bb19fea2SJohn Crispin #define RT3352_SYSC_REG_SYSCFG0 0x010 119bb19fea2SJohn Crispin #define RT3352_SYSC_REG_SYSCFG1 0x014 120bb19fea2SJohn Crispin #define RT3352_SYSC_REG_CLKCFG1 0x030 121bb19fea2SJohn Crispin #define RT3352_SYSC_REG_RSTCTRL 0x034 122bb19fea2SJohn Crispin #define RT3352_SYSC_REG_USB_PS 0x05c 123bb19fea2SJohn Crispin 124bb19fea2SJohn Crispin #define RT3352_CLKCFG0_XTAL_SEL BIT(20) 125bb19fea2SJohn Crispin #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) 126bb19fea2SJohn Crispin #define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) 127bb19fea2SJohn Crispin #define RT3352_RSTCTRL_UHST BIT(22) 128bb19fea2SJohn Crispin #define RT3352_RSTCTRL_UDEV BIT(25) 129bb19fea2SJohn Crispin #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) 130bb19fea2SJohn Crispin 131dafecee8SJohn Crispin #define RT305X_SDRAM_BASE 0x00000000 132dafecee8SJohn Crispin #define RT305X_MEM_SIZE_MIN 2 133dafecee8SJohn Crispin #define RT305X_MEM_SIZE_MAX 64 134dafecee8SJohn Crispin #define RT3352_MEM_SIZE_MIN 2 135dafecee8SJohn Crispin #define RT3352_MEM_SIZE_MAX 256 136dafecee8SJohn Crispin 1372809b317SJohn Crispin #endif 138