1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Parts of this file are based on Ralink's 2.6.21 BSP 5 * 6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 8 * Copyright (C) 2013 John Crispin <john@phrozen.org> 9 */ 10 11 #ifndef _RT288X_REGS_H_ 12 #define _RT288X_REGS_H_ 13 14 #define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) 15 #define RT2880_SYSC_BASE IOMEM(0x00300000) 16 17 #define SYSC_REG_CHIP_NAME0 0x00 18 #define SYSC_REG_CHIP_NAME1 0x04 19 #define SYSC_REG_CHIP_ID 0x0c 20 #define SYSC_REG_SYSTEM_CONFIG 0x10 21 #define SYSC_REG_CLKCFG 0x30 22 23 #define RT2880_CHIP_NAME0 0x38325452 24 #define RT2880_CHIP_NAME1 0x20203038 25 26 #define CHIP_ID_ID_MASK 0xff 27 #define CHIP_ID_ID_SHIFT 8 28 #define CHIP_ID_REV_MASK 0xff 29 30 #define SYSTEM_CONFIG_CPUCLK_SHIFT 20 31 #define SYSTEM_CONFIG_CPUCLK_MASK 0x3 32 #define SYSTEM_CONFIG_CPUCLK_250 0x0 33 #define SYSTEM_CONFIG_CPUCLK_266 0x1 34 #define SYSTEM_CONFIG_CPUCLK_280 0x2 35 #define SYSTEM_CONFIG_CPUCLK_300 0x3 36 37 #define CLKCFG_SRAM_CS_N_WDT BIT(9) 38 39 #define RT2880_SDRAM_BASE 0x08000000 40 #define RT2880_MEM_SIZE_MIN 2 41 #define RT2880_MEM_SIZE_MAX 128 42 43 #endif 44