1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * Copyright (C) 2015 John Crispin <john@phrozen.org> 7 */ 8 9 #ifndef _MT7621_REGS_H_ 10 #define _MT7621_REGS_H_ 11 12 #define MT7621_PALMBUS_BASE 0x1C000000 13 #define MT7621_PALMBUS_SIZE 0x03FFFFFF 14 15 #define MT7621_SYSC_BASE 0x1E000000 16 17 #define SYSC_REG_CHIP_NAME0 0x00 18 #define SYSC_REG_CHIP_NAME1 0x04 19 #define SYSC_REG_CHIP_REV 0x0c 20 #define SYSC_REG_SYSTEM_CONFIG0 0x10 21 #define SYSC_REG_SYSTEM_CONFIG1 0x14 22 #define SYSC_REG_CLKCFG0 0x2c 23 #define SYSC_REG_CUR_CLK_STS 0x44 24 25 #define MEMC_REG_CPU_PLL 0x648 26 27 #define CHIP_REV_PKG_MASK 0x1 28 #define CHIP_REV_PKG_SHIFT 16 29 #define CHIP_REV_VER_MASK 0xf 30 #define CHIP_REV_VER_SHIFT 8 31 #define CHIP_REV_ECO_MASK 0xf 32 33 #define XTAL_MODE_SEL_MASK 0x7 34 #define XTAL_MODE_SEL_SHIFT 6 35 36 #define CPU_CLK_SEL_MASK 0x3 37 #define CPU_CLK_SEL_SHIFT 30 38 39 #define CUR_CPU_FDIV_MASK 0x1f 40 #define CUR_CPU_FDIV_SHIFT 8 41 #define CUR_CPU_FFRAC_MASK 0x1f 42 #define CUR_CPU_FFRAC_SHIFT 0 43 44 #define CPU_PLL_PREDIV_MASK 0x3 45 #define CPU_PLL_PREDIV_SHIFT 12 46 #define CPU_PLL_FBDIV_MASK 0x7f 47 #define CPU_PLL_FBDIV_SHIFT 4 48 49 #define MT7621_DRAM_BASE 0x0 50 #define MT7621_DDR2_SIZE_MIN 32 51 #define MT7621_DDR2_SIZE_MAX 256 52 53 #define MT7621_CHIP_NAME0 0x3637544D 54 #define MT7621_CHIP_NAME1 0x20203132 55 56 #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8) 57 58 #endif 59